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Patent US6367066 - System for synthesizing a circuit by re-writing signed variables into ... - Google Patents
A circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language stores in advance translation rules for re-writing operations using signed variables into operations using unsigned...http://www.google.com/patents/US6367066?utm_source=gb-gplus-sharePatent US6367066 - System for synthesizing a circuit by re-writing signed variables into unsigned variables and sharing resources for identical operations having different timing
Publication number US6367066 B1
Application number US 09/237,256
Publication number 09237256, 237256, US 6367066 B1, US 6367066B1, US-B1-6367066, US6367066 B1, US6367066B1
Patent Citations (4), Non-Patent Citations (1), Referenced by (6), Classifications (7), Legal Events (8)
US 6367066 B1
A circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language stores in advance translation rules for re-writing operations using signed variables into operations using unsigned variables, detects operations using signed variables from a behavior description, extracts translation rules associated with the detected signed variables, re-writes said operations using signed variables into operations using unsigned variables according to the extracted translation rules, and based on said re-written behavior description, finds identical operations that do not behave in the same timing and carries out the process of sharing a functional unit.
1. A circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising the steps of:
re-writing behavior description by re-writing operations using signed variables within said behavior description into operations using unsigned variables; and
based on said re-written behavior description, finding identical operations that do not behave in the same timing and carrying out a process of sharing a functional unit for the variables thus found.
2. The circuit synthesizing method as set forth in claim 1, wherein
translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, and
operations using signed variables within said behavior description are re-written into operations using unsigned variables according to said translation rules.
3. The circuit synthesizing method as set forth in claim 1, wherein
translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance,
operations using signed variables are detected from said behavior description,
translation rules associated with the detected signed variables are extracted, and
said operations using signed variables are re-written into operations using unsigned variables according to the extracted translation rules.
4. The circuit synthesizing method as set forth in claim 1, wherein
when in said operation re-writing process, said operation is multiplication,
exclusive-ORs for the signed bits of said signed variables are obtained individually,
when the result of said exclusive-OR operation is 0, the result of multiplication for the variable is output as are, and
when the result of said exclusive-OR operation is 1, a negative sign is added to the result of multiplication for the variable.
5. The circuit synthesizing method as set forth in claim 1, wherein
translation rules associated with the detected signed variables are extracted,
6. A circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising the steps of:
finding variables that are not processed in a same timing from said behavior description;
comparing a bit count of the variable to a bit count of a register to be shared,
wherein if the bit count of the variable is less than the bit count of the register to be shared,
adding same data as the signed bits, in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register; and
adding pre-determined data, in the case of an unsigned variable, in the number of bits by which the number of bits in the unsigned variable is less than the number of bits in the register, and then carrying out the process of sharing a register.
7. The circuit synthesizing method as set forth in claim 6, wherein “0s” are added as the pre-determined data.
8. A circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising the steps of:
finding identical operations, based on said re-written behavior description, that do not behave in the same timing and carrying out a process of sharing a functional unit for the variables thus found;
finding variables that are not processed in the same timing from said behavior description,
comparing a bit count of the variable to a bit count of the register to be shared,
9. The circuit synthesizing method as set forth in claim 8, wherein
said operations using signed variables within said behavior description are re-written into operations using unsigned variables according to said translation rules.
10. The circuit synthesizing method as set forth in claim 8, wherein “0s” are added as the pre-determined data.
11. A circuit synthesizing device for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising:
re-writing means for re-writing operations using signed variables within said behavior description into operations using unsigned variables; and
means for sharing a functional unit for performing identical operations that do not behave in the same timing from the re-written description.
12. The circuit synthesizing device as set forth in claim 11, further comprising
translation table storing means in which translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, and
said operation re-writing means
re-writes operations using signed variables within said description into operations using unsigned variables according to the translation rules that are stored in said translation table storing means.
13. The circuit synthesizing device as set forth in claim 11, further comprising
translation table storing means in which translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance,
detects operations using signed variables from said behavior description,
extracts translation rules associated with the detected signed variables from said translation table storing means, and
re-writes said operations using signed variables into operations using unsigned variables according to the extracted translation rules.
14. The circuit synthesizing device as set forth in claim 11, wherein
obtains exclusive-ORs for the signed bits of said signed variables individually,
when the result of said exclusive-OR operation is 0, outputs the result of multiplication for the variable as are, and
when the result of said exclusive-OR operation is 1, adds a negative sign to the result of multiplication for the variable.
15. The circuit synthesizing device as set forth in claim 11, further comprising
extracts translation rules associated with the detected signed variables from said translation table storing means,
16. A circuit synthesizing device for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising:
means for finding variables that are not processed in the same timing from said behavior description;
means for comparing a bit count of the variable to a bit count of the register to be shared,
wherein if the bit count of the variable is less than the bit count of the register to be shared, adding the same data as the signed bits, in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and adding pre-determined data, in the case of an unsigned variable, in the number of bits by which the number of bits in the unsigned variable is less than the number of bits in the register; and
means for, after adding data to said variables, carrying out the process of sharing a register.
17. The circuit synthesizing device as set forth in claim 16, wherein “0s” are added as the pre-determined data.
18. A circuit synthesizing device for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising:
means for re-writing behavior description by re-writing operations using signed variables within said behavior description into operations using unsigned variables;
means for finding identical operations, based on said re-written behavior description, that do not behave in the same timing and carrying out a process of sharing a functional unit for the variables thus found;
means for adding same data as the signed bits, in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bit s in the register and adding pre-determined data in the number of bits that are in short in the case of an unsigned variable, comparing a bit count of the variable to a bit count of the register to be shared; and
19. The circuit synthesizing device as set forth in claim 18, further comprising
20. A computer readable memory that records a circuit synthesizing program for synthesizing a circuit from a behavior description indicating the behavior of a circuit that is created by a computer in a hardware description language, wherein said circuit synthesizing program causes said computer to carry out the processes of:
re-writing operations using signed variables within said behavior description into operations using unsigned variables; and
sharing a functional unit for performing identical operations that do not behave in the same timing from a description that has been re-written in said translation process.
21. The computer readable memory as set forth in claim 20, wherein said circuit synthesizing program
stores in advance translation rules for re-writing operations using signed variables into operations using unsigned variables, and
re-writes said operations using signed variables within said behavior description into operations using unsigned variables according to said translation rules.
22. The computer readable memory as set forth in claim 20, wherein said circuit synthesizing program
stores in advance translation rules for re-writing operations using signed variables into operations using unsigned variables,
extracts translation rules associated with the detected signed variables, and
23. The computer readable memory as set forth in claim 20, wherein said circuit synthesizing program
24. The computer readable memory as set forth in claim 20, wherein said circuit synthesizing program
stores in advance translation rules for rewriting operations using signed variables into operations using unsigned variables,
extracts translation rules associated with the detected signed variables,
25. A computer readable memory that records a circuit synthesizing program for synthesizing a circuit from a behavior description indicating the behavior of a circuit that is created by a computer in a hardware description language, wherein said circuit synthesizing program causes said computer to carry out a process of:
finding variables that are not processed in the same timing from said behavior description;
26. The computer readable memory as set forth in claim 25, wherein said circuit synthesizing program adds “0s” as the pre-determined data.
27. A circuit synthesizing device for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising:
a data processor configured to find variables that are not processed in the same timing from said behavior description;
said data processor configured to compare a bit count of the variable to the bit count of the register to be shared,
wherein if the bit count of the variable is less than the bit count of the register to be shared, add same data as the signed bits, in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and adding pre-determined data, in the case of an unsigned variable, in the number of bits by which the number of bits in the unsigned variable is less than the number of bits in the register,
said data processor to carry out the process of sharing a register, after adding data to said variables.
The present invention relates to a circuit synthesizing method for LSIs and other types of integrated circuit devices and a circuit synthesizing device therefor, and more particularly to a circuit synthesizing method for enabling to synthesize a circuit with a small circuit area and to a circuit synthesizing device therefor.
In recent years, LSIs in general have become larger in size and more complex in structure, leading to increasing demand for a system that can automate logical design in order to achieve higher efficiency in LSI design. As a means of realizing automated circuit design, a circuit synthesizing device has been provided for describing the behavior of a circuit using the hardware description language and then synthesizing a desired circuit according to the description that has been input.
In general, the design levels of circuit synthesizing devices consist of three types: behavior, RTL (Register Transfer Level), and logic.
The behavior level is the same level as considering an algorithm using the programming language, which is a design level for defining “what” behaves “how.” In behavior synthesis, scheduling is performed to determine the clock cycle and the procedure in which an operation is to be carried out on a behavior description. As a result of this scheduling, registers and functional units are allocated to variables and registers (i.e., binding) as necessary, and a state machine part for controlling the sequence of the operation is generated (i.e., state generation).
The RTL is a level one order below the behavior level. This level defines an architecture using such components as registers, functional units, and a state machine part, and clarifies the behaviors of individual clock cycles. Actions in RTL synthesis include inferring registers from descriptions, optimizing the operational sequence, and allocating resources.
The logic level is the lowest level, which expresses a design circuit using Boolean expressions, ASIC net lists, and so forth. The term “logic synthesis” usually refers to synthesis at the logic level.
It should be noted here that a functional unit very often has a large circuit area. When synthesizing a circuit, therefore, sharing of a functional unit that is not used simultaneously is desirable so that the area of a logic-synthesized circuit can be prevented from becoming too large.
As an example, we will take the case in which the following is input into a circuit synthesizing device as a behavior description:
unsigned a1(0:2),b1(0:2),c1(0:4);
unsigned a2(0:3),b2(0:3),c2(0:6);
cl=a1*b1;
where a1 and b1 are unsigned variables that have 2 bits in total beginning with 0 bit, respectively; c1 is an unsigned variable that has 4 bits in total beginning with 0 bit; a2 and b2 are unsigned variables that have 3 bits in total beginning with 0 bit, respectively; and c2 is an unsigned variable that has 6 bits in total beginning with 0 bit. if(cond) else represents a process for selecting either of c1 or c2, depending on the state specified by the value of cond. While the behavior description above shows an example of a description that performs an operation using unsigned variables, there are also descriptions that perform operations using signed variables.
When carrying out behavior synthesis based on a behavior description similar to the one shown above, conventional circuit synthesizing devices first find operations that are identical to each other but are not used in the same timing in the behavior description, and cause these operations to share the functional unit that are associated with them. Thus, in the behavior description shown above, the operations c1=a1*b1 and c2=a2*b2 are not carried out simultaneously, so a behavior is so synthesized as to carry out a1*b1 and a2*b2 separately, using the same functional unit (i.e., a multiplier).
One example of the results of behavior synthesis according to the procedure described above is shown in FIG. 7.
FIG. 7 shows an example of the results of behavior synthesis that is output from a conventional circuit synthesizing device. In FIG. 7, “MUX” represents a multiplexer and “×” a multiplier (i.e., a functional unit).
As shown in FIG. 7, the number of multiplexers for switching variables to be input into a functional unit increases within a behavior-synthesized description. Even so, the area of the synthesized circuit can be reduced, since each multiplexer requires a smaller circuit area than a functional unit.
In conventional circuit synthesizing device, not only functional units but also registers are shared. Register sharing herein means to have one register to hold multiple pieces of data (variables) that are not processed in the same timing.
FIGS. 8 and 9 are data transfer diagrams showing an example of a register sharing method in a conventional circuit synthesizing device conducts. Of these, FIG. 8 is a block diagram showing a register sharing method for signed variables, and FIG. 9 showing a register sharing method for unsigned variables.
FIGS. 8 and 9 show the register sharing method that is conducted when transferring the value of the variable a1 to the register c1 and the value of the variable b1 to the register c2, as follows:
Here, the registers c1 and c2 are implemented (i.e., shared) in one register (5 bits).
For example, as shown in FIG. 8, when transferring a1, which is a 2-bit signed variable, and b1, which is a 4-bit signed variable, to a common register (5 bit), bits are added to the variables a1 and b1, respectively, in the numbers that are less than the bit count of the destination register. The multiplexer (MUX) then switches the variable to be transferred to the register, between a1 and b1. Here, since the 0th bit of the variable a1 and that of the variable b1 are signed bits, the same data as the signed bits are inserted in the bits that are in short.
On the other hand, as shown in FIG. 9, for example, when transferring a2, which is a 4-bit unsigned variable, and b2, which is a 2-bit unsigned variable, to a common register (5 bit), bits are added to the variables a2 and b2, respectively, in the numbers that are less than the bit count of the destination register, as with the case above for signed bits. The multiplexer (MUX) then switches the variable to be transferred to the register, between a2 and b2. Here, since neither the variable a2 nor b2 holds a signed bit, data “0s” are inserted to the number of bits that are less than the number of bits in the register.
Thus, by conducting sharing for not only functional units but also for registers, a reduction in circuit area can be realized.
Generally, in a conventional circuit synthesizing device as described above, a behavior description is created by employing either operations using signed variables or operations using unsigned variables. However, for cases in which two types of operations, i.e., those using signed variables and those using unsigned variables, exist in the same behavior description, two types of functional units are required, making it impossible to share these functional units.
Thus, conventional circuit synthesizing devices have a drawback that the area of a circuit cannot be minimized in design, since full sharing of functional units and registers are not possible.
An objective of the present invention is to provide a circuit synthesizing device that can synthesize a circuit with a small circuit area by enabling sharing of functional units and registers even when both operations using signed variables and unsigned variables exist, and a method therefor.
Another objective of the present invention is to provide a circuit synthesizing device that can perform simulation of circuit behavior and other processes at a higher speed by using C language for describing hardware in which both operations using signed variables and unsigned variables exist, and a method therefor.
According to the first aspect of the invention, a circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising the steps of
re-writing operations using signed variables within the behavior description into operations using unsigned variables, and
based on the re-written behavior description, finding identical operations that do not behave in the same timing and carrying out the process of sharing a functional unit for the variables thus found.
In the preferred construction, translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, and operations using signed variables within the behavior description are re-written into operations using unsigned variables according to the translation rules.
In another preferred construction, translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, operations using signed variables are detected from the behavior description, translation rules associated with the detected signed variables are extracted, and the operations using signed variables are re-written into operations using unsigned variables according to the extracted translation rules.
In another preferred construction, when in the operation re-writing process, the operation is multiplication, exclusive-ORs for the signed bits of the signed variables are obtained individually,
when the result of the exclusive-OR operation is 0, the result of multiplication for the variable is output as are, and
when the result of the exclusive-OR operation is 1, a negative sign is added to the result of multiplication for the variable.
In another preferred construction, translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, operations using signed variables are detected from the behavior description, translation rules associated with the detected signed variables are extracted,
when in the operation re-writing process, the operation is multiplication,
exclusive-ORs for the signed bits of the signed variables are obtained individually,
According to the second aspect of the invention, a circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising the steps of
finding variables that are not processed in the same timing from the behavior description,
comparing a bit count of the variable to the bit count of the register to be shared,
adding same data as the signed bits, in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and
adding pre-determined data, in the case of an unsigned variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and then carrying out the process of sharing a register.
According to the third aspect of the invention, a circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising the steps of
based on the re-written behavior description, finding identical operations that do not behave in the same timing and carrying out the process of sharing a functional unit for the variables thus found,
In the preferred construction, translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, and the operations using signed variables within the behavior description are re-written into operations using unsigned variables according to the translation rules.
In another preferred construction, “0s” are added as the pre-determined data, in the number of bits that is the difference between the number of bits in the unsigned variables and the number of bits in the register, in the case of an unsigned variable.
According to the fourth aspect of the invention, a circuit synthesizing device for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising
re-writing means for re-writing operations using signed variables within the behavior description into operations using unsigned variables, and
In the preferred construction, the circuit synthesizing device further comprises translation table storing means in which translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, and
the operation re-writing means re-writes operations using signed variables within the description into operations using unsigned variables according to the translation rules that are stored in the translation table storing means.
In another preferred construction, the circuit synthesizing device further comprises translation table storing means in which translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance,
the operation re-writing means detects operations using signed variables from the behavior description, extracts translation rules associated with the detected signed variables from the translation table storing means, and re-writes the operations using signed variables into operations using unsigned variables according to the extracted translation rules.
In another preferred construction, the operation re-writing means, when in the operation re-writing process, the operation is multiplication, obtains exclusive-ORs for the signed bits of the signed variables individually, when the result of the exclusive-OR operation is 0, outputs the result of multiplication for the variable as are, and when the result of the exclusive-OR operation is 1, adds a negative sign to the result of multiplication for the variable.
the operation re-writing means detects operations using signed variables from the behavior description, extracts translation rules associated with the detected signed variables from the translation table storing means,
when in the operation re-writing process, the operation is multiplication, obtains exclusive-ORs for the signed bits of the signed variables individually,
when the result of the exclusive-OR operation is 0, outputs the result of multiplication for the variable as are, and when the result of the exclusive-OR operation is 1, adds a negative sign to the result of multiplication for the variable.
According to the fifth aspect of the invention, a circuit synthesizing device for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprises:
means for finding variables that are not processing in the same timing from the behavior description,
means for, comparing a bit count of the variable to the bit count of the register to be shared,
wherein if the bit count of the variable is less than the bit count of the register to be shared, add the same data as the signed bits, in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and adding predetermined data, in the case of an unsigned variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and
In the preferred construction, “0s” are added as the pre-determined data, in the number of bits that are in short, in the case of an unsigned variable.
According to the sixth aspect of the invention, a circuit synthesizing device for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising
means for re-writing operations using signed variables within the behavior description into operations using unsigned variables,
means for, based on the re-written behavior description, finding identical operations that do no behave in the same timing and carrying out the process of sharing a functional unit for the variables thus found,
means for finding variables that are not processed in the same timing from the behavior description,
means for comparing a bit count of the variable to the bit count of the register to be shared,
adding pre-determined data, in the case of an unsigned variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register to be shared, and
means for, after adding data to the variables, carrying out the process of sharing a register.
In the preferred construction, the circuit synthesizing device further comprises translation table storing means in which translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, and the operation re-writing means re-writes operations using signed variables within the description into operations using unsigned variables according to the translation rules that are stored in the translation table storing means.
According to a further aspect of the invention, a computer readable memory that records a circuit synthesizing program for synthesizing a circuit from a behavior description indicating the behavior of a circuit that is created by a computer in a hardware description language, wherein the circuit synthesizing program causes the computer to carry out a process of
finding variables that are not processed in the same timing from the behavior description;
adding same data as the signed bits in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and
adding pre-determined data in the case of an unsigned variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and then carrying out the process of sharing a register.
According to a further aspect of the invention, a computer readable memory that records a circuit synthesizing program for synthesizing a circuit from a behavior description indicating the behavior of a circuit that is created by a computer in a hardware description language, wherein the circuit synthesizing program causes the computer to carry out the processes of
when the bit count of the variable is in short when compared with the bit count of the register to be shared,
adding the same data as the signed bits in the number of bits that are in short in the case of a signed variable, and
adding the pre-determined data in the number of bits that are in short in the case of an unsigned variable, and then carrying out the process of sharing a register.
FIG. 1 is a block diagram showing the configuration of a circuit synthesizing device according to the present invention;
FIG. 2 is a flow chart showing the processing procedure for the circuit synthesizing method carried out by a circuit synthesizing device according to the present invention;
FIG. 3 is a diagram showing an example of a translation table equipped with a circuit synthesizing device according to the present invention;
FIG. 4 is a diagram showing an example of the results of behavior synthesis that is output from a circuit synthesizing device according to the present invention;
FIG. 5 is a flow chart explaining a register sharing method in a circuit synthesizing device according to the present invention;
FIG. 6 is a block diagram showing an example of a register sharing method in a circuit synthesizing device according to the present invention;
FIG. 7 is a diagram showing an example of the results of behavior synthesis that is output from a conventional circuit synthesizing device according to the present invention;
FIG. 8 is a data transfer diagram showing an example of a register sharing method for signed variables in a conventional circuit synthesizing device;
FIG. 9 is a data transfer diagram showing an example of a register sharing method for unsigned variables in a conventional circuit synthesizing device.
A circuit synthesizing device according to the present invention enables a functional unit to be shared between an operation using signed variables and an operation using unsigned variables that are not processed in the same timing. Although the following describes a case in which behavior synthesis is conducted from a behavior description, this can also be applied to cases in which RTL synthesis is conducted from an RTL description.
FIG. 1 is a block diagram showing the configuration of a circuit synthesizing device according to an embodiment of the present invention.
In FIG. 1, the circuit synthesizing device includes the following components as components comprising the computer: input devices 10 for inputting behavior descriptions, output devices 20 for outputting the results of behavior synthesis, a hard disk 30 for storing behavior descriptions that have been input and the results of behavior synthesis, a memory 40 for holding data required for behavior synthesis, a storage medium 50 in which a program for performing behavior synthesis is recorded, a data processor 60 for executing behavior synthesis according to the program recorded in the storage medium 50, a bus 70 for connecting the input devices 10, such as a keyboard, the output device 20, such as a display and a printer, the hard disk 30, the memory 40, the storage medium 50, and the data processor 60.
The data processor 60 reads a program recorded in the storage medium 50, and executes a process, which will be described later, according to the program. The storage medium 50 herein may be a magnetic disk, a semi-conductor memory, a CD-ROM, or other recording means.
The memory 40 is provided with a translation table 100, which will be described later. In the translation table 100, translation rules for translating operations using signed variables into operations using unsigned variables are stored in advance.
The data processor 60 finds operations using signed variables in a behavior description, translates the operations using signed variables to operations using unsigned variables according to the translation rules stored in the translation table 100, and performs behavior synthesis based on the behavior description thus translated.
Next, the operation of a circuit synthesizing device according to the present embodiment will be described with reference to FIGS. 2 to 5.
FIG. 2 is a flow chart showing the processing procedure for the circuit synthesizing method carried out by a circuit synthesizing device according to the present invention.
In FIG. 2, after a behavior description is input by the operator to direct the computer to conduct behavior synthesis, the data processor 60 translates the behavior description stored in the hard disk 30 into a processable data format, and transfers the results to the memory 40 (Step 201).
The data processor 60 then searches the behavior description stored in the memory 40 for operations using signed variables (Step 202). When it finds signed variables within the behavior description, it references the translation table 100 stored in the memory 40 and extracts the applicable translation rules from the translation table 100 (Step 203).
The data processor 60 then re-writes the behavior description by translating the operations using signed variables into operations using unsigned variables according to the extracted translation rules (Step 204).
The data processor 60 then carries out scheduling according to the re-written behavior description (Step 205), and completes behavior synthesis by performing sharing of a functional unit, allocation of a register, binding, and state generation (Step 206). The results of behavior synthesis (e.g., an RTL description) is stored in the hard disk 30 (Step 207), and output in response to a request from the operator using the output device 20.
The process of enabling a functional unit to be shared is the same as the process in a conventional circuit synthesizing device; it finds operations that are identical to each other but are not used in the same timing from a behavior description, and cause these operations to share the associated functional unit.
When no signed variables are found within the behavior description during the process of Step 202, on the other hand, the processor proceeds to the scheduling process of Step 205 to perform scheduling according to the input behavior description. The processes thereafter are the same as Steps 206 and 207 described above.
The operation of a circuit synthesizing device according to the present invention will be described in greater detail with reference to FIGS. 3 to 5.
signed a1(0:3),b1(0:3),c1(0:6);
where a1 and b1 are signed variables that have 3 bits in total beginning with 0 bit, respectively; c1 is a signed variable that has 6 bits in total beginning with 0 bit; a2 and b2 are unsigned variables that have 3 bits in total beginning with 0 bit, respectively; and c2 is an unsigned variable that has 6 bits in total beginning with 0 bit. if(cond) else represents a process for selecting either of c1 or c2, depending on the state specified by the value of cond.
In this example, when the translation rules of a multiplier as shown in FIG. 3 is stored in the translation table 100 that are stored in the memory 40, the behavior description described above is translated as follows:
c1=(a1(0) XOR b1(0)) ? a1(1:2)*b1(1:2): −(a1(1:2)*b1(1:2));
c1=(a1(0) XOR b1(0)) ? a1(1:2)*b1(1:2): −(a1(1:2)*b1(1:2)); represents the process in which either a1 (1:2)* b1 (1:2) or −(a1 (1:2)* b1 (1:2)) is selected depending on the result of the exclusive-OR of a1 (0) and b1 (0) (exclusive-OR between signed bits). If the result of the exclusive-OR of a1 (0) and b1 (0) is “0”, the left-hand expression, a1 (1:2)* b1 (1:2) is selected since the signs of the variables a1 and b1 are the same; if the result of the exclusive-OR of a1 (0) and b1 (0) is “1”, the right-hand expression, −(a1 (1:2)* b1 (1:2)), is selected since the signs of the variables a1 and b1 are not the same.
The results of behavior synthesis according to the translated behavior description will be as shown in FIG. 4. FIG. 4 is a diagram showing an example of the results of behavior synthesis that is output from a circuit synthesizing device according to the present invention. In FIG. 4, “XOR” represents an exclusive-OR, “MUX” a multiplexer, and “×” a multiplier (a functional unit), respectively.
As shown in FIG. 4, a description in which a behavior is synthesized has a greater number of exclusive-ORs, negative signs inserted, and multiplexer modules after the insertion of negative signs when compared to conventional methods. Even so, the area of the synthesized circuit can be reduced, since each of these modules requires a smaller circuit area than a functional unit.
Furthermore, even when both operations using signed variables and operations using unsigned variables exist in a behavior description, a circuit synthesizing device according to the present invention can use C language as a hardware description language since sharing of a functional unit is possible. A behavior description written in C language can perform the synthesis process faster than a behavior description created using such well-known hardware description language as VHDL and Verilog-HDL. This is also true with simulations and other processes of a circuit behavior.
Next, the method of sharing a register in a circuit synthesizing device according to the present invention will be described.
In conventional circuit synthesizing devices, as shown in FIGS. 7 and 8, data that are not used in the same timing are stored in the same register, for each signed variable or unsigned variable.
In a circuit synthesizing device according to the present invention, on the other hand, it is possible to store data that are not used in the same timing for signed and unsigned variable in the same register collectively.
The operation of the circuit synthesizing device when sharing a register will be described with reference to the flow chart of FIG. 5.
In FIG. 5, after a behavior description is input by the operator to direct the computer to conduct behavior synthesis, the data processor 60 translates the behavior description stored in the hard disk 30 into a processable data format, and transfers the results to the memory 40 (Step 501).
The data processor 60 then finds variables that are not processed in the same timing from the behavior description stored in the memory 40 (Step 502).
If the bit count of the variable thus found is less than, in the bit count of the register to be shared, the processor adds pre-determined data, in the number of bits (a short number of bits), by which the bit count of the variable is less than the bit count of the register, to the variable (Step 503). More specifically, if the variable is a signed one, the same data as the signed bits, in the short number of bits, are added to the variable; if the variable is an unsigned one, the pre-determined data, in the short number of bits, are added to the variable.
The data processor 60 then carries out scheduling according to the translated behavior description (Step 504), and completes behavior synthesis by performing sharing of a functional unit, allocation of a register, binding, and state generation (Step 505). The results of behavior synthesis (e.g., an RTL description) is stored in the hard disk 30 (Step 506), and output in response to a request from the operator using the output device 20.
FIG. 6 is a block diagram showing an example of a register sharing method in a circuit synthesizing device according to the present invention.
FIG. 6 shows the register sharing method that is conducted when transferring the value of the variable a1 to the register c1 and the value of the variable a2 to the register c2, as follows:
In FIG. 6, for example, when transferring al, which is a 2-bit signed variable, and a2, which is a 4-bit unsigned variable, to a common register (5 bits), bits are added to the variables a1 and a2, respectively, in the numbers that are less than the bit count of the destination register when compared. The multiplexer (MUX) then switches the variable to be transferred to the register, between a1 and a2. Here, since the 0th bit of the variable a1 is a signed bit, the same data as the signed bits are inserted in the bits that are less than the number of bits in the register. On the other hand, since the variable a2 does not hold a signed bit, data “0s” are inserted to the bits that are in short.
Thus, a circuit synthesizing device according to the present invention can reduce a synthesized circuit in circuit area, since it can conduct sharing for not only functional units but also for registers for a description in which both signed variables and unsigned variables exist.
Furthermore, it is also possible to combine sharing of a functional unit as shown in FIG. 2 and sharing of a register as shown in FIG. 5.
Since the present invention is configured as the foregoing, it can offer the effects as described below:
A circuit synthesizing device as described above can reduce a synthesized circuit in circuit area since it can conduct sharing of a functional unit even for a description in which both signed variables and unsigned variables exist by re-writing operations using signed variables within a description into unsigned variables and then sharing a functional unit for performing identical operations from the re-written description that do not behave in the same timing.
Such a circuit synthesizing device can perform simulation of circuit behavior and other processes at a higher speed by using C language for describing hardware in which both operations using signed variables and unsigned variables exist.
Furthermore, such a circuit synthesizing device can reduce a synthesized circuit in circuit area since it can conduct sharing of a register even for a description in which both signed variables and unsigned variables exist by sharing a register after finding variables that are not processed in the same timing from a description and, if the bit count of the variable thus found is less than the bit count of the register to be shared, adding the same data as the signed bits in the number of bits (a short number of bits) by which the bit count of the variable is less than the bit count of the register in the case of a signed variable and the pre-determined data in the number of bits (a short number of bits) in the case of an unsigned variable.
1 * Burgess, N., "Removal of sign-extension circuitry from Booth's algorithm multiplier-accumulators", IEEE, pp. 1413-1415.
US8839163 * Nov 5, 2012 Sep 16, 2014 Renesas Electronics Corporation Behavioral synthesis method, behavioral synthesis program and behavioral synthesis apparatus
US20130132916 * Nov 5, 2012 May 23, 2013 Renesas Electronics Corporation Behavioral synthesis method, behavioral synthesis program and behavioral synthesis apparatus
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SATO, KOICHI;REEL/FRAME:009744/0957


text:
Patent US7153159 - Coaxial cable connector with pop-out pin - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn electrical connector having a front end for attachment to a terminal and a back end for attachment to a coaxial cable includes a body, a post mounted within the body; and a contact assembly movably mounted within the post. The contact assembly includes a guide, a pin mounted to the guide, and a clip...http://www.google.com/patents/US7153159?utm_source=gb-gplus-sharePatent US7153159 - Coaxial cable connector with pop-out pinAdvanced Patent SearchPublication numberUS7153159 B2Publication typeGrantApplication numberUS 11/036,443Publication dateDec 26, 2006Filing dateJan 14, 2005Priority dateJan 14, 2005Fee statusPaidAlso published asCN100508288C, CN101111974A, DE602006006970D1, EP1836747A1, EP1836747B1, US7303435, US20060160416, US20070105439, WO2006076440A1Publication number036443, 11036443, US 7153159 B2, US 7153159B2, US-B2-7153159, US7153159 B2, US7153159B2InventorsDonald Andrew Burris, William B. LutzOriginal AssigneeCorning Gilbert Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (18), Non-Patent Citations (4), Referenced by (25), Classifications (7), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetCoaxial cable connector with pop-out pin
US 7153159 B2Abstract
a pin fixedly mounted to the guide, the pin having a front end and a back end, wherein the back end defining a bore, and
a clip mounted within the bore for making electrical and mechanical contact with the center conductor of the coaxial cable, the clip fixedly mounted to the back end of the pin;
7. An axially compressible connector for attachment to a coaxial cable, the coaxial cable comprising a center conductor and a dielectric layer surrounding the center conductor, the axially compressible connector comprising:
8. The axially compressible connector of claim 7, in which a back side of the guide has an opening at the longitudinal axis for receiving the center conductor of the coaxial cable.
9. The axially compressible connector of claim 8, in which the back side of the guide is funnel-shaped to guide the center conductor of the coaxial cable toward the opening in the guide.
10. The axially compressible connector of claim 8, in which the dielectric layer of the coaxial cable moves the contact assembly.
11. The axially compressible connector of claim 8, in which the opening in the guide is viewable to a user during attachment until the center conductor of the coaxial cable enters the opening.
12. The axially compressible connector of claim 7, in which a back side of the guide is funnel-shaped with an opening at the longitudinal axis for receiving the center conductor of the coaxial cable, such that the dielectric layer, and not the center conductor, of the coaxial cable moves the contact assembly.
Disadvantageously, most known connectors require �blind entry� of the coaxial cable into the connector, meaning that a small opening in the connector into which it is necessary to insert the center conductor of the coaxial cable becomes blocked from a user's view by a dielectric or jacket of the coaxial cable. The dielectric or jacket blocks the user's view of the small opening primarily because the small opening is disadvantageously recessed too deeply in the connector. Such known connectors provide no means to ensure that the dielectric, or foam core, of the coaxial cable is properly centered within the connector during insertion of the coaxial cable into the connector.
It is therefore an object of the present invention to provide a coaxial connector that is more �installer friendly� and incorporates a positive visual indication that the connector is properly installed on a coaxial cable.
FIG. 1 is a perspective view of an axially-compressible RCA connector 100 in accordance with a preferred embodiment of the present invention. FIG. 1 shows the RCA connector 100 prior to attachment together of the RCA connector and a coaxial cable. FIG. 1 shows the RCA connector 100 as it preferably appears prior to use, such as during transport, or shipment, and during storage, hereinafter an �as shipped� state. The RCA connector 100 is generally tubular, and has a front end 101, a back end 102, and a central longitudinal axis 103. The front end 101 is for removable attachment to a terminal (not shown). The back end 102 is for attachment to a coaxial cable. The RCA connector 100 comprises a compression ring 110 that is generally tubular shaped. Preferably, the compression ring 110 is plastic. A tubular shaped shell 112 is mounted to the compression ring 110. Preferably, the shell 112 is metallic. The compression ring 110 is mounted onto a body 114, preferably by a press-fit. Preferably, the body 114 is metallic. A generally tubular shaped post 116 is mounted within the body 114. Preferably, the post 116 is metallic. A generally tubular shaped guide 118 is mounted within the post 116. Preferably, the guide 118 is a dielectric. The compression ring 110, shell 112, body 114, post 116 and guide 118 share the same longitudinal axis 103. A small opening in the guide 118 near the back end 102 of the RCA connector 100 at the longitudinal axis 103 forms a target 120 that is advantageously near the back end 102 of the RCA connector 100.
FIG. 2 is a perspective view of the RCA connector 100 showing the front end 101 of the RCA connector, prior to attachment together of the RCA connector and a coaxial cable. FIG. 2 shows the RCA connector 100 in the preferred �as shipped� state. The RCA connector 100 includes a pin 200 that is an integral part of the RCA connector, when shipped. Advantageously, the pin 200 does not extend beyond the front end 101 of the RCA connector 100 when in the �as shipped� state. As a result, the body 114 of the RCA connector 100 protects the pin 200 from damage during shipment.
FIG. 4 is a partial cross-sectional view of the RCA connector 100 and a side view of the cable 300, prior to attachment together. FIG. 4 shows the RCA connector 100 in the same preferred �as shipped� state as shown in FIG. 2, with a prepared cable 300 ready for insertion. Advantageously, the tip of pin 200 is recessed within the body 114 during shipment. The RCA connector 100 includes an insulator body 401 that supports a front portion of the pin 200 and maintains the pin at the longitudinal axis 103 of the RCA connector 100. The insulator body 401 is a generally tubular support made of electrically insulative material. The pin 200 has an inner surface defining a cylindrical bore along the longitudinal axis 103 of the pin. The bore extends into the pin 200 from the back end of the pin, and the bore has a length approximately one-third the length of the pin. The bore includes a wider portion 406 nearest the back end of the pin 200, and a narrower portion 407 farther from the back end of the pin. The RCA connector 100 includes spring clip, or clip, 402 mounted within the wider portion 406 of the bore. A contact assembly 800 (see FIG. 8) includes the guide 118, the pin 200 and the clip 402. The contact assembly 800 is capable of moving longitudinally, as a unit, relative to the body 114. A label 403 (not indicated in FIG. 1, 2 or 3) is optionally affixed to the outer surface of the shell 112. The cable 300 comprises a center conductor 431, surrounded by a dielectric layer, such as a foam core, 432, surrounded by an outer conductor 433, surrounded by a jacket 434.
FIG. 7 is a partial cross-sectional view of the RCA connector 100 and the cable 300, assembled together, with the pin 200 remaining in the fully popped out position. FIG. 7 shows the compression ring 110, moved into a closed position, which sandwiches the outer conductor 433 and the jacket 434 of the cable 300 with the post 116. In FIG. 7, the RCA connector 100 is shown in an �in use� state. In FIGS. 6 and 7, a front portion of the pin 200 extends beyond the front end 101 of the RCA connector 100.
FIG. 9 is a further enlarged, perspective view of the clip 402. The clip is mounted, preferably by press-fit, in the wider portion 406 of the bore of the pin 200. The clip 402 includes four (4) tines 911�914 at a front end 915 of the clip 402 each one configured to grip the center conductor 431 of the cable 300 with spring action. A back end 916 of the clip 402 makes contact with the wall of the wider portion 406 of the bore of the pin 200, preferably with a snug fit of the clip within the bore of the pin. Therefore, positive electrical and mechanical engagement is maintained between the pin 200 of the RCA connector 100 and the center conductor 431 of the cable 300 by means of the clip 402. The structure of the guide 118 and the pin 200 is pre-selected to provide a desired impedance range between the body 114 and the pin 200, at a desired radio frequency operating range. The impedance of the connectors in accordance with the invention is nominally 75-ohms. The desired radio frequency operating range of the RCA connector 100 is the audio frequencies. The desired radio frequency operating range of other connectors in accordance with the invention includes frequencies up to 3-GHz.
FIG. 10 is a perspective view of an axially-compressible BNC connector 1000 showing a back end 1002 of the BNC connector, prior to attachment onto the cable 300. FIG. 10 shows the BNC connector 1000 in the preferred �as shipped� state. The BNC connector 1000 is generally tubular, and has a front end 1001, a back end 1002, and a central longitudinal axis 1003. The front end 1001 is for removable attachment to a terminal (not shown). The back end 1002 is for attachment onto a cable. The BNC connector 1000 comprises a compression ring 1010 that is generally tubular shaped. A tubular shaped shell 1012 is mounted to the compression ring 1010. The compression ring 1010 is mounted onto a body 1014, preferably by a press-fit. Preferably, the compression ring 1010 is plastic, and the shell 1012 and the body 1014 are metallic. A bayonet coupler 1015, including a gasket 1017 and a pair of washers 1021 and 1022, is snap-fit mounted onto the front end 1001 of the body 1014. The gasket 1017 is preferably polypropylene. The bayonet coupler 1015 and the washers 1021 and 1022 are preferably metallic. A coil spring 1025 is mounted between the pair of washers 1021 and 1022. The coil spring 1025 is preferably metallic. A generally tubular shaped post 1016 is mounted within the body 1014. Preferably, the post is metallic. A generally tubular shaped guide 1018 is mounted within the post 1016. Preferably, the guide 1018 is a dielectric. The compression ring 1010, shell 1012, body 1014, post 1016 and guide 1018 share the same longitudinal axis 1003.
FIG. 11 is a perspective view of the BNC connector 1000 showing a front end 1001 of the BNC connector, prior to attachment of the BNC connector onto the cable 300. FIG. 11 shows the BNC connector 1000 in the preferred �as shipped� state. The BNC connector 1000 includes a pin 1100 that is an integral part of the BNC connector, when shipped. In preferred embodiments, the pin 1100 does not extend close to the front end 1001 of the BNC connector 1000 such that the body 1014 of the BNC connector 1000 protects the pin 1100 from damage during shipment.
FIG. 13 is a partial cross-sectional view of the BNC connector 1000 and a side view of the cable 300, prior to attachment together. The cross-sectional view of FIG. 13 shows the BNC connector 1000 in the same preferred �as shipped� state as shown in the perspective view of FIG. 11, with a prepared cable 300 ready for insertion. In preferred embodiments, the pin 1100 is recessed within the body 1014. The BNC connector 1000 includes an insulator body 1301 that supports a front portion of the pin 1100 and maintains the pin at the central longitudinal axis 1003 of the BNC connector 1000. Preferably, the insulator body 1301 is a generally tubular support made of electrically insulative material. The pin 1100 has an inner surface defining a cylindrical bore along the longitudinal axis 1003 of the pin. The bore extends into the pin 1100 from the back end of the pin, and the bore has a length approximately one-third the length of the pin. In a preferred embodiment, the bore includes a wider portion 1006 nearest the back end of the pin 1100, and a narrower portion 1007 farther from the back end of the pin. The BNC connector 1000 includes the clip 402 mounted within the wider portion 1006 of the bore of the pin 1100. A contact assembly 1300 includes the guide 1018, the pin 1100 and the clip 402. The contact assembly 1300 is capable of moving longitudinally, as a unit, relative to the body 114. A label 1303 (not indicated in FIG. 10, 11 or 12) is optionally affixed to the outer surface of the shell 1012.
FIG. 16 is a partial cross-sectional view of the BNC connector 1000 and a side view of the cable 300, attached together, with the pin 1100 remaining in the fully popped out position. FIG. 16 shows the compression ring 1010, moved into the closed position, which captures the outer conductor 433 and jacket 434 of the cable 300 between the compression ring 1010 and the post 1016. In FIG. 16, the BNC connector 1000 is shown in the �in use� state.
FIG. 17 is a perspective view of an axially-compressible F connector 1700 showing a back end 1702 of the F connector prior to attachment together of the F connector and the cable 300. FIG. 17 shows the F connector 1700 in the preferred �as shipped� state. The F connector 1700 is generally tubular, and has a front end 1701, a back end 1702, and a central longitudinal axis 1703. The front end 1701 is for removable attachment to a terminal (not shown). The back end 1702 is for attachment onto the cable 300. The F connector 1700 comprises a compression ring 1710 that is generally tubular shaped. Preferably, the compression ring 1710 is plastic, and more preferably, is molded acetal. A tubular shaped shell 1712 is mounted to the compression ring 1710. Preferably, the shell 1712 is metallic. The compression ring 1710 is mounted onto a body 1714, preferably by a press-fit. Preferably, the body 1714 is metallic. A generally tubular shaped post 1716 is mounted within the body 1714. Preferably, the post is metallic. A generally tubular shaped guide 1718 is mounted within the post 1716. Preferably, the guide 1718 is a dielectric. The compression ring 1710, shell 1712, body 1714, post 1716 and guide 1718 share the same longitudinal axis 1703.
FIG. 18 is a perspective view of the F connector 1700 showing a front end 1701 of the F connector, prior to attachment of the F connector onto the cable 300. FIG. 18 shows the F connector 1700 in the preferred �as shipped� state. The F connector 1700 includes a pin 1800 that is an integral part of the F connector, when shipped. Advantageously, the pin 1800 does not extend beyond the front end 1701 of the F connector 1700 during shipment. As a result, the body 1714 of the F connector 1700 protects the pin 1800 from damage.
FIG. 19 is a perspective view of the F connector 1700 and a portion of the cable 300, showing the front end 1701 of the F connector, subsequent to attachment together of the F connector and the cable, and prior to axial compression of the F connector. The cable 300 is completely inserted into the F connector 1700, and the tip or head of pin 1800 is fully extended or fully popped out of the body 1714. Advantageously, a user receives a visual indication that the cable 300 is fully inserted into the F connector 1700 in that the user sees that the pin 1800 has moved to a fully popped out position. In FIG. 19, a front portion of the pin 1800 extends beyond the front end 1701 of the F connector 1700. In a final step, the F connector 1700 is axially compressed using one of several standard installation tools, which causes the compression ring 1710 and the body 1714 to move toward each other, thereby completing the attachment, and the F connector 1700 enters the �in use� state (not shown). The pin 1800 remains in the fully popped out position shown in FIG. 19 after the attachment is completed.
FIG. 20 is a partial cross-sectional view of the F connector 1700 in the same preferred �as shipped� state as shown in the perspective view of FIG. 17, with a prepared cable 300 ready for insertion. Advantageously, the tip of pin 1800 is recessed within the body 1714 during shipment. The F connector 1700 includes an insulator body 2001 that supports a front portion of the pin 1800 and maintains the pin 1800 at the longitudinal axis 1703 of the F connector 1700. Preferably, the insulator body 2001 is a generally tubular support made of electrically insulative material. The F connector 1700 includes the clip 402 mounted within a wider portion 2006 of a bore at the back end of the pin 1800. A contact assembly includes the guide 1718, the pin 1800 and the clip 402. The contact assembly is capable of moving longitudinally, as a unit, relative to the body 1714. A label 2003 (not indicated in FIG. 17, 18 or 19) is optionally affixed to the outer surface of the shell 1712. FIG. 20A is an enlargement of Area 20A of FIG. 20, and shows the contact assembly.
FIGS. 21�25 show another embodiment of a BNC connector 2100 with an alternative embodiment of a pop up pin 2130 with an attached sabot 2140. FIG. 21 is a partial cross-sectional view the BNC connector 2100 and a side view of the cable 300, prior to attachment to each other. FIG. 21 shows the BNC connector 2100 in the preferred �as shipped� state, with a prepared cable 300 ready for insertion. The sabot 2140 helps reduce the effect of cable �blind entry�.
FIG. 23 is a partial cross-sectional view of the alternative embodiment of the BNC connector 2100 and a side view of the cable 300, at a second stage of attachment. FIG. 23 shows the cable 300 fully seated. The arms 2141�2144 of the sabot 2140 are radially displaced inwardly within the bore of the connector insulator 2111, causing the four metallic fingers (only finger 2131 and finger 2133 are shown) at the back end of the slotted pin 2130 to close around, and preferably on, the center conductor 431 of the cable 300.
FIG. 25 is a partial cross-sectional view of the alternative embodiment of the BNC connector 2100 and a side view of the cable 300, assembled together, and with the front guide 2150 separated therefrom. In FIG. 25, the alternative embodiment of the BNC connector 2100 is shown in the �in use� state.
FIG. 28 is an enlarged rear view of the sabot 2140 in the neutral state. The sabot 2140 comprises four (4) arms 2141�2144.
FIG. 30 is an enlarged partial cross-sectional view of the contact assembly of the alternative embodiment of the BNC connector 2100, which comprises the sabot 2140 and the pin 2130. The contact assembly moves forward within the post 2116 as the cable 300 is inserted into the back end 2102 of the BNC connector. Flaring ensures that the sabot 2140 engages the bore of the post 2116 and keeps the pin 2130 centered in the post. The sabot 2140 snaps onto the back end of the pin 2130, which helps the pin and the sabot to stay axially engaged. The positioning of the sabot 2140 and pin 2130 reduces blind entry problems of the cable 300. The sabot 2140 is preferably slotted to allow even closure when forced into the bore of the post 2116. The arms 2141�2144 of the sabot 2140 preferably close evenly during compression and drive the four (4) fingers of the pin 2130 radially inward, causing the four fingers of the pin to close upon and to engage the center conductor 431 of the cable 300. This type of closing action provides positive electrical and mechanical contact between the pin 2130 of the BNC connector 2100 and the center conductor 431 of the cable 300. This closing action also prevents buckling of the center conductor 431 of the cable 300 because the arms 2141�2144 of the sabot 2140 do not apply a columnar load to the center conductor. The sabot 2140 is at least partially closed by the inner diameter of the post 2116. The sabot 2140 also acts as a guide for the dielectric layer 432 of the cable 300 to enter the inner diameter of the post 2116.
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In this audiobook, you'll discover a variety of historical events covering the span from the turn of the common era through WWII. Within this audiobook is a record of events once forgotten, or previously unknown, that have helped shape history and the world we live in today. History holds the key to understanding the present. Our past explains where we have come from and where we are heading. Although humanity can determine the steps it will take in the future, history often shows us the cycles that humanity repeats.
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value: This website is an American online audiobook and podcast service that allows users to purchase and stream audiobooks and other forms of spoken word content. This content can be purchased individually or under a subscription model where the user receives "credits" that can be redeemed for content monthly and receive access to a curated on-demand library of content.


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"Let's Develop on Prod w/ Istio + K8s" + "Blaze-Persistence GraphQL Support" | Meetup
20:00 - 21:00 Talk 2: Blaze-Persistence GraphQL Support
# Blaze-Persistence GraphQL Support - High performance querying and Relay pagination
Christian Beikov works with Java EE since 2010 and has lots of experience with CDI and JPA. He works part time at Curecomp GmbH in Linz in R&D and is about to enter his final semester at the University of Technology Vienna.

value: This website is a service used to organize online groups that host in-person and virtual events for people with similar interests. It was founded in 2002 by Chairman Scott Heiferman and four co-founders.


text:
Hotel Reviews of Harbour Hotel Hong Kong Hong Kong - Page 110
2416 reviews in English
All reviews (4167)
Strategic Location but really very very small room
it is nice that the hotel Lobby provide some of the travel card & travel map
Hotel Staffs are very friendly, they will teach you how to go to the famous landmarks and places. All our needs were accomodated timely and they didnt even ask us to pay for extra charges. Clean room and good Wifi connection at the hotel room.
15 min. to walk for access all the shopping place: Temple Street Night Market, Lady market, Poland Street, Longham shopping mall
stay at mongkok, with all the shopping and food nearby. it's centralize and afforable. though the room is slightly small, however it's one of the better one in hongkong.
worth to stay for shopping lovers.
Report this review Ankur G.
Location,Cleanliness,New
Had a decent stay.Located right in the center of the market,its strikingly neat and clean.Looks quite new too.Though everything is rat sized, but thats what you get in HK.
This ones cleaner though.Decent Value for Money
Report this review Sherlyn W.
Tiny room but excellent location!
very near to mtr, very near to ladies market, great location, easy accessibility to other areas
The staffs are quite friendly and the hotel is very clean. Great place if you are not very particular about the space in the room. We can only open 1 luggage at a time. Overall, very satisfied with the stay as it is very affordable!
there is free wifi in the room, just need to approach the receptionist and ask for the password to log in. the internet speed is incredibly fast!
Report this review Valentin V.
Super location, tiny rooms
Overall nice stay, the only cons:
- no good wifi in rooms
2-3 min walk to Mongkok shopping area, MTR (subway) and bus to airport
Location is so great until all great place like lady market & sport shoe street is just right beside the corner
this is my first time visit to hong kong with my wife during honey moon.
best thing to share:
1) hotel service is good & friendly staff.
2) the location is so great for you to find a great hk local food and popular streets.
to improve:-
1) wifi weak
2) water heater is not functioning even after fixed.
Report this review Yi Q.
Good Foods nearby but very small room
Lots of good food and shopping outlet. Excellent Location!
hotel is situated in mongkok, which is an excellent location with all the good foods and shopping outlets nearby.
however, the room is very small with small walking space. the toilet is also very small with knee touching the wall when sitting on the toilet bowl.
Try different variety of foods over there. You will be spoilt for choices.
Report this review Pariyapa L.
The location of this hotel is close to subway only two blocks away.
Even the room is small about 3*4 square meters including a shower room but its normal in hong kong anyway.
The breakfast is quite simple, they offer four choices, each one will ge served with an egg and a banana. Dont expect too. Anyway with the breakfast, i felt so full and got enough energy for the day.
Nice choice for budget trip!
Go to ladies market at night, its just across the road!!
Report this review Manachanok K.
Near MRT, nice for shopping in Mongkok
Very welcome and nice service. Near MRT, Shopping center. Easy to travel. Small room but clean. I'm impress!!
Easy to shopping to Lady market and a lot of toys !!
Suggess hotel for shopping
clean and easy to get shopping
It small but very clean and lovely price. Nice location near MRT and shopping center in Mongkok.
Perfect for Hobby and toys shopping trip !!
1091 - 1100 of 2416 reviews

value: This website is a Singaporean online travel agency and metasearch engine for hotels, vacation rentals, flights, and airport transfer. It is owned by Agoda Company Pte.


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Aled Haydn Jones (born 9 August 1976 in Aberystwyth, Wales[1][2]) is a Welsh radio editor, presenter and former radio producer. From 2004 until 2012 he worked on The Chris Moyles Show. He was a presenter on The Surgery on BBC Radio 1 between 2009 and 2015.
Jones was born to Hayden and Ann Jones in Aberystwyth, Wales, in 1976. He has a younger sister named Meleri. Jones is a fluent Welsh speaker. He attended Ysgol Gymraeg Aberystwyth, a Welsh medium primary school, and Ysgol Gyfun Penweddig Welsh medium secondary before going on to complete a BTEC qualification in Media Studies at Swansea College.[2] He currently lives in London.
As well as being a producer of The Chris Moyles Show, Jones also presents Radio 1's Surgery on Sunday night as part of the BBC Switch strand.[4]
The Surgery with Aled and Doctor Radha (formerly known as the Sunday Surgery and more recently The Surgery with Aled) is a British radio show that airs on BBC Radio 1 on Wednesday evenings from 9-10pm. In 2008, Jones was a regular presenter on Radio 1's Sunday Surgery, providing cover for Kelly Osbourne while she was ill. In Autumn 2008, it was announced that Osbourne would be taking a break from the Sunday Surgery in order to film Osbournes: Reloaded in the USA with the rest of her family, and Jones became the regular presenter. In 2013 Jones was given a co host, Doctor Radha. In April 2015 it was announced that Gemma Cairney would present the show from June 2015.
Working with Chris Moyles[edit]
In addition to his career on Radio 1, he has also been a judge on the S4C Welsh language talent show, Wawffactor. He appeared as an extra in season 4 of 24, in episode 23, and was voted Rear of the Year in 2004.[5]
In November 2007, Jones appeared as a contestant in the BBC series "Celebrity Scissorhands",[6] in aid of charity Children in Need. The contestants had to learn how to cut hair and give various beauty salon treatments on volunteers, with the minimal amount of training. Jones eventually finished second in the contest, losing in the final to comedian Ninia Benjamin.
In March 2011, Jones was part of the ITV2 Show, OMG with Peaches Geldof in which he, alongside Geldof looked at understanding alternative lifestyles and subcultures.[7]
^ "Aled Haydn Jones Biography". BBC Wales. ^ a b "Aled Haydn Jones Profile". chrismoyles.net. ^ https://twitter.com/ahj/status/763363488521740288
^ "Radio 1 Surgery". 2009-02-15. ^ "Rear of the Year History". Rear of the Year. ^ "Aleds 'Celebrity Scissorhands' profile on the BBC website". BBC. ^ "OMG with Peaches Geldof". itv.com. External links[edit]
Aled Jones on Twitter Biography at BBC Wales
Retrieved from "https://en.wikipedia.org/w/index.php?title=Aled_Haydn_Jones&oldid=742349257"	Categories: 1976 birthsBBC Radio 1 presentersLGBT broadcastersLGBT DJsWelsh radio DJsPeople from AberystwythPeople educated at Ysgol Gyfun Gymunedol PenweddigLiving people	Navigation menu
Cymraeg	Edit links	This page was last edited on 3 October 2016, at 05:04.

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text: We found 0 results for "" Check your spelling or use different keywords and try again. If you are searching for help information, please select "Help" from the list of departments and try the search again. Some products available in stores may not be listed online — contact your local store to see if they carry what you are looking for. Walmart Sterling 45415 Dulles Crossing Plz Sterling, VA 20166 Ph. (571) 434-9434 Find another store Showing 0 of 0 results Compute- app-11030446-10-54868083, DC- prod-dfw3, ENV- prod-a, Ver- 32.0.1, SHA- 218663fd569ac9bf392b2c78e3a7f424c761bb61, Log- 154a2cf1-780b-152d03ca848000 Site Information Be the first to save! Email Address Sign up Privacy policy

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WBrecheen in San Jose - TripAdvisor
Search Profile Badge collection Travel map WBrecheen's San Jose, CA, USA View all WBrecheen's cities 45 Contributions 23 Reviews | 22 Ratings Sort by: Date posted Date posted Reviews first Alphabetical Top rated Grid View List View Back to top
Black Angus Steakhouse - Blossom Hill 1011 Blossom Hill RdPosted Dec 14, 2014 "Bit of a disappointment for the first time"We shared a holiday dinner with a group of friends this week-end at the Black Angus Steak House on B...read more Children's Musical Theater San Jose 1401 Parkmoor AvePosted Apr 25, 2013 Three Flames Restaurant 1547 Meridian AvePosted Apr 25, 2013 History Museum of San Jose 1650 Senter RdPosted Apr 25, 2013 California Pizza Kitchen 2077 Airport BlvdPosted Apr 25, 2013 History Park 1650 Senter RdPosted Apr 25, 2013 Almaden Quicksilver County Park At the corner of McAbee Road and Camden AvenuePosted Apr 25, 2013 Togo's 1205 The AlamedaPosted Apr 25, 2013 Kelley Park 1300 Senter RoadPosted Apr 25, 2013 The City National Civic 135 W San Carlos StPosted Apr 25, 2013 Bill's Cafe 1115 Willow StPosted Apr 25, 2013 P F Chang's China Bistro - CLOSED 98 S 2nd StPosted Apr 25, 2013 About Us

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text:
Patent US4809681 - Electrocardiographic measurement method for controlling an intra-aortic ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA pair of spaced electrodes are disposed inside the thoracic aorta near the heart and are used to sense R- and P-waves in an ECG signal. The electrodes are moved to an ideal intra-aortic position, which is that where R- and P-waves are sensed to have the same magnitude, the P-wave, which occurs earlier...http://www.google.com/patents/US4809681?utm_source=gb-gplus-sharePatent US4809681 - Electrocardiographic measurement method for controlling an intra-aortic balloon pumpAdvanced Patent SearchPublication numberUS4809681 APublication typeGrantApplication numberUS 07/031,137Publication dateMar 7, 1989Filing dateMar 30, 1987Priority dateMar 28, 1986Fee statusPaidPublication number031137, 07031137, US 4809681 A, US 4809681A, US-A-4809681, US4809681 A, US4809681AInventorsAdrian Kantrowitz, Paul S. Freed, Hiroyuki Tachi, Akira SuzukiOriginal AssigneeAisin Seiki Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (18), Non-Patent Citations (2), Referenced by (49), Classifications (18), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetElectrocardiographic measurement method for controlling an intra-aortic balloon pump
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Ltd.Catheter head-type transducerUS4274423 *Dec 8, 1978Jun 23, 1981Kabushiki Kaisha Toyota Chuo KenkyushoCatheter tip pressure transducerUS4284073 *May 10, 1979Aug 18, 1981Krause Horst EMethod and apparatus for pumping blood within a vesselUS4362150 *Sep 10, 1980Dec 7, 1982Kontron Cardiovascular Inc.Percutaneous intra-aortic balloon apparatusUS4552127 *Apr 1, 1983Nov 12, 1985Peter SchiffPercutaneous intra-aortic balloon having an EKG electrode and a twisting stylet for coupling the EKG electrode to monitoring and/or pacing instrumentation external to the bodyUS4569332 *Apr 13, 1983Feb 11, 1986Peter SchiffMethod and apparatus for treating a heart patient through the coordinating efforts of balloon pumping and dispensing cathetersUS4630597 *Apr 30, 1984Dec 23, 1986Adrian KantrowitzDynamic aortic patch for thoracic or abdominal implantationSU995751A1 * Title not available* Cited by examinerNon-Patent CitationsReference1 *Mansfield Scientific, Inc. brochure directed to Ventri Pace Torque and Ventri Pace Semi Floater catheters.2Mansfield Scientific, Inc. brochure directed to Ventri-Pace Torque and Ventri-Pace Semi-Floater catheters.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5158529 *Mar 27, 1991Oct 27, 1992Aisin Seiki Kabushiki KaishaPumping device for operating an intra-aortic balloonUS5169379 *Jun 14, 1989Dec 8, 1992L-Vad TechnologyIn-series ventricular assist system and method of controlling sameUS5494032 *May 23, 1994Feb 27, 1996Sandia CorporationOximeter for reliable clinical determination of blood oxygen saturation in a fetusUS5904666 *Aug 18, 1997May 18, 1999L.Vad Technology, Inc.Method and apparatus for measuring flow rate and controlling delivered volume of fluid through a valve apertureUS5935103 *Jul 18, 1997Aug 10, 1999Heartport, Inc.Blood vessel occlusion deviceUS5941894 *Jul 18, 1997Aug 24, 1999Heartport, Inc.Blood vessel occlusion deviceUS5997505 *Jul 18, 1997Dec 7, 1999Heartport, Inc.Method of cannulating an ascending aorta using a blood vessel occlusion deviceUS6042532 *Mar 9, 1998Mar 28, 2000L. Vad Technology, Inc.Pressure control system for cardiac assist deviceUS6066086 *Mar 4, 1998May 23, 2000Nimbus, Inc.Speed control system for implanted blood pumpsUS6132363 *Sep 30, 1998Oct 17, 2000L.Vad Technology, Inc.Cardiovascular support control systemUS6224619Sep 17, 1996May 1, 2001Heartport, Inc.Blood vessel occlusion trocar having size and shape varying insertion bodyUS6511412Oct 16, 2000Jan 28, 2003L. Vad Technology, Inc.Cardivascular support control systemUS6669624 *Mar 26, 2002Dec 30, 2003O. Howard FrazierTemporary heart-assist systemUS6679829May 7, 2001Jan 20, 2004Paul NigroniIntra-aortic balloon pump having improved automated electrocardiogram based intra-aortic balloon deflation timingUS6735532Nov 18, 2002May 11, 2004L. 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Vad Technology, Inc.External blood pressure sensor apparatus and methodEP1968666A2 *Dec 4, 2006Sep 17, 2008Arrow International, Inc.Methods and apparatus for selecting intra-aortic balloon deflation timingWO1990013322A1 *May 7, 1990Nov 15, 1990Jacob SegalowitzHeart-assist balloon pumpWO1996034531A1May 3, 1996Nov 7, 1996G Van Wijnsberghe En Co N VMethod of delivering animals to a processing area and an apparatus thereforWO2002028280A1Oct 1, 2001Apr 11, 2002Arrow Int IncApparatus for controlling heart assist devicesWO2003082379A1 *Feb 21, 2003Oct 9, 2003Howard O FrazierTemporary heart-assist systemWO2007081454A2Dec 4, 2006Jul 19, 2007Arrow Int IncMethods and apparatus for selecting intra-aortic balloon deflation timing* Cited by examinerClassifications U.S. Classification600/17, 604/914, 600/521, 604/913International ClassificationA61M1/10, A61B5/042, A61B5/0215, A61M29/02Cooperative ClassificationA61B5/6853, A61M1/1072, A61B5/0215, A61M29/02, A61B5/042European ClassificationA61B5/68D1H1, A61B5/0215, A61M1/10E51D, A61B5/042, A61M29/02Legal EventsDateCodeEventDescriptionAug 26, 1992FPAYFee paymentYear of fee payment: 4Aug 27, 1996FPAYFee paymentYear of fee payment: 8Aug 28, 2000FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services