text:
Patent US5364557 - Aligned cholesteric liquid crystal inks - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsIn color printing, and in the fine arts, cholesteric liquid crystal (CLC) color inks are known to possess much higher color saturation and brightness than conventional pigment and dyed based inks. However, prior art CLC ink formulations are inconvenient because in the liquid phase they have to be confined...http://www.google.com/patents/US5364557?utm_source=gb-gplus-sharePatent US5364557 - Aligned cholesteric liquid crystal inksAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS5364557 APublication typeGrantApplication numberUS 07/798,881Publication dateNov 15, 1994Filing dateNov 27, 1991Priority dateNov 27, 1991Fee statusPaidAlso published asUS5599412, US6338807, US6551526, US7029601, US20020020829, US20040011995Publication number07798881, 798881, US 5364557 A, US 5364557A, US-A-5364557, US5364557 A, US5364557AInventorsSades M. FarisOriginal AssigneeFaris Sades MExport CitationBiBTeX, EndNote, RefManPatent Citations (3), Referenced by (75), Classifications (38), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetAligned cholesteric liquid crystal inks
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4707080 *Mar 2, 1984Nov 17, 1987Manchester R & D PartnershipEncapsulated liquid crystal material, apparatus and methodUS4859360 *Mar 21, 1986Aug 22, 1989Biosynergy, Inc.Cholesteric liquid crystal formulations and time/temperature monitoring meansUS5198148 *Jun 14, 1990Mar 30, 1993Shinko Electric Works Co., Ltd.Cholesteric liquid crystal composition, color-forming liquid crystal composite product, method for protecting liquid crystal and color-forming liquid crystal picture laminated product* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5683622 *May 5, 1995Nov 4, 1997Consortium Fur Elektrochemische Industrie GmbhOptical elements having color-selective and polarization-selective reflection containing LC pigments, and the production of these elementsUS5824733 *Apr 26, 1995Oct 20, 1998Wacker-Chemie GmbhAqueous coating product and a process for producing multiple layer paint coatings whose perceived color varies with the angle from which they are viewedUS5851277 *Jul 8, 1997Dec 22, 1998Wacker-Chemie GmbhPreparation whose coloring depends on the viewing angleUS5851604 *May 1, 1995Dec 22, 1998Consortium Fur Elektrochemische Industrie GmbhInterference pigments comprising molecules fixed in a cholesteric configuration, and use thereofUS6136251 *Sep 9, 1997Oct 24, 2000Basf AktiengesellschaftProcess for producing pigment particles of defined shape and sizeUS6207770 *Feb 1, 1997Mar 27, 2001Merck Patent GmbhCholesteric flakesUS6337131Apr 26, 1999Jan 8, 2002Basf AktiengesellschaftCore-shell particles and preparation and use thereofUS6338807 *Jan 24, 1997Jan 15, 2002Reveo, Inc.Cholesteric liquid crystal (CLC)-based coloring media for producing color effects having improved brightness and color characteristicsUS6369868 *Jun 5, 1998Apr 9, 2002Reveo, Inc.Liquid crystal polarizer with electrically controllable bandwidthUS6377325 *Jul 9, 1997Apr 23, 2002Sadeg M. FarisReflective film material having symmetrical reflection characteristics and method and apparatus for making the sameUS6387457 *Aug 28, 1998May 14, 2002Reveo, Inc.Method of dry printing and paintingUS6394595Aug 28, 1998May 28, 2002Reveo, Inc.Apparatus for producing multi-color images on substrates using dry multi-colored cholesteric liquid crystal (CLC) pigment materialsUS6404464 *Jul 22, 1997Jun 11, 2002Reveo, Inc.Method and system for producing color images with improved brightness and color characteristics on radiation absorptive surfacesUS6410130Sep 1, 1998Jun 25, 2002Basf AktiengesellschaftCoatings with a cholesteric effect and method for the production thereofUS6414092 *Nov 28, 2000Jul 2, 2002Merck Patent Gesellschaft Mit Beschraenkter HaftungCholesteric flakesUS6551526 *Jul 16, 2001Apr 22, 2003Reveo, Inc.Aligned cholesteric liquid crystal inksUS6582781Sep 1, 1998Jun 24, 2003Basf AktiengesellschaftMultilayer cholesteric pigmentsUS6630974 *May 14, 1999Oct 7, 2003Reveo, Inc.Super-wide-angle cholesteric liquid crystal based reflective broadband polarizing filmsUS6643001Nov 20, 1998Nov 4, 2003Revco, Inc.Patterned plateletsUS6665042May 16, 2000Dec 16, 2003The University Of RochesterElectrically switchable polymer liquid crystal and polymer birefringent flake in fluid host systems and optical devices utilizing sameUS6697133Apr 8, 2002Feb 24, 2004Reveo, Inc.Controllable bandwidth polarizerUS6710823Nov 6, 2001Mar 23, 2004Reveo, Inc.Electro-optical glazing structures having reflection and transparent modes of operationUS6829075May 20, 2003Dec 7, 2004The University Of RochesterElectrically addressable optical devices using a system of composite layered flakes suspended in a fluid host to obtain angularly dependent optical effectsUS6873381 *Jan 23, 2004Mar 29, 2005Reveo, Inc.System for controlling unpolarized electromagnetic radiationUS6876427 *Sep 21, 2001Apr 5, 20053M Innovative Properties CompanyCholesteric liquid crystal optical bodies and methods of manufacture and useUS6913793 *Feb 3, 2003Jul 5, 2005Reveo, Inc.Method of producing iridescent coatingsUS7029601 *Apr 21, 2003Apr 18, 2006Reveo, Inc.Aligned cholesteric liquid crystal inksUS7042617Apr 2, 2003May 9, 2006The University Of RochesterOptical devices having flakes suspended in a host fluid to provide a flake/fluid system providing flakes with angularly dependent optical properties in response to an alternating current electric field due to the dielectric properties of the systemUS7081282Jul 1, 2002Jul 25, 2006Merck Patent GmbhOptically variable markingUS7238316Mar 7, 2003Jul 3, 2007University Of RochesterMethod for making precisely configured flakes useful in optical devicesUS7298442Feb 24, 2005Nov 20, 20073M Innovative Properties CompanyCholesteric liquid crystal optical bodies and methods of manufacture and useUS7488451Jul 28, 2004Feb 10, 2009Millipore CorporationSystems for particle manipulationUS7557070Apr 10, 2002Jul 7, 2009Millipore CorporationMultiplexed cell analysis systemUS7601417Dec 18, 2002Oct 13, 2009Seiko Epson CorporationRecorded matter having countermeasure against forgingUS8558995 *Sep 15, 2006Oct 15, 2013Arjowiggins SecurityStructure comprising a fibrous material substrate and method for authenticating and/or identifying such a structureUS8864037Mar 13, 2013Oct 21, 2014Sicpa Holding SaMultilayer flake with high level of codingUS8902385 *Mar 16, 2011Dec 2, 2014National Cheng Kung UniversityPolymer film without cholesteric liquid crystal, polymer film and reflective display moduleUS20030012935 *Jul 1, 2002Jan 16, 2003Merck Patent GmbhOptically variable markingUS20030059764 *Apr 10, 2002Mar 27, 2003Ilya RavkinMultiplexed cell analysis systemUS20030063245 *Sep 21, 2001Apr 3, 2003Bowley Christopher C.Cholesteric liquid crystal optical bodies and methods of manufacture and useUS20040011995 *Apr 21, 2003Jan 22, 2004Faris Sadeg M.Aligned cholesteric liquid crystal inksUS20040043180 *Feb 3, 2003Mar 4, 2004Yingqiu JiangMethod of producing iridescent coatingsUS20040151880 *Dec 12, 2002Aug 5, 2004Hiroto NakamuraRecorded matter having countermeasure against forgingUS20040173927 *Mar 7, 2003Sep 9, 2004Anka Trajkovska-PetkoskaMethod for making precisely configured flakes useful in optical devicesUS20040196226 *Apr 2, 2003Oct 7, 2004Kosc Tanya Z.Optical devices having flakes with angularly dependent optical properties in response to an alternating current electric field when the flakes are suspended in a host fluid to provide a flake/fluid system which is conductiveUS20040218116 *Jan 23, 2004Nov 4, 2004Bunsen FanControllable bandwidth polarizerUS20040233508 *May 20, 2003Nov 25, 2004Kosc Tanya Z.Electrically addressable optical devices using a system of composite layered flakes suspended in a fluid host to obtain angularly dependent optical effectsUS20040247825 *Mar 13, 2004Dec 9, 2004Faris Sadeg M.Coloring media having improved brightness and color characteristicsUS20040258894 *Mar 31, 2004Dec 23, 2004Yingqiu JiangMethod of dry printing and paintingUS20040263975 *Jun 24, 2004Dec 30, 2004Metronic AgMethod for producing a polarization-affecting viewing elementUS20050024626 *Oct 20, 2003Feb 3, 2005Faris Sadeg M.Patterned plateletsUS20050084423 *Jul 28, 2004Apr 21, 2005Zarowitz Michael A.Systems for particle manipulationUS20050084914 *Sep 15, 2004Apr 21, 2005Foulkes J. G.Assays with primary cellsUS20050208468 *Sep 15, 2004Sep 22, 2005Beske Oren EAssays with primary cellsUS20060073278 *Nov 23, 2005Apr 6, 2006Hiroto NakamuraRecorded article with anti-counterfeit measuresUS20070273879 *Aug 6, 2007Nov 29, 2007Oleg SiniaguineParticles with light-polarizing codesUS20090033914 *Sep 15, 2006Feb 5, 2009Arjowiggins SecurityStructure Comprising a Fibrous Material Substrate and Method for Authenticating and/or Identifying Such a StructureUS20100112314 *Nov 2, 2009May 6, 2010Yingqiu JiangInvisible Pigments and InkUS20100208351 *Mar 18, 2010Aug 19, 2010Nofi Michael RSelective and oriented assembly of platelet materials and functional additivesUS20120050650 *Mar 16, 2011Mar 1, 2012Jui-Hsiang LiuPolymer film without cholesteric liquid crystal, polymer film and reflective display moduleUS20120168506 *Sep 30, 2011Jul 5, 2012Ulrich RuehrmairMethod For Security PurposesEP0686674A1 *May 4, 1995Dec 13, 1995Consortium für elektrochemische Industrie GmbHInterference pigments from molecules fixed in a cholesteric arrangement and their useEP0872326A1 *Apr 9, 1998Oct 21, 1998Clariant GmbHMethod of making polymer laminatesEP0994775A1 *Jul 8, 1998Apr 26, 2000Reveo, Inc.Coloring media having improved brightness and color characteristicsEP0994775A4 *Jul 8, 1998Apr 2, 2003Reveo IncColoring media having improved brightness and color characteristicsEP1213338A1Nov 8, 2001Jun 12, 2002Consortium für elektrochemische Industrie GmbHMethods for preparing flakesEP1281538A2Jun 7, 2002Feb 5, 2003MERCK PATENT GmbHOptically variable markingEP1428065B1 *Aug 7, 2002Sep 19, 20123M Innovative Properties CompanyCholesteric liquid crystal optical bodies and methods of manufacture and useEP1491935A1 *May 14, 2004Dec 29, 2004Metronic AGMethod of manufacturing a visualization element with polarization influenceEP2529940A1May 31, 2011Dec 5, 2012Sicpa Holding SaPrinted device with three dimensional appearanceWO1997027251A1 *Jan 22, 1997Jul 31, 1997Basf AktiengesellschaftProcess for producing pigment particlesWO1998012265A1 *Sep 9, 1997Mar 26, 1998Basf AktiengesellschaftProcess for producing pigment particles of defined shape and sizeWO2001088607A1 *May 15, 2001Nov 22, 2001The University Of RochesterElectrically switchable polymer liquid crystal and polymer birefringent flake in fluid host systems and optical devices utilizing sameWO2002085642A2Mar 28, 2002Oct 31, 2002Merck Patent GmbhBirefringent markingWO2012163553A1Feb 15, 2012Dec 6, 2012Sicpa Holding SaPrinted device with three dimensional appearance* Cited by examinerClassifications U.S. Classification252/299.01, 347/100, 252/299.7International ClassificationG02F1/1334, E06B9/24, C09B67/00, C09K19/52, C09D11/02, C09K19/00, C09D11/16, F24J2/40, G02B5/30Cooperative ClassificationC09K19/00, G02F1/1334, G02B5/3016, E06B9/24, C09D11/037, F24J2/407, E06B2009/2464, Y10T428/1036, C09K19/52, C09D11/17, Y02E10/40, Y10T156/1374, Y10T428/1086, C09B67/0098, Y10T156/1084, B82Y15/00, Y10T428/2998European ClassificationB82Y15/00, C09D11/17, C09D11/037, E06B9/24, F24J2/40D, C09K19/52, G02B5/30L, C09B67/00V, C09K19/00Legal EventsDateCodeEventDescriptionMar 29, 1996ASAssignmentOwner name: REVEO, INC., NEW YORKFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FARIS, SADEG M.;REEL/FRAME:007868/0165Effective date: 19950818Mar 30, 1998FPAYFee paymentYear of fee payment: 4Jan 7, 2002FPAYFee paymentYear of fee payment: 8May 31, 2006REMIMaintenance fee reminder mailedNov 13, 2006FPAYFee paymentYear of fee payment: 12Nov 13, 2006SULPSurcharge for late paymentYear of fee payment: 11RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


text:
BBB Business Profile | All My Sons Moving & Storage of Southwest Florida, Inc.
Home > Florida > Ocala > Moving Companies > All My Sons Moving & Storage of Southwest Florida, Inc.
(352) 577-2411
303 SE 17th St # 309-156
(352) 390-3220
southwestflorida@allmysons.com
Principal: Ms. Linda Dubberly, President

type: global

value: This website is a private, nonprofit organization whose self-described mission is to focus on advancing marketplace trust, consisting of 106 independently incorporated local BBB organizations in the United States and Canada, coordinated under the International Association of Better Business Bureaus  in Arlington, Virginia.The Better Business Bureau is not affiliated with any governmental agency. Businesses that affiliate with the BBB and adhere to its standards do so through industry self-regulation.


text:
Threaded Shreds in Dim from Indelible by Katarina Roccella - Art Gallery Fabrics - (IDL-1225)
SALE Complete Fat eighth bundle of IN Blue fabric collection by Katarina Roccella for Art Gallery fabrics - INB-36637

value: This website is an American e-commerce company focused on handmade or vintage items and craft supplies.


text:
Gen Story Girl (#47021614)	member for 6 years, 10 months
Search Contributor's Records First NameLast NameVirtual CemeteriesB-24 #42-7486 Crew (10)The Lees of Virginia (19)Find A Grave FriendsBill G, Blackco, Carol Lane, Connie , Connie, Dee Burris Blak..., EAC, J. Rubio, Jeanne.Killick, Jude, Kimberly Whetse..., Lee Veal, MFloyd, Mookie, Nancy, sandra ferguson, Sue McGuireMessages left for Gen Story Girl (135)[Leave Message]
judy lakkisRE: Thanks!You are so welcomed. It was a beautiful day here after the rainstorm, so I wanted to show that in my photo. I put much feeling into my photos. Keeping all natural is the best.Added by judy lakkis on Jan 29, 2015 12:37 PMCassandra DavisJonathan D. "John" GroganHello! Apparently we share 4th great grandfathers... I just wanted to see how you align up with John. Feel free to email me directly at casakelash@hotmail.comBeth Holmes DavisAdded by Cassandra Davis on Jan 27, 2015 9:15 PMKevin FinchRobert & Nellie ColemanHelloI fulfilled your request for Robert today. He shares a headstone with his wife Nellie. I would have posted the photo on Nellie's memorial, however another contributor claimed your request for her. So you will receive the same photo for her at a later date.KevinAdded by Kevin Finch on Jan 27, 2015 11:22 AMBlackcoRE: Coleman CousinsYou are right, you are related to many, which you will easily find in the book. The book was written as a gift to the Liberty Cemetery Trustees to bring in funds for the support of the cemetery's maintenance. It is a historical work and contains a lot of research information that would be helpful to you, including cemetery, monument, people and document images that all help bring our ancestors to life. It is available in black and white copy from Marvin and Betty Cameron, Trustees, at (479) 963-3576. I believe the book is $50.00, plus mailing. If you have any questions about family, please feel free to ask. Your cousin, ConnieAdded by Blackco on Dec 02, 2014 12:40 PMBlackcoRE: Coleman CousinsI have been putting family photos on FindAGrave, Liberty Cemetery. Do you have any of Robert P. and down the line? I am always interested in what everyone looks like. Did you know that Uncle Dee once owned the land that makes up the Liberty Cemetery, etc. I have copies of the deeds. I also authored a book called, The Residents of Liberty Cemetery Logan County, Arkansas. It actually a historical work. Anyway, I always like to connect with family. Best wishes, ConnieAdded by Blackco on Dec 01, 2014 6:34 PMBlackcoColeman CousinsI am one of your Coleman cousins now living in the town of Magazine. I am an old lady now, but have been researching since I was 16 years, because of a family history similar to yours where family was very important. I have done extensive research, and am hoping we might be able to help one another. Hope to hear from you, Connie BlackwellAdded by Blackco on Dec 01, 2014 6:16 AMTeddyDSSgt Earl A Patterson, Jr MemorialI have uploaded an image of The Shark Crew that Earl was a member of. Would you be able to ask your contact of the Patterson family if they could identify him in the image? Thanks. Ted DudziakAdded by TeddyD on Sep 13, 2014 8:18 AMAlycia KRE: Stephen Ells # 47499948I feel sad. I will see if I can find out more.Added by Alycia K on Sep 12, 2014 5:55 AMAlycia KStephen Ells # 47499948Hi,Your request for this grave marker is a bit of a problem. I've walked the yard a couple times and did not see this grave. Moreover, he is not listed in the Hale index of cemetery inscriptions. Also, this particular yard seems to date back to the 1800s but not to the 1700s...with a very few exceptions. Could he be interred elsewhere?All the best,AlyciaAdded by Alycia K on Sep 08, 2014 11:18 AMM&CRe: Thank You.My pleasure in visiting your beloved Dad, James. I hope you are doing well and have a blessed weekend. CarolynAdded by M&C on Aug 22, 2014 8:30 AM[View all messages...] Privacy Statement and Terms of Service Advertisement

value: This website is a website that allows the public to search and add to an online database of cemetery records. It is owned by Ancestry.com.


text: will receive more medical care at his the johannesburg home until you fully recovers. >> newtown, conn. are asking for the public to stop sending gifts, which the small town is struggling to manage. since the slaying of the 20 students and six this faculty members >> two weeks ago, a new town has been the lowest bid, up from tens of thousands of teddy bears, or does a soccer balls to flowers, our work and school supplies. officials say that they would be to the best way to help the community after the " where houses pull items " our process. >> will be right back. >> a developing story just into kron 4 news room. we're getting reports of an officer involved shooting in walnut creek. it happens in an apartment complex on creekside drive. the call came in around 315 this morning. kron 4 urs will tran just to the scene and he joins us now on the phone. >> we do know that there was some sort of incident involving a police officer that discharged his weapon about 320 this morning. no officer is injured at this time. we do not know a lot of details because we just arrived here. there with ho Search Results 0 to 4 of about 5

value: This website is an American digital library with the stated mission of "universal access to all knowledge". It provides free public access to collections of digitized materials, including websites, software applications/games, music, movies/videos, moving images, and millions of books.


text: Sorry, no products matched "" Check your spelling Use different keywords and try again Contact your local store Compute- app-11031075-1-50864069, DC- prod-dfw4, ENV- prod-a, Ver- 44.0.2, SHA- 42702b0755507672d99b43707ee6c95abb804137, Log- 18a66d6-3d6b-1563d241db7000 Site Information Be the first to save! Email Address Sign up Privacy Policy Stay connected Mobile apps Help Feedback MoneyCenter Privacy & Security CA Privacy Rights Terms of Use Financial services Walmart MoneyCenter Walmart Credit Card Apply Now Manage Card Account Product Care Plans Walmart Pay Get to know us About Walmart.com Corporate Suppliers Marketplace Careers @WalmartLabs Walmart.com Terms of Use About Our Ads Affiliate Program CA Privacy Rights Privacy & Security Customer service Returns Policy Product Recalls Int’l Customers Tax Exempt Program Contact Us Feedback Store Pickup In the spotlight Expand Baby Cribs Strollers Diapers Baby Feeding Car Seats Expand Electronics Cut the Cable Computers TVs iPads & Tablets Expand Fitness Exercise Machines Vitamins Ellipticals Treadmills Fitbit Expand Keep Cool Air Conditioners Fans Swimming Pools Pool Toys Expand International Sites Argentina Brazil Canada Chile China Japan Mexico United Kingdom © Walmart Stores, Inc. To ensure we’re able to help you as best we can, please include your reference number: Ref:

value: This website is an American multinational retail corporation that operates a chain of hypermarkets , discount department stores, and grocery stores from the United States, headquartered in Bentonville, Arkansas.


text:
20th Century American Composers Intermediate Level Piano Pf Bk by Hal Leonard... 9781495008160 | eBay
See more 20th Century American Composers Intermediate L...
20th CENTURY ITALIAN COMPOSERS Piano
20Th Century American Composers Upper Intermediate Level Piano, New, Various Bo
20TH CENTURY AMERICAN COMPOSERS Upper Intermediate
Hal Leonard Student Piano Library: Double Agent! Piano Duets - Intermediate Pian
blackwelloxford (106101 )
Details about 20th Century American Composers Intermediate Level Piano Pf Bk by Hal Leonard...
20th Century American Composers Intermediate Level Piano Pf Bk by Hal Leonard...
Jazz Exercises, Minuets, Etudes & Pieces For Piano, Paperback by Peterson, Os...
Piano Lessons : Book 1, Paperback by Hal Leonard Publishing Corporation (EDT)...
333479879255
Publication Year: 2015 Title: 20th Century American Composers Intermediate Level Piano Pf Bk
ISBN: 9781495008160 Author: Hal Leonard Publishing Corporation
EAN: 9781495008160
ISBN-10 1495008169
ISBN-13 9781495008160
eBay Product ID (ePID) 213101082
Back to home page | See more details about "20th Century American Composers Intermediate Level Pia..." Return to top
20th Century American Composers Intermediate Level Pian... 20th Century American Composers Intermediate Level Pian...
Buy it now - 20th Century American Composers Intermediate Level Piano Pf Bk by Hal Leonard... Add to Watch list Added to your Watch list
Piano Intermediate Piano Score Contemporary Sheet Music & Song Books,
Piano Intermediate Music Theory Books,
Orchestra Piano Intermediate Sheet Music & Song Books,
Piano Score Piano Intermediate Sheet Music & Song Books

value: This website is an American multinational e-commerce corporation based in San Jose, California, that facilitates consumer-to-consumer and business-to-consumer sales through its website.


text:
Wildest Dream: The Biography of George Mallory by Peter Gillman, Gillman |, Paperback | Barnes & Noble®
by Peter Gillman, Gillman, Leni Gillman (Joint Author)Peter Gillman
The discovery of George Mallory's body high on Everest on May 1, 1999, stunned the world. Yet behind the headlines, investigative journalists Peter and Leni Gillman sensed there was far more to the story than whether Mallory had reached the top. How did Mallory reconcile his love for his wife and children with his dream of summitting Everest? Why did he make his final
Wildest Dream: The Biography of George Mallory available in
The discovery of George Mallory's body high on Everest on May 1, 1999, stunned the world. Yet behind the headlines, investigative journalists Peter and Leni Gillman sensed there was far more to the story than whether Mallory had reached the top. How did Mallory reconcile his love for his wife and children with his dream of summitting Everest? Why did he make his final attempt when he knew the odds were stacked against him? The Wildest Dream is an intimate portrait of a man torn between competing desires and the fatal choice he ultimately made. Drawing on newly discovered documents and letters and aided by members of Mallory's family, the Gillmans reveal him as a versatile, complex, questing figure, who relished new experiences and took them to the limit. He was a socialist, an early campaigner for women's rights, and a clergyman's son who became an agnostic. A teacher and a writer, Mallory espoused the new movements in literature and the arts and consorted with London's avant-garde Bloomsbury set. He fell passionately in love with Ruth Turner, marrying her on the eve of the First World War. They had to endure the anguish of separation when he fought on the Western Front and suffered it again as Everest -- forbidding, remote, "the wildest dream" -- kept luring him back. The Wildest Dream bares the heart and soul of the man behind the myth.
Much has been written about Mallory's mysterious end, but this graceful, meticulous biography should revive appreciation for his achievement as a philosopher of mountaineering, the man who wrote of one Alpine summit, Have we vanquished an enemy? None but ourselves.
Why did George Mallory, his 1924 expedition in treacherous straits, nevertheless make a last-ditch attempt to go for the summit of Mt. Everest--a decision that cost the lives of this seasoned climber and his young climbing partner, Andrew Irvine? To the Gillmans, British journalists and mountaineers who together retraced Mallory's 1921 reconnaissance expedition, the answer is plain: he hoped to resolve the conflict at the core of his marriage, to obviate the need for further expeditions and further separations from his beloved wife, Ruth. This vivid, illustrated biography is both a moving tribute to Mallory and a fresh reappraisal of the man and the legends surrounding him. While the authors take no position on whether or not Mallory and Irvine reached Everest's acme--a controversy intensified by the discovery of Mallory's body in 1999--they provide a useful summary of the ongoing debate. Drawing liberally on letters between Mallory and his wife, the Gillmans chart the highs and lows of a marriage strained by his periodic absences. While mountain climbing was for decades an imperialist's sport, Mallory did not fit the mold. A rector's son, he became a Fabian socialist and agnostic at Cambridge, making friends with poet Rupert Brooke, Robert Graves and Bloomsbury painter Duncan Grant, and indulging in a brief homosexual affair. Mallory's literary output includes a study of Boswell and an intense love sonnet to fianc e Ruth. Among the spate of recent books on Mallory's Everest expeditions, this biography stands out for its well-rounded, sensitive portrait of a restless, thoughtful adventurer. Photos. (Sept.) Copyright 2000 Cahners Business Information.|
6.05(w) x 9.01(h) x 0.82(d)

value: This website is an American bookseller. It is a Fortune 1000 company and the bookseller with the largest number of retail outlets in the United States.


text:
Amazon.co.uk: Noah's Ark's review of Moroccan & the Foods of North Africa (The ...
Food glorious Moroccan food/, 16 Dec. 2012
My first try at making good Moroccan food, and this book helps me on the way to impress my family and friends
Moroccan & the Foods of North Africa (The Australian Women's Weekly Essentials) 1863966277
Food glorious Moroccan food/
Top Reviewer Ranking: 58,473

value: This website is an American multinational technology company which focuses on e-commerce, cloud computing, digital streaming, and artificial intelligence.


text:
Patent US7719333 - Power control circuit, method of controlling power control circuit, and DLL ... - Google Patents
A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference...http://www.google.com/patents/US7719333?utm_source=gb-gplus-sharePatent US7719333 - Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit
Publication number US7719333 B2
Application number US 11/964,802
Also published as US8154326, US8742806, US20090002039, US20100213920, US20120194231
Publication number 11964802, 964802, US 7719333 B2, US 7719333B2, US-B2-7719333, US7719333 B2, US7719333B2
Inventors Won Joo YUN, Hyun Woo Lee, Dong Suk Shin
Patent Citations (14), Non-Patent Citations (1), Referenced by (2), Classifications (6), Legal Events (3)
Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit
US 7719333 B2
1. A power control circuit, comprising:
a check unit that receives a reference clock and generates a check signal using a control pulse signal which is toggled at every operation cycle of a DLL (Delay Locked Loop) circuit;
a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal; and
a signal combining unit that generates a power cutoff signal for cutting a power supply to the DLL circuit in response to a locking completion signal, the check signal, and the phase difference detection signal.
2. The power control circuit of claim 1,
wherein the check unit repeatedly enables the check signal by a time corresponding to an operation cycle of the DLL circuit.
3. The power control circuit of claim 1,
wherein the check unit includes:
a control pulse generator that divides the reference clock by a predetermined ratio and generates the control pulse signal in a pulsed manner; and
a shift register that shifts a logic high level in response to the control pulse signal, a reset signal, and a first pulse signal, and generates the check signal.
4. The power control circuit of claim 3,
wherein the first pulse signal has a toggle timing more advanced than the toggle timing of the control pulse signal.
5. The power control circuit of claim 3,
an initializer that receives a shift signal, the first pulse signal, and the reset signal, and generates an initialization signal; and
a shifter that is initialized in response to the initialization signal, and shifts the external power under the control of the control pulse signal to generate the shift signal and the check signal.
6. The power control circuit of claim 5,
wherein the initializer enables the initialization signal when the first pulse signal is toggled in a state where the check signal is enabled.
7. The power control circuit of claim 1,
wherein the phase detecting unit determines whether or not the phase difference between the reference clock and the feedback clock exceeds a predetermined range,
if the phase difference exceeds the predetermined range, enables the phase difference detection signal, and
if the phase difference is within the predetermined range, disables the phase difference detection signal.
8. The power control circuit of claim 7,
a phase difference detector that detects the phase difference between the reference clock and the feedback clock, and generates a detection signal; and
a latch that latches and inverts the detection signal in response to a first pulse signal and generates the phase difference detection signal.
9. The power control circuit of claim 8,
wherein the phase difference detector includes:
a first detector that determines whether or not the feedback clock has a more advanced phase than the reference clock for a first time or more, and generates a first detection signal;
a second detector that determines whether or not the reference clock has a more advanced phase than the feedback clock for a second time or more, and generates a second detection signal; and
a combiner that combines the first detection signal and the second detection signal, and generates the detection signal.
10. A power control circuit, comprising:
a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL (Delay Locked Loop) circuit;
a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal,
wherein the signal combining unit disables the power cutoff signal if the locking completion signal is disabled or if the phase difference detection signal or the check signal is enabled, and enables the power cutoff signal when the locking completion signal is enabled, and the phase difference detection signal and the check signal are disabled.
11. The power control circuit of claim 10,
wherein the signal combining unit includes:
a first combiner that combines the locking completion signal, the phase difference detection signal, and the check signal, and generates a combined signal;
a latch that latches the combined signal in response to a first pulse signal and outputs a latch signal; and
a second combiner that combines the combined signal and the latch signal, and outputs the power cutoff signal.
The present application claims priority under 35 U.S.C. 119(a) to Korean application number 10-2007-063069, filed on 26 Jun. 2007, in the Korean Patent Office, which is incorporated by reference in its entirety as if set forth in full.
The embodiments described herein relate to a semiconductor integrated circuit, and in particular, to a power control circuit that improves power efficiency, a method of controlling a power control circuit and a DLL circuit including power a control circuit.
In general, a DLL circuit generates an internal clock that has a more advanced phase than a reference clock (obtained by converting an external clock). The internal clock that is used in a semiconductor integrated circuit is delayed by a clock buffer and a transmission line to generate a phase difference between the internal clock and the external clock. Due to the phase difference, the output data access time is made longer. The DLL circuit is used to prevent the output data access time from being extended. As such, the DLL circuit controls the internal clock to have a more advanced phase than the external clock for a predetermined time, to thereby increase an effective data output period.
The DLL circuit includes a feedback loop that compares a feedback clock (generated by modeling the delay amount of the internal clock until it is transmitted to the data output buffer) with the reference clock. A delay block that delays the reference clock to generate the internal clock is configured to perform a coarse delay operation or a fine delay operation according to the phase difference between the feedback clock and the reference clock. The delay block selects one of the coarse delay mode and the fine delay mode depending on whether or not a locking completion signal transmitted from an operation mode setting apparatus is enabled. With this operation, the DLL circuit gives a fixed coarse delay time to the reference clock when the locking completion signal is enabled, and performs an operation to change the fine delay time, to thereby change the delay value that is given to the reference clock.
The operation cycle of the DLL circuit is determined by a toggle timing of one of a plurality of pulse signals, which are generated by a clock generating block. One of the plurality of pulse signals has a cycle larger than the reference clock (for example, two times), and is enabled at every predetermined number of cycles of the reference clock (for example, 20 cycles). The phase comparing block and the operation mode setting block of the DLL circuit operate in response to the one pulse signal. Therefore, the enable cycle of the pulse signal becomes the operation cycle of the DLL circuit.
As such, the DLL circuit detects the phase difference between the reference clock and the feedback clock at every operation cycle to determine whether or not locking is completed. Then, if it is determined that locking is completed, the DLL circuit does not significantly change the delay amount, which is applied to the reference clock. Therefore, the feedback loop that constitutes the DLL circuit is not necessarily activated after locking is completed.
However, the feedback loop of the DLL circuit is activated after locking is completed, and then power is continuously consumed. As semiconductor integrated circuits with low power consumption profiles may be advantageous for certain applications, it is desirable to improve the power efficiency of integrated circuits by eliminating power consumption factors.
A power control circuit that improves power efficiency after a clock delay locking operation are disclosed.
According to one aspect, a power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL (Delay Locked Loop) circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.
According to another aspect, a method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a DLL circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.
According to still another aspect, a DLL circuit includes a power control circuit that generates a power cutoff signal in response to a locking completion signal, a pulse signal, a reference clock, and a feedback clock, a clock generating apparatus that generates the pulse signal in response to the power cutoff signal, and a delay compensating apparatus that generates the feedback clock from a delayed clock in response to the power cutoff signal.
According to yet still another aspect, a method for controlling a DLL circuit includes cutting the power supply to a delay compensating block and a clock generating block when a delay locking operation is completed, allowing the power supply to the delay compensating block and the clock generating block for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine whether or not to allow the power supply to the delay compensating block and the clock generating block.
Whether or not the delay locking operation is completed can be determined according to whether or not a locking completion signal to be output from an operation mode setting block is enabled.
The predetermined time may be a time corresponding to an integer multiple of an operation cycle of a feedback loop, which includes the delay compensating block, the clock generating block, and the operation mode setting block.
The allowing of the power supply to the delay compensating block and the clock generating block may include dividing the reference clock by a predetermined ratio and generating a control pulse signal in a pulsed manner, shifting external power in response to the control pulse signal to generate a check signal, allowing the power supply to the delay compensating block and the clock generating block when the check signal is enabled, and disabling the check signal when a first pulse signal is enabled.
The re-determining of whether or not to allow the power supply may include determining whether or not the phase difference between the reference clock and the feedback clock exceeds a predetermined range. When the phase difference exceeds the predetermined range and the first pulse signal is enabled, enabling a phase difference detection signal. If the phase difference detection signal is enabled, maintaining the power supply to the delay compensating block and the clock generating block.
FIG. 1 is a block diagram showing the configuration of a DLL circuit according to an embodiment;
FIG. 2 is a diagram showing the detailed configuration of a power control block that can be included in the circuit shown in FIG. 1, in accordance with one embodiment;
FIG. 3 is a diagram showing the detailed configuration of a shift register that can be included in the power control block shown in FIG. 2, in accordance with one embodiment;
FIG. 4 is a diagram showing the detailed configuration of a phase difference detector that can be included in the power control block shown in FIG. 2, in accordance with one embodiment; and
FIG. 5 is a timing diagram illustrating the operation of the DLL circuit.
FIG. 1 is a diagram illustrating an example DLL circuit 11 configured in accordance with one embodiment. As shown in FIG. 1, the DLL circuit 11 can include a clock input buffer 10, a delay block 20, a clock driver 30, a delay compensating block 40, a clock generating block 50, a phase comparing block 60, an operation mode setting block 70, a delay control block 80, and a power control block 90.
The clock input buffer 10 can be configured to buffer an external clock “clk_ext” and to generate a reference clock “clk_ref.” The delay block 20 can be configured to delay the reference clock “clk_ref” in response to delay control signal “dlcnt” to generate a delayed clock “clk_dly.” The clock driver 30 can be configured to generate an output clock “clk_out” using the delayed clock “clk_dly.” The delay compensating block 40 can be configured to give a delay time, which can be obtained by modeling a delay amount of an output path of the delayed clock “clk_dly,” to the delayed clock “clk_dly” in response to a power cutoff signal “vscut” and generate a feedback clock “clk_fb.” The clock generating block 50 can be configured to receive the reference clock “clk_ref” in response to the power cutoff signal “vscut” and generate n pulse signals “pls<1:n>.” The phase comparing block 60 can be configured to compare the phase of the reference clock “clk_ref” with the phase of the feedback clock “clk_fb,” and to generate a phase comparison signal “phcmp.” The operation mode setting block 70 can be configured to generate a locking completion signal lock in response to the phase comparison signal “phcmp.” The delay control block 80 can be configured to generate the delay control signal “dlcnt” in response to the phase comparison signal “phcmp” and the locking completion signal lock. The power control block 90 can be configured to generate the power cutoff signal “vscut” in response to the locking completion signal lock, the reference clock “clk_ref,” and the feedback clock “clk_fb” under the control of first and second pulse signals “pls<1:2>” among the n pulse signals “pls<1:n>.”
Some of the n pulse signals “pls<1:n>” that are generated by the clock generating block 50 can be transmitted to the operation mode setting block 70 and the delay control block 80 to define the operation timing thereof. In this example, pulse signals that are input to the power control block 90 are the first pulse signal “pls1” and the second pulse signal “pls2.” The first pulse signal “pls1” can be a signal that has an enable timing after the operation mode setting block 70 determines whether or not locking is completed. Among the n pulse signals “pls<1:n>” and the second pulse signal “pls2” is a signal that has an enable timing later than the first pulse signal “pls1.”
The power control block 90 can be configured to disable the power cutoff signal “vscut” into a state where the locking completion signal lock is disabled. Accordingly, power can be supplied to the delay compensating block 40 and the clock generating block 50. That is, when a delay locking operation of the DLL circuit is not completed, a feedback loop in the DLL circuit can be activated.
Meanwhile, when the locking completion signal lock is enabled, the power control block 90 can be configured to enable the power cutoff signal “vscut” to cut power supply to the delay compensating block 40 and the clock generating block 50. It will be understood that the delay compensating block 40 and the clock generating block 50, in which power supply is cut by the power cutoff signal “vscut,” can be implemented via a change in design to the DLL circuit.
Subsequently, the power control block 90 can be configured to disable the power cutoff signal “vscut” for a cycle of every predetermined operation cycle of the DLL circuit, for example, 8 operation cycles. At that time, the cyclically activating of the feedback loop can be performed in order to check whether or not DLL circuit is operating normally.
At this time, the power control block 90 can be configured to detect a phase difference between the reference clock “clk_ref” and the feedback clock “clk_fb” to re-determine whether or not to enable the power cutoff signal “vscut.” If the phase difference between the reference clock “clk_ref” and the feedback clock “clk_fb” exceeds a predetermined range, the DLL circuit can be configured to activate the feedback loop and re-adjust the delay time that is given to the reference clock “clk_ref” by the delay block 20. In this case, therefore, the power control block 90 can be configured to maintain the power cutoff signal “vscut” disabled to supply the power to the delay compensating block 40 and the clock generating block 50.
The reason why the power control block 90 controls the power supply to the delay compensating block 40 is that, if the delay compensating block 40 is inactivated the feedback clock “clk_fb” is not generated, which may effectively inactivate the feedback loop in the DLL circuit. In addition, the reason why the power control block 90 controls the power supply to the clock generating block 50 is that, if the feedback loop in the DLL circuit is inactive, the generation of the n pulse signals “pls<1:n>” is insignificant.
Referring to FIG. 2, the power control block 90 can include a check unit 910, a phase detecting unit 920, and a signal combining unit 930.
The check unit 910 can be configured to receive the reference “clock clk_ref” and to generate a check signal “chk” for cyclically disabling the power cutoff signal “vscut.” The phase detecting unit 920 can be configured to detect the phase difference between the reference clock “clk_ref” and the feedback clock “clk_fb” in response to the first pulse signal “pls1,” and to generate a phase difference detection signal “phddtg.” The signal combining unit 930 can be configured to generate the power cutoff signal “vscut” in response to the locking completion signal “lock,” the phase difference detection signal “phddtg,” and the check signal “chk” under the control of the second pulse signal “pls2.”
The check unit 910 can be configured to divide the reference clock “clk_ref” by a predetermined ratio and generate a control pulse signal “cntpls” in a pulsed manner. The control pulse signal “cntpls” can be toggled at every operation cycle of the DLL circuit. The control pulse signal “cntpls” can preferably be enabled immediately after the second pulse signal “pls2.” The check unit 910 can be further configured to repeatedly enable the check signal “chk” by a time corresponding to the operation cycle of the DLL circuit. During this time, the check signal “chk” is preferably a low enable signal.
To this end, the check unit 910 can include a control pulse generator 912 and a shift register 914. The control pulse generator 912 can be configured to generate the control pulse signal “cntpls” from the reference clock “clk_ref.” The shift register 914 can be configured to shift external power VDD in response to the control pulse signal “cntpls,” a reset signal “rst,” and the second pulse signal “pls2” to generate check signal “chk.”
The control pulse generator 912 can be implemented so as to have the same configuration as the clock generating block 50 (as depicted in FIG. 1). However, whereas clock generating block 50 is deactivated by the power cutoff signal “vscut,” the control pulse generator 912 can be configured to operate regardless of whether or not the power cutoff signal “vscut” is enabled.
As described above, the phase detecting unit 920 is configured to determine whether or not the phase difference between the reference clock “clk_ref” and the feedback clock “clk_fb” exceeds a predetermined range. If the phase difference exceeds the predetermined range, the phase detecting unit 920 can be configured to enable the phase difference detection signal “phddtg.” If the phase difference is within the predetermined range, the phase detection unit 920 can be configured to disable the phase difference detection signal “phddtg.” At this time, the phase detecting unit 920 operates when the power cutoff signal “vscut” is disabled, the clock generating block 50 is activated, and the first pulse signal “pls1” is enabled. Here, the phase difference detection signal “phddtg” can be a low enable signal.
The phase detecting unit 920 can include a phase difference detector 922 that can be configured to detect the phase difference between the reference clock “clk_ref” and the feedback clock “clk_fb,” and generate a detection signal “dtg,” and a first latch 924 that is configured to latch and invert the detection signal “dtg” in response to the first pulse signal “pls1” and generate the phase difference detection signal “phddtg.”
The first latch 924 can be implemented with a first flip-flop (i.e., FF1) that operates in response to the first pulse signal “pls1,” and a first inverter (i.e., IV1) that inverts an output signal of the first flip-flop FF1.
The signal combining unit 930 can include a first combiner 932, a second latch 934 and a second combiner 936. The first combiner 932 can be configured to combine the locking completion signal lock, the phase difference detection signal “phddtg,” and the check signal “chk,” and generate a combined signal “cmb.” The second latch 934 can be configured to latch the combined signal “cmb” in response to the second pulse signal “pls2” and output a latch signal “lat.” The second combiner 936 can be configured to combine the combined signal “cmb” and the latch signal “lat,” and outputs power cutoff signal “vscut.”
Here, the first combiner 932 and the second combiner 936 can be implemented with logical AND structures, which include NAND gates (i.e., ND1 and ND2) and inverters (i.e., IV2 and IV3), respectively. In addition, the second latch 934 can preferably include a second flip-flop (i.e., FF2) that operates in response to the second pulse signal “pls2.”
With this structure, if the locking completion signal lock is disabled or if the phase difference detection signal “phddtg” or the check signal “chk” is enabled, the power cutoff signal “vscut” can be disabled. Meanwhile, if the locking completion signal lock is enabled, and the phase difference detection signal “phddtg” and the check signal “chk” are disabled, the power cutoff signal “vscut” can be enabled. However, whether or not to enable the phase difference detection signal “phddtg” is determined in a state where the check signal “chk” is enabled. The second latch 934 can be configured to perform an operation to determine a timing at which the power cutoff signal “vscut” is enabled.
As shown in FIG. 3, the shift register 914 can include an initializer 9142 and a shifter 9144. The initializer 9142 can be configured to receive a shift signal “shft,” the second pulse signal “pls2,” and the reset signal “rst,” and generate an initialization signal “init.” The shifter 9144 can be configured to be initialized in response to the initialization signal “init” and shift the external power VDD under the control of the control pulse signal “cntpls” to generate the shift signal “shft” and the check signal “chk.”
Here, the initializer 9142 includes a third NAND gate (i.e., ND3) that receives the shift signal “shft” and the second pulse signal “pls2,” a fourth inverter (i.e., IV4) that receives the reset signal “rst,” and a fourth NAND gate (i.e., ND4) that receives an output signal of the third NAND gate (i.e., ND3) and an output signal of the fourth inverter (i.e., IV4), and output the initialization signal “init.”
The shifter 9144 can include a plurality of third flip-flops (i.e., FF3) and a sixth inverter (i.e., IV6). The third flip-flops FF3 are connected with each other in series. Each of the third flip-flops FF3 can have a reset terminal, to which the initialization signal “init” can be input, and a clock terminal, to which the control pulse signal “cntpls” can be input. The first-stage third flip-flop FF3 can be supplied with the external power VDD through its input terminal, and each of the subsequent third flip-flops FF3 can receive the output signal of the previous-stage flip-flop FF3. The last-stage third flip-flop FF3 can be configured to output the shift signal “shft.” The sixth inverter IV6 can be configured to receive the shift signal “shft” and output the check signal “chk.”
Here, the reset signal “rst” can be a pulse signal that is enabled during the initial operation of the DLL circuit. After the third flip-flops FF3 are initialized in response to the reset signal “rst,” the shifter 9144 can sequentially shift a high-level signal corresponding to the external power VDD using the third flip-flops FF3 each time the control pulse signal “cntpls” is toggled. With this operation, if the high-level signal to be shifted passes through the last-stage third flip-flop FF3, the shift signal “shft” and the check signal “chk” are enabled. The enable timing of the check signal “chk” can be maintained until the initialization signal “init” is enabled. As such, if the second pulse signal “pls2” (which is enabled when the power cutoff signal “vscut” is disabled in a state where the shift signal “shft” is enabled) is input, the initialization signal “init” is enabled, and then the shift signal “shft” and the check signal “chk” are disabled.
That is, the control pulse signal “cntpls” represents the operation cycle of the DLL circuit, and it is determined according to the number of third flip-flops FF3 in the shifter 9144 and how many cycles of the DLL circuit lapse each time the check signal “chk” is enabled. As such, the check signal “chk” can be enabled at one operation cycle among a plurality of operation cycles of the DLL circuit, and the check signal “chk” can be disabled at the remaining operation cycles. Therefore, power that is consumed by the DLL circuit can be markedly reduced.
FIG. 4 is a diagram showing the detailed configuration of the phase difference detector 922 shown in FIG. 2, in accordance with one embodiment. As shown in FIG. 4, the phase difference detector 922 includes a first detector 9222, a second detector 9224, and a third combiner 9226.
The first detector 9222 can be configured to determine whether or not the feedback clock “clk_fb” has a more advanced phase than the reference clock “clk_ref” for a first time or more and generates a first detection signal det1. The second detector 9224 can be configured to determine whether or not the reference clock “clk_ref” has a more advanced phase than the feedback clock “clk_fb” for a second time or more and generates a second detection signal det2. The third combiner 9226 can be configured to combine the first detection signal “det1” and the second detection signal “det2”, and to generate the detection signal “dtg.”
Here, the first detector 9222 can include a first delay element DLY1 that can be configured to delay the feedback clock “clk_fb” for the first time, and a first phase comparator (i.e., PHDET1) that can be configured to compare the phase of an output signal of the first delay element (i.e., DLY1) with the phase of the reference clock “clk_ref,” and generate the first detection signal “det1.”
The second detector 9224 can include a second delay element (i.e., DLY2) that can be configured to delay the reference clock “clk_ref” for the second time, and a second phase comparator (i.e., PHDET2) that can be configured to compare the phase of an output signal of the second delay element DLY2 with the phase of the feedback clock “clk_fb” to generate the second detection signal “det2.”
The third combiner 9226 can include a sixth inverter (i.e., IV6) that can be configured to invert the second detection signal “det2,” and a fifth NAND gate (i.e., ND5) that can be configured to receive the first detection signal “det1” and an output signal of the sixth inverter IV6, and outputs the detection signal “dtg.”
Here, the first time and the second time can be the same, and the sum of the first time and the second time can become a detection range in which the phase difference between the reference clock “clk_ref” and the feedback clock “clk_fb” is detected by the phase difference detector 922. The first detection signal “det1” can preferably be a low enable signal, and the second detection signal “det2” can preferably be a high enable signal.
The first detector 9222 can be configured to enable the first detection signal “det1” when the feedback clock “clk_fb” has a more advanced phase than the reference clock “clk_ref” for the first time or more. The second detector 9224 can be configured to enable the second detection signal “det2” when the reference clock “clk_ref” has a more advanced phase than the feedback clock “clk_fb” for the second time or more. Subsequently, the third combiner 9226 can be configured to enable the detection signal “dtg” when the first detection signal “det1” or the second detection signal “det2” is enabled.
FIG. 5 is a timing diagram illustrating the operation of the DLL circuit 11. FIG. 5 shows the waveforms of the locking completion signal “lock,” the first pulse signal “pls1,” the second pulse signal “pls2,” the check signal “chk,” the phase difference detection signal “phddtg,” and the power cutoff signal “vscut.”
Referring to FIG. 5, it can be seen that, when the locking completion signal “lock” is disabled, the power cutoff signal “vscut” is also disabled. If the locking completion signal lock is enabled, the power cutoff signal “vscut” is also enabled. However, as the check signal “chk” is cyclically enabled, the power cutoff signal “vscut” is also cyclically disabled. It can be seen that the check signal “chk” is disabled according to the second pulse signal “pls2.”
FIG. 5 shows a case where the phase difference between the reference clock “clk_ref” and the feedback clock “clk_fb” exceeds the predetermined range at a second enable timing of the check signal “chk.” At this time, the phase difference detection signal “phddtg” can be enabled or disabled in response to the first pulse signal “pls1.” The power cutoff signal “vscut” can be disabled in response to the phase difference detection signal “phddtg” and the check signal “chk.” The power cutoff signal may be enabled at the toggle timing of the second pulse signal “pls2.”
As described in the above embodiments of the power control block (circuit) and the DLL circuit (including the same), power supply to a delay compensating block and clock generating block is cut when a locking completion signal is enabled, thereby reducing unnecessary power consumption. Meanwhile, power can be supplied again to the delay compensating block and the clock generating block at every predetermined number of operation cycles of the DLL circuit, to thereby check the operation of a feedback loop. At this time, when it is detected that a phase difference between a reference clock and a feedback clock exceeds a predetermined range, the power supply to the delay compensating block and the clock generating block is maintained. Subsequently, when it is determined that the DLL circuit is normally operating, the power supply to the delay compensating block and the clock generating block is cut, thereby reducing power consumption in the feedback loop. As a result, power efficiency can be improved, and a low-power semiconductor integrated circuit can be implemented.
US6329854 * Aug 31, 1999 Dec 11, 2001 Samsung Electronics Co., Ltd. Phase locked loop integrated circuits having dynamic phase locking characteristics and methods of operating same
US7098712 Jun 1, 2004 Aug 29, 2006 Hynix Semiconductor, Inc. Register controlled delay locked loop with reduced delay locking time
US20030098721 * Jun 3, 2002 May 29, 2003 Mitsubishi Denki Kabushiki Kaisha Phase comparator accurately comparing phases of two clock signals and clock generation circuit employing the same
JP2000195265A Title not available
KR20010104496A Title not available
KR20020040443A Title not available
KR20020075572A Title not available
1 US 7,161,399, 01/2007, Lin (withdrawn)
US8344771 * Nov 2, 2010 Jan 1, 2013 Hynix Semiconductor Inc. Delay locked loop of semiconductor integrated circuit and method for driving the same
WO2017112320A1 * Nov 23, 2016 Jun 29, 2017 Intel Corporation Flexible dll (delay locked loop) calibration
U.S. Classification 327/158, 327/142, 327/198
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YUN, WON JOO;LEE, HYUN WOO;SHIN, DONG SUK;REEL/FRAME:020328/0022

value: This website is a search engine provided by Google. Handling over 3.5 billion searches per day, it has a 92% share of the global search engine market.


text:
The Classroom Boogie by Tom Knight (CD, Sep-2004, CD Baby (distributor)) | eBay
The Classroom Boogie by Tom Knight (CD, Sep-2004, CD Baby (distributor))
742941116326
item 1 Tom Knight - Classroom Boogie [New CD] -Tom Knight - Classroom Boogie [New CD]
item 2 Classroom Boogie Audio CD -Classroom Boogie Audio CD
item 3 TOM KNIGHT - CLASSROOM BOOGIE NEW CD -TOM KNIGHT - CLASSROOM BOOGIE NEW CD
Boogie-Woogie Music CD
Compilation Blues Boogie-Woogie Music CDs & DVDs
Blues Import Boogie-Woogie Music CDs & DVDs


text:
Mehmet Senel - Semantic Scholar
Ravi P. Agarwala13
Emre Çevik12
Samir H. Saker12
Allan Peterson11
12Emre Çevik
8Ercan Tunç
8Said R. Grace
7Muamer Dervisevic
Oscillation Theorems for Second-Order Nonlinear Dynamic Equation on Time Scales
This paper concerns the oscillation of solutions to the second order non-lin ear dynamic equation (r(t)x∆ (t))∆ + p(t) f (xσ (t))g(x∆ (t)) = 0 on a time scaleT which is unbounded above. By using a… (More)
Mehmet Senel, Nadide Utku
It is the purpose of this paper to give oscillation criteria for the third-order neutral dynamic equations with continuously distributed delay, r(t) x(t) + b a p(t, η)x τ (t, η) η γ + d c q(t, ξ)f (x… (More)
Oscillation Theorems for Dynamic Equation on Time Scales
Samir H. Saker, Mehmet Senel
By using the generalized Riccati transformation and the inequality technique, we establish a oscillation criterion for certain non-linear secondorder dynamic equations with damping on a time scale.
Solubility enhancement of Non-Steroidal Anti-Inflammatory Drugs (NSAIDs) using polypolypropylene oxide core PAMAM dendrimers.
Fatma Ebru Koç, Mehmet Senel
The aim of the present study was to evaluate the aqueous solubility enhancement properties of polypropylene oxide cored PAMAM (PPO@PAMAM) dendrimers. The solubility of NSAIDs (Ketoprofen, Ibuprofen… (More)
Simple method for preparing glucose biosensor based on in-situ polypyrrole cross-linked chitosan/glucose oxidase/gold bionanocomposite film.
A film of chitosan-polypyrrole-gold nanoparticles was fabricated by in-situ chemical synthesis method and its application in glucose biosensor was investigated. The obtained biosensor exhibited a… (More)
An electrochemical immunosensor for sensitive detection of Escherichia coli O157:H7 by using chitosan, MWCNT, polypyrrole with gold nanoparticles hybrid sensing platform.
Ahmet Güner, Emre Çevik, Mehmet Senel, Lokman Alpsoy
An electrochemical immunosensor for the common food pathogen Escherichia coli O157:H7 was developed. This novel immunosensor based on the PPy/AuNP/MWCNT/Chi hybrid bionanocomposite modified pencil… (More)
Development of glucose biosensor based on reconstitution of glucose oxidase onto polymeric redox mediator coated pencil graphite electrodes.
Muamer D Dervišević, Emre Çevik, Mehmet Senel
In this study, a novel glucose biosensor was fabricated by reconstitutional immobilization of glucose oxidase (GOx) onto a poly(glycidyl methacrylate-co-vinylferrocene) (poly(GMA-co-VFc)) film coated… (More)
Muamer Dervisevic, Mehmet Senel, Tugba Sagir, Sevim Isik
The detection of cancer cells through important molecular recognition target such as sialic acid is significant for the clinical diagnosis and treatment. There are many electrochemical cytosensors… (More)
Oscillation Behavior of Third-Order Nonlinear Neutral Dynamic Equations on Time Scales with Distributed Deviating Arguments
The aim of this paper is to give oscillation criteria for the third-order neutral dynamic equations with distributed deviating arguments of the form [ r(t) ( [x(t) + p(t)x(τ(t))] )γ]∆ + ∫ d c f (t,… (More)
Preparation and in vitro evaluation of 5-flourouracil loaded magnetite-zeolite nanocomposite (5-FU-MZNC) for cancer drug delivery applications.
Tuğba Sağir, Merve Huysal, Zehra Durmus, Belma Zengin Kurt, Mehmet Senel, Sevim Işık
In this work, super paramagnetic magnetite nanoparticles were synthesized onto/into zeolite, then loaded with anti-cancer drug 5-fluorouracil (5-FU). The physical properties of the prepared… (More)

value: This website is an artificial-intelligence backed search engine for academic publications developed at the Allen Institute for AI and publicly released in November 2015. It uses advances in natural language processing to provide summaries for scholarly papers.


text: 245How to run `rails generate scaffold` when the model already exists?1Rails updating multiple Models of the same type in a post0Displaying and updating multiple models in one view102Rails Model find where not equal0How to add data from multiple models to same view (Rails 3.2)0Using 2 virtual attributes for 1 model field0Rails model multiple properties of the same model0Multiple forms to edit the same Model on the same page1Multiple Views Same Model1creating multiple objects of the same model in a single form

value: This website is a question and answer website for professional and enthusiast programmers. It is the flagship site of the Stack Exchange Network, created in 2008 by Jeff Atwood and Joel Spolsky.


text:
P. 1Danh Sach TCVN Thay the TCXD 2012 Dot 1Danh Sach TCVN Thay the TCXD 2012 Dot 1Ratings: (0)|Views: 371|Likes: 0Published by letuananhbList of changing TCVNList of changing TCVNMore info:Categories:Topics, Art & DesignPublished by: letuananhb on May 28, 2013Copyright:Attribution Non-commercialAvailability:Read on Scribd mobile: iPhone, iPad and Android.download as PDF, TXT or read online from ScribdFlag for inappropriate content|Add to collectionSee moreSee lesshttps://www.scribd.com/doc/144109600/Danh-Sach-TCVN-Thay-the-TCXD-2012-Dot-107/29/2014pdftextoriginal You're Reading a Free Preview
More From This Userplw0511cb1-1561-1e.pdfletuananhbGFA_Declaration-NonRes225Apr2011REVISED.pdfletuananhbBai Tap Co Loi Giai Dong Luc HocletuananhbConcrete Slab Design - Strip MethodletuananhbGFA Definition Part 2letuananhbGFA Definition Part 1letuananhbArea Definition Code EnletuananhbPiling SpecificationletuananhbAdvances in Grouting TechnologyletuananhbBasha Diaphragm WallletuananhbConcrete Basements the New Design GuideletuananhbSaigon Mc TowerletuananhbJet GroutingletuananhbKingpost DesignletuananhbTypes of Grouting MethodletuananhbThu Tuc Cap Gpxd So Xd TphcmletuananhbQuy trinh du anletuananhbVN Fire Protection CodeletuananhbVN Fire Protection CodeletuananhbQCVN07_2010_BXDletuananhbCau Tao Be Tong Cot ThepletuananhbD-hd Trinh Bay Lats Lvthsletuananhb3D Fracture-Plastic ModelletuananhbSem in a 3letuananhb

value: This website is an American e-book and audiobook subscription service that includes one million titles.


text:
Words containing lydist | Words that contain lydist
https://www.thefreedictionary.com/words-containing-lydist
Dictionary, Encyclopedia and Thesaurus - The Free Dictionary 10,934,155,583 visitors served
Found 1 words containing lydist. Browse our Scrabble Word Finder, Words With Friends cheat dictionary, and WordHub word solver to find words that contain lydist. Or use our Unscramble word solver to find your best possible play!
14 letter words containing lydistSee also
14 letter words containing lydist

value: This website is an American online dictionary and encyclopedia that aggregates information from various sources.


text:
9780130195654: Electronic Project Design and Fabrication (5th Edition) - AbeBooks - Ronald A. Reis: 0130195650
For courses in Shop Fabrication.Hands-on approach and carefully focused on key topics, this innovative text presents thorough coverage of the fundamentals of electronic design, fabrication, and documentation, PLUS a complete experience in creating electronic prototype devices. Students work their way through Sample, Exercise, and Elective Projects (covering all skill levels) and develop a thorough Project Report--with written and graphic documentation--delineating procedures, developments, and specifications of a project.
ELECTRONIC PROJECT DESIGN AND FABRICATION is more than just a project book. The fundamentals of prototype design, fabrication, and documentation are a part of each chapter. The student designs the circuit, breadboards it, designs and fabricates a printed circuit board, and encloses the project in a case. New to the fifth edition: "Something to Think About" mini-sections provide students with suggestions for further inquiry. Five new elective projects have been added to Chapter 17. Revised and new appendices, including information on electronic kit sources, electronic project design, and fabrication websites to visit. "About this title" may belong to another edition of this title.
1. Electronic Project Design and Fabrication (5th Edition)
Book Description Prentice Hall, 2001. Hardcover. Book Condition: New. Bookseller Inventory # P110130195650

value: This website is an e-commerce global online marketplace with seven websites that offer books, fine art, and collectables from sellers in over 50 countries. Launched in 1996, it specialises in used, rare and out-of-print books.