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Amazon.com : Sony DSCHX80/B High Zoom Point & Shoot Camera (Black) : Camera & Photo
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This item:Sony DSCHX80/B High Zoom Point & Shoot Camera (Black) $368.00
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This item Sony DSCHX80/B High Zoom Point & Shoot Camera (Black)
4 out of 5 stars (161) 4 out of 5 stars (306) 4 out of 5 stars (207) 4 out of 5 stars (9) 4 out of 5 stars (23) 4 out of 5 stars (366)
$368.00$368.00 $273.00$273.00 $448.00$448.00 $364.99$364.99 $209.95$209.95 Add to cart to see product details. Why?
Amazon.com PRIMESELLER Amazon.com PRIMESELLER Supercenter-USA Amazon.com
5 x 6.25 x 2.75 in 1.41 x 2.51 x 4.32 in 1.42 x 4.02 x 2.28 in — — 1.01 x 3.78 x 2.16 in
1.15 lbs 0.54 lb 0.54 lb — 1.28 lbs 4.8 ounces
18.2 megapixels — — 18.2 megapixels 18 megapixels 21.1 megapixels
30x 40x 30x 30x — 20x
1080p 1920 x 1280 (59.94 fps / 29.97 fps) 1920 x 1080 (60p, 60i, 30p, 24p), 1280 x 720 (30p) — 4k VCHD: 28M PS(1,920x1,080/60p) / 24M FX(1,920x1,080/60i) / 17M FH(1,920x1,080/60i),MP4: 12M(1,440x1,080/30fps) / 3M VGA(640x480/30fps)
electronic viewfinder fixed LCD LCD electronic viewfinder electronic viewfinder None
6.2 x 5 x 2.8 inches
#1,075 in Camera & Photo (See Top 100 in Camera & Photo)
#58 in Camera & Photo > Point & Shoot Digital Cameras
pictures features photos cameras viewfinder video images flash mode feature lens pocket dslr shots pop image manual flip photo selfies
S.C. Dallas
5.0 out of 5 starsOne of the best 1/2.3 sensor point & shoot!
This is my fourth Sony product after my purchase of Sony a7s, RX100, and RX100III (wife's cam). I currently also have the Lumix GH4 as I like to take videos as much as photos. I bought the HX80 as a gift for my niece. I would recommend this to anyone who doesn't quite need the prosumer 1" sensor point and shoot or who wants the extra zoom capabilities that the larger sensors can't pack in such a small form. I will work backwards and start with the cons then the pros.
* Smaller 1/2.3 sensor as opposed to 1" sensor (then again price is reflective of smaller sensor and the 1/2.3 sensor on the HX80 is back illuminated which makes it much nicer than other comparable sensors)
* No manual zoom
* Pop up viewfinder
* Flash that's semi-tiltable
* Quick menu with 12 customizable functions
* Full PASM modes for manual and semi-manual controls plus full auto modes if that's the preference
* Monitor that tilts 180 degrees for selfies
* 30X zoom fantastic for travelers
* High quality XAVC S video format up to 50mbps at 24p, 30p, and 60p (requires SDXC memory cards)
* PASM modes all available for video
* Video manual mode has auto-iso option (not all cameras allow video auto-iso in manual; i.e. the much more expensive RX100 doesn't have this option)
* 5-AXIS image stabilizer works great
* WIFI/NFC included plus downloadable apps
There are many more features that I could go on about this neat little point and shoot, just check out the spec sheets. At this price level, especially for those that like to shoot both photos and videos, the Sony HX80 in my opinion is one of the best 1/2.3 sensor pocket cameras. I hope you find this review helpful!
5.0 out of 5 starsLove this little camera - viewfinder is a MUST HAVE!
Love this little camera. I have DSLR cameras - and I wanted a tiny camera to complement such - i.e. when out shooting nature with a DSLR and long lens - I would also like to have a little pocket camera to capture the near scene and scenery. This HX80 fits in the pocket of your trousers with a 30x zoom and a view-finder - and can take amazing shots. With the tiny small sensor in the HX80 - will photos be as clear as a DSLR with a $2000 lens? No. Of course not. But this camera for what is does - is genius. The electronic viewfinder is critical for the images that I will attach here.
I was out bird watching with my SWAROVSKI binos - and spotted this iguana (St. Maarten) sunning itself on a dead snag far in the distance. Decided to try out my new HX80 to see what the zoom could do. Zoom is really good - but it would be worthless in this case without a view finder. See attached hand-held images for wide angle - and the 30x zoom on the iguana. The red arrow in the wide angle shows where the iguana is sunning itself.
Highly recommend as a nice pocket point and shoot.
5.0 out of 5 starsI love the active viewfinder
I mostly use Canon Digital SLR cameras, but I needed a small camera for a trip abroad. I particularly like the active viewfinder. It works great in very bright sunlight. So far the camera has met my expectations.
5.0 out of 5 starsStep up your social media game
I've been using this camera for a couple of weeks and here's a list of what I've shot so far:
Stuff in the daytime
A video of me making coffee
It's pretty easy and straight forward. It has two modes where the camera does pretty much everything for you. Superior Auto shoots a burst of photos and creates a composite of the images captured. It's pretty great if you're willing to hold the camera still for about two whole seconds for it to capture the scene. And I'm told it's best to use this mode in darker places to reduce noise, but I haven't tried that yet. I personally prefer the other mode, Intelligent Auto. This mode adjusts the settings according to the shooting conditions. It's quicker to get a picture in this mode while still automating a lot of the process in taking the picture.
Other photo modes include:
Scene Selection: Lets you pick one of the many preset for certain conditions so that things can be more predictable when you shoot. Gives you a little more control than the previous two modes.
Memory Recall: Lets you create some presets that you can recall.
Manual Exposure: Adjust aperture and shutter speed manually. I think this mode is meant to be used for long exposure photos.
Shutter Priority: Adjust only the shutter speed manually.
Aperture Priority:Adjust only the aperture manually.
Program Auto: Sets both aperture and shutter speed automatically, while the other settings can be set manually.
iSweep Panorama: Shoot a panorama picture. You can set the direction you want to sweep, so you can shoot horizontally or vertically.
Videos are a whole other story with this camera. The first thing to talk about is the video quality when filming. It can capture in 1080p and 60 frames per second in three formats. The first format is MP4, which is the preferred format for YouTube. If you intend to shoot a video that will be uploaded directly up to YouTube, this is the video format to use. I shot a little YouTube video using the "AVCHD 60p 28M(PS)", which was the maximum setting for that video format. It looks good, but when I went to edit it, I can only export into MP4 or some other formats, so next time I'll just use MP4. I couldn't tell the difference anyway when I compared two videos in both formats. There's also the "XAVC S HD" video format, which is said to be suited for shooting movies, but apparently my SD card isn't good enough for it, so I have to wait for my new SDXC card to arrive. I probably won't need it.
Another thing to keep in mind when filming with this camera is the 5-axis stabilization feature. Basically, it's a feature where the sensor in the camera is being mechanically stabilized, giving you no compromise in quality when shooting stabilized video. Most cameras handle this digitally by cropping the actual video and outputting an upscaled version of the cropped video. Depending on how much you shake, you can notice a huge drop in video quality if you use digital stabilization. This camera does not have that issue. An interesting this to keep in mind is that when the feature is on, you can notice the camera adjusting the sensor when you set the camera down, which creates this feeling like you're on a boat or something even though it's sitting on the counter or s sturdy surface.
When it comes to audio, the stereo speakers are located on top of the camera. They're located in a way that makes it pretty impossible to stick fluff to, which is something I see a lot of people do to mitigate wind noises when shooting videos. It does have a feature `There's also no way, that I know of, to connect an external microphone, so that internal microphone is all you have. So far, I don't have any problems with it, but I also don't shoot videos where I talk and I haven't been to any concerts since I bought this.
The flash is hidden away inside of the camera until you hit a switch to pop it up. This means if you want to use the flash, you have to pop it up every time and also remember to push it back down when you're done with it. It sounds like a chore, but it could be a good thing. When you don't need it, you have the assurance that it won't go off when you shoot, because it's tucked away. The flash is located directly above the sensor, so the lighting it provides is pretty centered on the subject.
Auto-focusing was kind of a pain to deal with. The only explanation I've found on how it works is that it auto-focuses on the nearest subject in the center of view. I can see it's pretty quick at auto-focusing, but I can't seem to figure out how to make it focus on what I want it to focus on. I guess I just need to do a lot more research on this.
Transferring photos and videos off this camera is SUPER easy! I connected my phone (Sony Xperia XZ) via NFC and the QR code it provides and both of them work super quickly and the transfer starts right away. Usually takes about 3 seconds for an 18mp photo, which is about 4 MB. You do need to download the PlayMemories app on your phone.
There's an OLED viewfinder that pops up and down. By default, it turns on the camera when it pops up and turns it off when you push it back down. You can turn that off in the setting. It has a proximity sensor that automatically turns on the screen in the viewfinder when you bring it close to your eye. I personally don't use this feature, because I have to get really close to it to set the sensor off and my nose ends up touching the screen below, which is gross in the Summer when I'm sweaty and the sweat gets on the screen.
The flip up screen is amazing! It would automatically flip the image and the HUD. By default, when you flip up the screen and press the shutter button, it has a 3 second timer before taking the picture. You can turn that off in the settings. Also the camera has Smile-Shutter where it detects smiles would take a picture automatically.
Another feature I find to be extremely useful, but haven't gotten around to using, is the facial registration. You can program the camera to recognize up to 8 faces and it uses these faces to prioritize autofocusing and the smile shutter.
The feature I use the most, however, is the built-in level. This will help you keep your camera level in both landscape and portrait mode. It's very useful for panorama pictures and capturing video.
Finally, there's a button in the bottom right corner of the camera with a question mark on it. This button gives you hints and explanations on pretty much every feature on the camera. Just go to any option or setting and press the button for help. It's been pretty helpful for me in troubleshooting and learning how to better utilize the many features.
In order to record a video, you have to press the dedicated video button, which is the circular button on the top right corner with the label MOVIE above it. Even if you're in Movie mode, you have to press that button. This is an issue when you shoot a video of yourself, since you have to feel around and find that button to start and stop the video and it's VERY annoying.
You can also use the PlayMemories app to remotely control your camera, but I don't like it. It kinda lags and there's almost no point in using it. You're better off buying a camera remote from Sony.
Even though I had issues with some of the things about the camera, most of those issues can pretty much be resolved with a little research and further experimentation. I'm not a professional photographer or a vlogger and my Xperia XZ can take better pictures and videos than this can, but it is a reliable camera with greater zoom capability (30x) and a lot of features to explore. It doesn't excel in any field, but it's also far from the worst in every field, so you end up with what can only be described as decent. I do plan to continue using this camera a lot more. I'd say if you're not a professional photographer or a vlogger, this is the best camera you can get for around $300. This is the camera you would buy if you want to step up your Instagram pictures and videos or just need to use something that's more natural to hold and use than your phone. I've done just that with a lot of my recent Instagram posts and I'd say this camera is doing a phenomenal job at that. I'd even go so far to say that this is the perfect small camera on the market in this price range.
5.0 out of 5 starsA stunning achievement in a small package.
Wow! This camera will not disappoint. I purchased this as a gift to replace a clunky DSLR. The camera is incredible. The optical zoom is amazing and you still get an incredible digital zoom in addition. It is only slightly larger than an iPhone yet has all the features of a much larger camera. The flash is tiny in size yet extremely capable. The pop up eye piece takes a little getting accustomed to but is very functional and activates when you look through it like magic. If you think your phone is good enough for your pictures, try this camera, it will change your mind.
5.0 out of 5 starsA excellent travel camera that will fit in your pocket ...
A excellent travel camera that will fit in your shirt or pants pocket and takes amazing pics. I bought this camera for our trip out west and was very pleased with the images. Below are my pics from the Valley of Fire & Joshua Tree National Park, You will not be disappointed with this purchase.
5.0 out of 5 starsA great little travel camera
As advertised. A great little travel camera. Takes good pictures and is trouble free.
5.0 out of 5 starsIt was fast and took really good pics. Perfect travel camera
Took 1200+ pics on our trip to Jamaica. It was fast and took really good pics. Perfect travel camera. Did not miss not lugging around DSLR and lenses for the week.
I really like the camera perfect for vlogging
4.0 out of 5 starsThis camera performs slightly better than advertised
This camera performs slightly better than advertised. Everything you could want in a compact point-and-shoot is there, and with one of the best compact long range zooms.Read more
Got it from best buy. Really good camera for the price!
5.0 out of 5 starsIssa camera
Great entry level point and shoot camera. Amazing zoom for those small objects in your life.
5.0 out of 5 starsPoint and shoot camera! Simple
I needed a camera for a trip to Ireland and this did the trick. Wanted something I could point and shoot so this was the best choice for the price.
5.0 out of 5 starsPerfect for Serious Amatuer.
This camera has so many manual controls its almost like a DSLR. The zoom is overkill and makes it heavy, but the pictures are super clear and the video is sharp too.
2.0 out of 5 starsPoor quality Images, but could be useful for vlogging or general photos
I got this camera to replace my wrx350. I loved that little camera and it was great to carry at times when my DSLR was not practical.Read more
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 Lexis Port Dickson in Malaysia - Room Deals, Photos & Reviews
Book Lexis Port Dickson
(4714 reviews)See what guests said
Masjid Jalan Lama1.51 km
Kuil Sri Maha Mariamman1.59 km
Masjid Daerah Port Dickson1.66 km
Tesco Lukut1.9 km
Masjid Kariah Kg. Paya2.04 km
Alive 3D Art Gallery2.52 km
Batu 2 Jalan Seremban, Taman Tanjung, Port Dickson, Malaysia, - See map
"The hotel was spacious, there were 2 king beds and your own personal huge swimming pool inside the room."
Mas - January 2, 2019
Rooms available at Lexis Port Dickson
Premium Double Tower Seaview
What people love about Lexis Port Dickson
"A lot of convenient facilities, super friendly staff, delicious breakfast."
"Recommend to come at off peak season with more value package"
"Good room cleanliness is ok. tq."
"We had very great time here."
"Wonderful stay even though just for 1 night."
Vickneswarie
Alive 3D Art Gallery - 2.52 km
Kota Lukut - 4.35 km
Army Museum - 9.12 km
Wan Loong Chinese Temple - 11.16 km
Teluk Kemang Beach - 12.54 km
Upside Down Art Gallery - 14.91 km
Blue Lagoon Beach - 16.49 km
Cape Rachado Lighthouse - 17.17 km
Fort Kempas - 27.68 km
PD Ostrich Show Farm - 32.9 km
Masjid Jalan Lama - 1.51 km
Masjid Daerah Port Dickson - 1.66 km
Tesco Lukut - 1.9 km
Masjid Kariah Kg. Paya - 2.04 km
Reviews of Lexis Port Dickson from real guests
Agoda Reviews (4714)Booking.com Reviews (1584)
8-9 Excellent (610)
7-8 Very Good (1167)
6-7 Good (534)
<6 Below Expectation (607)
Jun - Aug (939)
Sep - Nov (784)
Dec - Feb (998)
All guests (4714)
Family with young children (2177)
Family with older children (503)
The one thing that needed to be mentioned were the staffs which were all very friendly, smiles on their faces and always eager to help. The environment was excellent and we got lucky to be staying in the water chalet which was a top notch experience for everyone. Will definitely choose this hotel to stay when we are in PD the next time with a huge spread of breakfast! Excellent!
Dear Edwin, Thank you for choosing to stay at Lexis Port Dickson. We are glad that you were overall satisfied with your stay, and it was a pleasure being of service to you. The team look forward to welcoming you back to the resort soon. Warm regards, The Management
Hotel did not well maintain its room. Unpleasant smell in room and it is noisy when you walk around in room because some of the wood are detached. Only 1 out of 3 lifts is functioning, waited quite some time for lift and ended up need to use staircase.
Dear Yuen, Thank you for your feedback. We would like to apologize for the shortfall of services that you have experienced and will be sure to share your remarks with the team for future improvements. We look forward to an opportunity of welcoming you back to Lexis Port Dickson with better service delivery in future. Warm regards, The Management
Good resort for holiday. ”
Good resort for holiday.
Dear Rex, Thank you for choosing to stay at Lexis during your recent trip to Port Dickson. We are pleased to learn that you were satisfied with your stay experience. We certainly look forward to another opportunity to be of service to you again soon. Warm regards, The Management
It was my 1st time in PD with my family and despite the reviews I went ahead with booking a family suite. I wanted my children to experience the closeness to the ocean that was my 1st priority. Upon arrival, the staff didn’t hesitate to upgrade my family to the family suite facing the sea which is what I wanted. I was impressed by their initiative and superb service. Overall was a superb experience which my family and I enjoyed the 2 nights stay. Breakfast was good and the view was scenic thank you for the great hospitality which makes my stay an impressionable one..
Good service from front desk(Fareena) and the concierge staff. Got an upgrade to the water chalet which was a pleasant surprise. Relaxing hotel and kids had a good time at the pool and beach. Breakfast spread was good though the area around the juice dispenser was al wet and someone nearly had a bad fall, slipping on the wet floor.
Front desk staffs: super friendly even though is peak season but they are very helpful. Room cleanliness: is clean though but still have certain area they miss out. Location: nr to Lukut town where you can find many seafood restaurant and food court. However there is few restaurant will increase the pricing during peak season which is not worth it. The distance to the famous curry chicken bun is near. Facilities: great place for family with kids. You can bring ur kids for train ride(Rm10/ride)which ride within the hotel area, archery (for elder kids n adult), mini car ride(rm10) and few more. There is a game room and movie room too. You can rent a bike and roam around the hotel area. Beach is like 2-3 mins walking distance. In-house pool is so small esp when is crowed with guest during peak hours. Breakfast: consider good and variety. They open up the ball room for guest during peak season to ensure all guest have place to enjoy their breakfast. Well done to the mgmt. Overall, I’m hpy with their staffs and enjoy the stay.
Great family retreat ”
Superb location to spend a wonderful time with family and young children. I booked 4 rooms and was upgraded to Premier Water Chalet, rooms was superb and spacious for a family with young children. Spread of breakfast was good too. Overall a A+ to Lexis Port Dickson. For sure I will be back
Great weekend escape from Singapore. We Got upgraded for this stay which added to our pleasure. The rooms were great. The Beach is good for kids. Safe. Staff was friendly. Breakfast was good. Can’t ask for more.
Great vacay with kid”
We arrived at approx. 4pm but the room still not yet ready. After performing Zohor, we went back to the reception and our room was upgraded. Thank you! My nephew was amazed and very excited with the view from Premier Water Chalet.
Stones Throw Away from the City”
It's merely 2 hours drive from KL and closer still if you are travelling from KLIA. My family stayed in the over-the-water chalets with a private pool. It was a celebration I sponsored for my brother in law's birthday, father's day, mother's day, and a brief reprieve for my son before his major exams this year. I would say the rooms are spacious and can comfortably fit 4 people (2 large king sized beds) so perfect for a family with kids. We booked 2 rooms and it fit 7 of us comfortably. The private pool was the first time in years my father and mother decided to take a dip together (they are close to 80) without being too self conscious. Highly recommended.
Dear Nurul, Thank you for your feedback. We are pleased to learn that you were satisfied with your stay experience. We certainly look forward to another opportunity to be of service to you again soon. Warm regards, The Management
Zehan from Malaysia
The view outside of the room is kinda pretty with sea breeze and gentle wind blowing at night. Overall, it was quite satisfied except that the price is abit too high!
Dear Tan, We are delighted you have chosen Lexis Port Dickson as your preferred choice of accommodation during your trip to Port Dickson. Thank you for your positive feedback and looking forward to extend our hospitality to you again soon. Warm regards, The Management
spacious room great breakfast well kept and clean friendly and accommodating staff from the desk, to banquet, to guards and concierge. will come again
Dear HASNIZA, We are delighted you have chosen Lexis Port Dickson as your preferred choice of accommodation during your trip to Port Dickson. Thank you for your positive feedback and looking forward to extend our hospitality to you again soon. Warm regards, The Management
Overall the villa is old ,swimming pool.is small ,breakfast food and area need to be improve ,noodle soup or nasi lemak is all cold and the area is full of flies. Only thing I'm impress is the helfup and friendly staff.
We received a complimentary upgrade to the grand lexis hotel which is next door which was a very pleasant surprise. The staff were very friendly and helpful throughout our stay. The private pool in our room was a delight. Thank you lexis team for the wonderful stay.
A piece of mind. ”
Value for money with every penny spent. Clean bedroom with no bedbug or insect and mosquito. I was happy with the security guards there. Felt safer. And receptionist responded fast. Indoor parking(free) available. Wifi at room. Toilet, shower room and bathtub separated from bedroom which is good. Breakfast included with international breakfast standard. Variety of choice. Just that got lots of flies. Hope mgt can solve this issue. Friendly staff. Buggy service responded fast too. This location also convineint going to restaurants, food stalls and mini market. 5 mins drive. Here is a more private place to enjoy quality time with family. Had a real relaxation here. Definitely will recommend friends over here. There are lots of facilities which you can browse through at their web which I won't elaborate again. All family members were happy with the choice staying here. Just come and enjoy.
Clean and comfortable room. Polite staff.”
Booked Lexis premium tower sea view. However, was upgraded to Grand Lexis with private pool upon arrival. Spacious oom with 2 king size bed. Room was clean. Children enjoy playing in the games room@level 2.

type: global

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Patrick H. - Games Gateway - U.S. Mid Atlantic Region (Arlington, VA)
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I love video games! I always have and always will. It's amazing to watch genre evolve into the multi-faceted medium of storytelling, artistic expression, education, social interaction, and still remain a fun way to kill time and entertain myself.
1,843 Househeads

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text:
Patent US6483344 - Interconnect circuitry for implementing logic functions in a field ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThere is disclosed a field programmable gate array that performs in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, normally performed in the configurable logic blocks of the FPGA. The field programmable gate array comprises: 1) a plurality of configurable logic...http://www.google.com/patents/US6483344?utm_source=gb-gplus-sharePatent US6483344 - Interconnect circuitry for implementing logic functions in a field programmable gate array and method of operationAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6483344 B2Publication typeGrantApplication numberUS 09/773,320Publication dateNov 19, 2002Filing dateJan 31, 2001Priority dateJan 31, 2001Fee statusPaidAlso published asUS20020101259Publication number09773320, 773320, US 6483344 B2, US 6483344B2, US-B2-6483344, US6483344 B2, US6483344B2InventorsVidyabhusan GuptaOriginal AssigneeStmicroelectronics, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (2), Referenced by (64), Classifications (12), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetInterconnect circuitry for implementing logic functions in a field programmable gate array and method of operation
US 6483344 B2Abstract
There is disclosed a field programmable gate array that performs in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, normally performed in the configurable logic blocks of the FPGA. The field programmable gate array comprises: 1) a plurality of configurable logic blocks (CLBs); 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches. The interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes the first and second interconnects to be coupled to a third interconnect, and causes the third interconnect to be coupled to a pull-up device coupled to a power supply source of the field programmable gate array. The first, second and third interconnects and the pull-up device thereby form a two-input OR gate.
What is claimed is: 1. A field programmable gate array comprising:
a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes said first and second interconnects to be coupled to a third interconnect, and causes said third interconnect to be coupled to a pull-up device coupled to a power supply source of said field programmable gate array, said first, second and third interconnects and said pull-up device thereby forming a two-input NOR gate. 2. The field programmable gate array as set forth in claim 1 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
3. The field programmable gate array as set forth in claim 2 wherein said memory comprises a static read only memory.
4. The field programmable gate array as set forth in claim 3 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
5. The field programmable gate array as set forth in claim 1 wherein said pull-up device is a pull-up transistor.
6. The field programmable gate array as set forth in claim 1 further comprising a buffer having an input coupled to said third interconnect and an output coupled to an input of a third CLB.
7. The field programmable gate array as set forth in claim 6 wherein said buffer is a non-inverting line driver.
8. The field programmable gate array as set forth in claim 6 wherein said buffer is an inverting line driver, said first, second and third interconnects, said pull-up device, and said buffer thereby forming a two-input OR gate.
9. A system-on-a-chip integrated circuit comprising:
a main memory for storing main program instructions; a processing circuit capable of executing said main program instructions; a plurality of embedded circuit components; and a field programmable gate array comprising: a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes said first and second interconnects to be coupled to a third interconnect, and causes said third interconnect to be coupled to a pull-up device coupled to a power supply source of said field programmable gate array, said first, second and third interconnects and said pull-up device thereby forming a two-input NOR gate. 10. The system-on-a-chip integrated circuit as set forth in claim 9 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
11. The system-on-a-chip integrated circuit as set forth in claim 10 wherein said memory comprises a static read only memory.
12. The system-on-a-chip integrated circuit as set forth in claim 11 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
13. The system-on-a-chip integrated circuit as set forth in claim 9 wherein said pull-up device is a pull-up transistor.
14. The system-on-a-chip integrated circuit as set forth in claim 9 further comprising a buffer having an input coupled to said third interconnect and an output coupled to an input of a third CLB.
15. The system-on-a-chip integrated circuit as set forth in claim 14 wherein said buffer is a non-inverting line driver.
16. The system-on-a-chip integrated circuit as set forth in claim 14 wherein said buffer is an inverting line driver, said first, second and third interconnects, said pull-up device, and said buffer thereby forming a two-input OR gate.
17. A field programmable gate array comprising:
a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration couples N interconnects between N CLB outputs and a common interconnect, each of said N interconnects being coupled between one CLB output and said common interconnect, and wherein said interconnect switch controller couples said common interconnect to a pull-up device coupled to a power supply source of said field programmable gate array, said N interconnects, said common interconnect, and said pull-up device thereby forming an N-input NOR gate. 18. The field programmable gate array as set forth in claim 17 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
19. The field programmable gate array as set forth in claim 18 wherein said memory comprises a static read only memory.
20. The field programmable gate array as set forth in claim 17 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
21. The field programmable gate array as set forth in claim 17 wherein said pull-up device is a pull-up transistor.
22. The field programmable gate array as set forth in claim 17 further comprising a buffer having an input coupled to said common interconnect and an output coupled to an input of a CLB.
23. The field programmable gate array as set forth in claim 22 wherein said buffer is a non-inverting line driver.
24. The field programmable gate array as set forth in claim 23 wherein said buffer is an inverting line driver, said N interconnects, said common interconnect, said pull-up device, and said buffer thereby forming an N-input OR gate.
25. The field programmable gate array comprising:
a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes said first and second interconnects to be coupled to a third interconnect, and causes said third interconnect to be coupled to a pull-up device coupled to a power supply source of said field programmable gate array, said first, second and third interconnects and said pull-up device thereby forming a logic state. 26. The field programmable gate array as set forth in claim 25 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
27. The field programmable gate array as set forth in claim 26 wherein said memory comprises a static read only memory.
28. The field programmable gate array as set forth in claim 27 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
29. The field programmable gate array as set forth in claim 25 wherein said pull-up device is a pull-up transistor.
30. The field programmable gate array as set forth in claim 25 further comprising a buffer having an input coupled to said third interconnect and an output coupled to an input of a third CLB.
31. The field programmable gate array as set forth in claim 30 wherein said buffer is a non-inverting line driver.
32. The field programmable gate array as set forth in claim 30 wherein saif first, second and third interconnects, said pull-up device, and said buffer form a two-input NOR gate.
33. The field programmable gate array as set forth in claim 30 wherein said buffer in an inverting line driver, said first, second and third interconnects, said pull-up device, and said buffer thereby forming a two-input OR gate.
34. A system-on-a-chip integrated circuit comprising:
a main memory for storing mean program instructions; a processing circuit capable of executing said main program instructions; a plurality of embedded circuit components; and a field programmable gate array comprising: a plurality of configurable logic blocks (CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration causes a first interconnect to be couple to an output of a first and second interconnects to be coupled to a third interconnect, and causes said third interconnect to be coupled to a pull-up device coupled to a power of said field programmable gate array, said first, second and third interconnects and said pull-up device thereby forming a logic gate. 35. The system-on-a-chip integrated circuit as set forth in claim 34 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
36. The system-on-a-chip integrated circuit as set forth in claim 35 wherein said memory comprises a static read only memory.
37. The system-on-a-chip integrated circuit as set forth in claim 36 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
38. The system-on-a-chip integrated circuit as set forth in claim 34 wherein said pull-up device is a pull-up transistor.
39. The system-on-a-chip integrated circuit as set forth in claim 34 further comprising a buffer having an input coupled to said third interconnect and an output coupled to an input of a third CLB.
40. The system-on-a-chip integrated circuit as set forth in claim 39 wherein said buffer is a non-inverting line driver.
41. The system-on-a-chip integrated circuit as set forth in claim 40 wherein said first, second and third interconnects, said pull-up device, and said buffer from a two-input NOR gate.
42. The system-on-a-chip integrated circuit as set forth in claim 39 wherein said buffer is an inverting line driver, said first, second and third interconnects, said pull-up device, and said buffer thereby forming a two-input OR gate.
43. A field programmable gate array comprising:
a plurality of configurable logic blocks )CLBs); a plurality of interconnects; a plurality of interconnect switches capable of coupling ones of said plurality of interconnects to each other and to inputs and outputs of said plurality of configurable logic blocks; and an interconnect switch controller capable of controlling said plurality of interconnect switches, wherein said interconnect switch controller in a first switch configuration couples N interconnects between N CLB outputs and a common interconnect, each of said N interconnects being coupled between one CLB output and said common interconnect, and wherein said interconnect switch controller couples said common interconnect to a pull-up device coupled to a power supply source of said field programmable gate array, said N interconnects, said common interconnect, and said pull-up device thereby forming a logic gate. 44. The field programmable gate array as set forth in claim 43 wherein said interconnect switch controller comprises a memory capable of storing said first switch configuration.
45. The field programmable gate array as set forth in claim 44 wherein said memory comprises a static read only memory.
46. The field programmable gate array as set forth in claim 43 wherein said interconnect switch controller comprises at least one configurable logic block in said field programmable gate array.
47. The field programmable gate array as set forth in claim 43 wherein said pull-up device is a pull-up transistor.
48. The field programmable gate array as set forth in claim 43 further comprising a buffer having an input coupled to said common interconnect and an output coupled to an input of a CLB.
49. The field programmable gate array as set forth in claim 48 wherein said buffer is a non-inverting line driver.
50. The field programmable gate array as set forth in claim 49 wherein said N interconnects, said common interconnect, said pull-up device, and said buffer from an N-input NOR gate.
51. The field programmable gate array as set forth in claim 48 wherein said buffer is an inverting line driver, said N-interconnects, said common interconnect, said pull-up device, and said buffer thereby forming an N-input OR gate.
The present invention is related to that disclosed in U.S. patent application Ser. No. 09/774,891 filed concurrently herewith, entitled “INTERCONNECT CIRCUITRY FOR IMPLEMENTING BIT-SWAP FUNCTIONS IN A FIELD PROGRAMMABLE GATE ARRAY AND METHOD OF OPERATION”. Patent application Ser. No. 09/774,891 is commonly assigned to the assignee of the present invention. The disclosure of this related patent application is hereby incorporated by reference for all purposes as if fully set forth herein.
The present invention is generally directed to field programmable gate array (FPGA) circuits, a more specifically to an FPGA circuit in which logic functions may be implemented by the interconnect circuitry between logic blocks.
The speed, power, and complexity of integrated circuits, such as microprocessor chips, random access memory (RAM) chips, application specific integrated circuit (ASIC) chips, and the like, have increased dramatically in the last twenty years. More recently, these increases have led to development of so-called system-on-a-chip (SoC) devices. A SoC device allows nearly all of the components of a complex system, such as a cell phone or a television receiver, to be integrated onto a single piece of silicon. This level of integration greatly reduces the size and power consumption of the system, while generally also reducing manufacturing costs.
A key component in many highly integrated circuits, including SoC devices, is the field programmable gate array (FPGA). FPGA circuits are a particular class of general purpose integrated circuits (ICs) that can be configured (i.e., programmed) to perform a wide range of tasks. There are a number of different types of FPGA circuit topologies, including symmetrical array, row-based, sea-of-gates, and hierarchical programmable logic device (PLD). Each of these FPGA types has certain advantages over other types, depending on the specific application.
FPGA circuits generally are implemented using one of four technologies: static RAM cells, anti-fuse, EPROM transistors, and EEPROM transistors. In static RAM technology, programmable connections in the FPGA are made using pass transistors, transmission gates, or multiplexers controlled by a static random access memory (RAM) cell. Static RAM cells technology allow fast reconfiguration of a FPGA circuit. Anti-fuse technology uses an anti-fuse that is initially a high-impedance connection path (i.e., open circuit). The anti-fuse is then programmed into a low impedance (i.e., short circuit) or fused state. While anti-fuse technology is simple and less expensive than static RAM technology, an anti-fuse is a “program once” device. EPROM and EEPROM technologies use the same methods that are used in EPROM memories.
There are three primary configurable elements in a FPGA circuit: configurable logic blocks (CLBs), input/output (I/O) blocks, and programmable interconnects. The configurable logic blocks contain a variety of different logic functions, such as look-up tables (LUTs), registers, multiplexer (MUX) gates, programmable logic arrays (PLDs) programmable logic devices (PLDs), and the like. A programmable interconnect generally connects a single output of a CLB to an input of another CLB. An interconnect comprises metal wires and transistors that act as pass gates and signal buffers that preserve the signal integrity. Control of the interconnect transistors may be provided by an SRAM cell, a flash RAM cell, or external pins. The programming of an interconnect is usually done in a static fashion, such as at the power-up of a stand-alone FPGA circuit, especially for flash RAM and SRAM based configurations. The I/O blocks provide the interface between the external pins of the IC package and the internal signals lines, including the programmable interconnects.
Despite the considerable advancements made in field programmable gate array circuits, however, there remains room for improvement. There is a limitation to the complexity of the logic functions that may be implemented in a FPGA circuit of a particular size and density. More complex functions call for still greater FPGA density. However, this greater density must be achieved without incurring larger latencies due to increased propagation times through the FPGA circuit.
Therefore, there is a need in the art for system-on-a-chip (SoC) devices and other large scale integrated circuits that implement improved field programmable gate array (FPGA) circuits. In particular, there is a need for FPGA circuits, including embedded FPGA circuits, that achieve greater density and/or utilization over standard FPGA technologies. More particularly, there is a need for improved FPGA circuits that are capable of performing more complex logical functions while minimizing propagation times.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a field programmable gate array capable of performing in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, that are normally performed in the configurable logic blocks of the FPGA. According to an advantageous embodiment of the present invention, the field programmable gate array comprises: 1) a plurality of configurable logic blocks (CLBs); 2) a plurality of interconnects; 3) a plurality of interconnect switches capable of coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller capable of controlling the plurality of interconnect switches. The interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes the first and second interconnects to be coupled to a third interconnect, and causes the third interconnect to be coupled to a pull-up device coupled to a power supply source of the field programmable gate array. The first, second and third interconnects and the pull-up device thereby form a two-input NOR gate.
According to one embodiment of the present invention, the interconnect switch controller comprises a memory capable of storing the first switch configuration.
According to another embodiment of the present invention, the memory comprises a static read only memory.
According to still another embodiment of the present invention, the interconnect switch controller comprises at least one configurable logic block in the field programmable gate array.
According to yet another embodiment of the present invention, the pull-up device is a pull-up transistor.
According to a further embodiment of the present invention, the field programmable gate array further comprises a buffer having an input coupled to the third interconnect and an output coupled to an input of a third CLB.
According to a still further embodiment of the present invention, the buffer is a non-inverting line driver.
According to a yet further embodiment of the present invention, the buffer is an inverting line driver, such that the first, second and third interconnects, the pull-up device, and the buffer thereby form a two-input OR gate.
FIG. 1 illustrates a processing system that includes an exemplary system-on-a-chip (SoC) device according to one embodiment of the present invention;
FIGS. 2A-2D illustrate various circuit topologies of the field programmable gate array (FPGA) in the exemplary SoC device in FIG. 1;
FIGS. 3A and 3B illustrate an exemplary bit swap device implemented with programmable interconnects that is operable to receive an N-bit input value and generate a re-ordered N-bit output value according to one embodiment of the present invention; and
FIG. 4 illustrates an exemplary Boolean logic gate in the embedded FPGA implemented with programmable interconnects according to one embodiment of the present invention.
FIGS. 1 through 4, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged field programmable gate array (FPGA).
FIG. 1 illustrates processing system 100, which includes exemplary system-on-a-chip (SoC) device 105 according to one embodiment of the present invention. SoC device 105 is a single integrated circuit comprising embedded field programmable gate array (FPGA) 115, optional FPGA built-in self test (BIST) circuit 116, peripheral circuits 120 and 125, microprocessor 130, random access memory (RAM) 135, read-only memory (ROM) 140, configurable bus 150, main (or system) bus 160, and bridge circuit 150. In an exemplary embodiment of the present invention, processing system 100 also comprises external memory 110, which may be, for example, a flash memory, a random access memory, a disc storage device, or the like. Optional FPGA built-in self test (BIST) circuit 116 is used to perform BIST testing on embedded FPGA device 115 in the event of a reboot or other event that requires the execution of BIST functions.
Processing system 100 is shown in a general level of detail because it is intended to represent any one of a wide variety of electronic devices, particularly consumer appliances. For example, processing system 100 may be a printer rendering system for use in a conventional laser printer. Processing system 100 also may represent selected portions of the video and audio compression-decompression circuitry of a video playback system, such as a video cassette recorder or a digital versatile disk (DVD) player. In another alternative embodiment, processing system 100 may comprise selected portions of a cable television set-top box or a stereo receiver.
Embedded FPGA 115 and peripheral circuits 120 and 125, which are arbitrarily labeled Circuit Block 1 and Circuit Block 2, respectively, may be configured to implement any designated function in processing system 100. For example, peripheral circuit 120 may be a video codec and peripheral circuit 125 may be an audio code. In the ordinary operation of processing system 100, embedded FPGA 115 also may be a video codec, and audio coded, or some other functional unit, such as a bus controller for configurable bus 150.
In an exemplary embodiment of the present invention, microprocessor 130 executes an application program that may be stored in RAM 135. ROM 140 stores a start-up program that is executed by microprocessor 130 after a system reboot. Address and data information is transferred between microprocessor 130, RAM 135 and ROM 140 via main bus 160. Similarly, address and data information may be transferred between peripheral devices 120 and 125 and embedded FPGA 115 via configurable bus 150. Data traffic may be transferred between configurable bus 160 and main bus 160 via bridge 170, which provides isolation between configurable bus 150 and main bus 160 to increase overall system throughput.
According to the principles of the present invention, embedded FPGA 115 comprises configuration static random access memory (SRAM) 117, configurable logic blocks (CLBs), input/output (I/O) blocks, and programmable interconnects. The configurable logic blocks contain a variety of different logic functions, such as look-up tables (LUTs), registers, multiplexer (MUX) gates, programmable logic arrays (PLDs), programmable logic devices (PLDs), and the like. However, the programmable interconnects in FPGA 115 differ from the interconnects of prior art FPGA circuits, which merely provide connections between the outputs of some CLBs and the inputs of other CLBs. The programmable interconnects in FPGA 115 are selectively connected under the control of configuration SRAM 117 (or designated CLBS) in order to implement selected logical operations, including Boolean operators (i.e., AND, NAND, OR, NOR, and similar functions).
FIGS. 2A-2D illustrate various circuit topologies of field programmable gate array (FPGA) 115 in exemplary SoC device 105. FIG. 2A illustrates FPGA 115A, which uses a symmetrical array topology. A symmetrical array topology comprises a plurality of configurable logic blocks (CLBs), such as exemplary CLB 205A, arranged in an N×M matrix and separated by vertical columns and horizontal rows of interconnects, such as exemplary interconnect 210A. The inputs and outputs of the CLBs are selectively connectable to the rows and columns of interconnects. FIG. 2B illustrates FPGA 115B, which uses a row-based topology. A row-based topology comprises a plurality of configurable logic blocks (CLBs), such as exemplary CLB 205B, arranged in a plurality of rows and separated by horizontal rows of interconnects, such as exemplary interconnect 210B. The inputs and outputs of the CLBs are selectively connectable to the rows of interconnects.
FIG. 2C illustrates FPGA 115C, which uses a sea-of-gates topology. A sea-of-gates topology comprises a plurality of comparatively simple logic gates, such as exemplary logic gate 205C, arranged in an R×C matrix and separated by vertical columns and horizontal rows of interconnects, such as exemplary interconnect 210C. The inputs and outputs of the logic gates are selectively connectable to the rows and columns of interconnects. FIG. 2D illustrates FPGA 115D, which uses a hierarchical programmable logic device (PLD) topology. A hierarchical programmable logic device topology comprises a plurality of programmable logic devices, such as exemplary PLD 205D, that are selectively connectable by a plurality of interconnects, such as exemplary interconnect 210D. An FPGA circuit having programmable interconnects that perform selected logical operations according to the principles of the present invention may be embodied as anyone of the foregoing circuit topologies, as well as other FPGA circuit topologies.
FIGS. 3A and 3B illustrate exemplary bit swap device 300 in FPGA 115 that uses programmable interconnects to receive an N-bit input value and generate a re-ordered N-bit output value according to one embodiment of the present invention. The bit swap operation can be described as follows. Given a N-bit value X, where each of the bits is described by the concatenation [X(N−1), X(N−2), . . . , X2, X1, X0] and an N-bit value Y, where each of the bits is described by the concatenation [Y(N−1), Y(N−2), . . . , Y2, X1, X0], the value Y can be related to the value X according to the following relationship:
Y(N−1)=X 0, Y(N−2)=X 1, . . . Y 2=X(N−3), Y 1=X(N−2), Y 0=X(N−1).
This operation is often performed when handling data that has different “endianess”, thereby requiring the program to convert between little endian format (least significant bit or byte first) and big endian format (most significant bit or byte first). According to the principles of the present invention, the endian conversion operation may be executed by the programmable interconnects in FPGA 115, rather than in a configurable logic block, by reprogramming 2N switches between the interconnects. The 2N switches may be controlled by switch position settings stored in configuration SRAM 117 or by one or more configuration CLBs. This results in a bit swap operation that is carried out with very little circuit overhead and with a major reduction in circuit area. One key point is that the configuration bits of the routing array are able to be set by the logic inside of the FPGA itself.
In the exemplary circuit in FIG. 3A, it is assumed that the X value and the Y value have the same endian format (i.e., both big endian format or both little endian format). For the sake of simplicity in explaining the operation of the bit swap device, it is assumed that X and Y are 16-bit values. Thus, X0=Y0, X1=Y1, . . . , X15=Y15. The sixteen bits of the value X are coupled to programmable vertical interconnects that are labeled X0, X1, X2, . . . , X15 for convenience. The sixteen bits of the value Y are coupled to programmable vertical interconnects that are labeled Y0, Y1, Y2, . . . , Y15 for convenience.
Bit swap device 300 in FPGA 115 also comprises programmable horizontal interconnects, including exemplary programmable horizontal interconnects 341, 342, 343 and 344. Any one of the programmable vertical interconnects, X0, X1, . . . , X15 and Y0, Y1, . . . , Y15 may be selectively coupled to anyone of the programmable horizontal interconnects by closing interconnect switches, such as exemplary interconnect switches 301-310, disposed at the junctions of the vertical and horizontal interconnects. In FIGS. 3A and 3B, closed interconnect switches are shown as a square with an X therein and open interconnect switches are shown as an empty square. Thus, interconnect switch 301 and interconnect switches 304-310 are closed and interconnect switches 302 and 303, among others, are open.
As FIG. 3A shows, vertical interconnect X0 and vertical interconnect Y0 are both connected to horizontal interconnect 341. Similarly, vertical interconnect X1 and vertical interconnect Y1 are both connected to horizontal interconnect 342. This connection scheme continues through vertical interconnect X15 and vertical interconnect Y15, which are both connected to horizontal interconnect 344. In this manner, the X value and the Y value have the same endian format, such that X0=Y0, X1=Y1, . . . , X15=Y15. The interconnect switches are set by switch select lines that may be controlled by, for example, a static random access memory (SRAM). Groups of exemplary switch select lines (shown as dotted lines) are designated by reference numbers 320 and 330. The exemplary switch select lines designated by reference number 320 control exemplary interconnect switches 301-304.
However, the endian format can easily be reversed by selectively resetting the interconnect switches that couple the vertical interconnects and the horizontal interconnects. As FIG. 3B illustrates, the interconnect switches that couple the vertical interconnects Y0-Y15 to the horizontal interconnects have been reset to reverse the endian format. Thus, interconnect switch 307 is open and interconnect switch 311 is closed, so that vertical interconnect Y0 is now coupled to vertical interconnect X15, rather that to vertical interconnect X0. Similarly, interconnect switch 308 is open and interconnect switch 312 is closed, so that vertical interconnect Y1 is now coupled to vertical interconnect X14, rather that to vertical interconnect X1. Continuing this process, it can be seen that the X value and the Y value have different endian formats, such that X0=Y15, X1=Y14, . . . , X15=Y0.
In the exemplary embodiment described above, bit swap device 300 reverses the order of all of the N-bits in the X value and Y value. More generally speaking, however, bit swap device 300 may re-order bits according to any selected algorithm. For instance, in the example above, bit swap device 300 may instead be configured to swap the most significant byte (MSB) and least significant byte (LSB) in the 16-bit X and Y values, while preserving order within each byte. Thus, the initial ordering may be as follows:
LSB=X 0=Y 0, X 1=Y 1, . . . , X 7=Y 7;
MSB=X 8=Y 8, X 9=Y 9, . . . , X 15=Y 5.
However, after bit swap device 300 re-orders the bits, the final ordering may be as follows:
LSB=X 0=Y 8, X 1=Y 9, . . . , X 7=Y 15;
MSB=X 8=Y 0, X 9=Y 1, . . . , X 15=Y 7.
Another way to improve the computational capability of the programmable interconnects in an FPGA is to increase the signal aggregation ability. For instance, if a number of CLBs are able to transmit data over the same wiring, there is a corresponding reduction in the required routing complexity of the FPGA. Examples of logical functions that benefit from this type of improvement are Logic 1 detectors and Logic 0 detectors. These functions are used to detect at least one Logic 1 value or all Logic 0 values in a set of data bits. More complex functions like overflow detection and threshold detection rely on these more basic functions. Implementing a conventional Logic 1 detector or Logic 0 detector in a FPGA consumes a fair amount of CLB resources. However, an FPGA that implements logical functions using the programmable interconnects in accordance with the principles of the present invention eases these requirements.
FIG. 4 illustrates exemplary Boolean logic gate 400 in FPGA 115 implemented with programmable interconnects according to one embodiment of the present invention. Boolean logic gate 400 comprises transistors 411-416, output interconnects 421-426, horizontal interconnects 431 and 432, vertical interconnects 441 and 442, interconnect switches 451-456, interconnect switches 461-464, buffer 470, and pull-up transistor 480. As will be explained below in greater detail, Boolean logic gate 400 may function as a wired OR gate or a wired NOR gate, depending on whether buffer 470 is an inverting buffer or a non-inverting buffer. Boolean logic gate 400 may be used to detect the presence of at least one Logic 1 value and to detect the presence of all Logic 0 values.
Transistors 411-416 are N-type transistors that may comprise the output drive transistors in configurable logic blocks, programmable logic devices, or simple logic gates in FPGA 115. The outputs of transistors 411-416 are the output interconnects 421-426, respectively. Output interconnects 421-423 may be coupled to vertical interconnect 441 by interconnect switches 451-453, respectively. Output interconnects 424-426 may be coupled to vertical interconnect 442 by interconnect switches 454-456, respectively.
Vertical interconnect 441 may be coupled to horizontal interconnects 431 and 432 by interconnect switches 461 and 462, respectively. Vertical interconnect 442 may be coupled to horizontal interconnects 431 and 432 by interconnect switches 463 and 464, respectively. In FIG. 4, closed interconnect switches are shown as a square with an X therein and open interconnect switches are shown as an empty square. Thus, interconnect switches 451-454 and interconnect switches 462 and 464 are closed and interconnect switches 455, 456, 461 and 463 are open.
In effect, the outputs of transistors 411-414 are shorted to each other and are connected to pull-up transistor 480. This forms a wired-OR gate. The gates of transistors 411-416 are the signals A, B, C, D, E and F. The outputs of transistors 415 and 416 are not used (i.e., open-circuited). Thus, the input of buffer 470 is the OR result of A, B, C and D. If buffer 470 is non-inverting, the OUT signal is equal to the OR result of A, B, C and D (i.e., A OR B OR C OR D). If buffer 470 is inverting, the OUT signal is equal to the NOR result of A, B, C and D.
Advantageously, the interconnect switches may be reset to give different OR and NOR results. For example, if interconnect switches 453 and 454 are opened and interconnect switches 455 and 456 are closed, the input of buffer 470 is the OR result of A, B, E and F. Similarly, buffer 470 may be reset to switch between an OR result (non-inverting) and a NOR result (inverting).
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20010131Apr 27, 2006FPAYFee paymentYear of fee payment: 4Apr 29, 2010FPAYFee paymentYear of fee payment: 8Apr 28, 2014FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services

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text:
Oppdag Asmara | Booking.com
→ Asmara
Sunshine Hotel ligger i Asmara, og har terrasse, utsikt over hagen og gratis Wi-Fi overalt. Som gjest kan du spise i restauranten eller bestille drikke i baren. «The fruit juice was out of this world! Food fresh and large portions.
Overall was not regrettable.»
Hotel Asmara Palace har et utendørsbasseng og en solterrasse, og ligger i Asmara. Du kan hygge deg i restauranten på hotellet. Avgiftsfri, privat parkering er tilgjengelig på stedet. «Compared to the rest of the Asmara, it is a luxury hotel. Facilities and common areas are great, services good. I was happy to have clean water and as much as I wanted.»
Situated in Asmara, 900 metres from Asmara Paediatric Hospital, Crystal Hotel features free WiFi access and free private parking. Guests can enjoy the on-site restaurant. Crystal Hotel
Set 1 km from Asmara Paediatric Hospital in Asmara, Hamasien Hotel features a restaurant, bar and free WiFi throughout the property. Guests can enjoy the on-site restaurant. Hamasien Hotel
Embasoira Hotel is set in Asmara, 1 km from Asmara Paediatric Hospital. Guests can enjoy the on-site bar. Free private parking is available on site. Embasoira Hotel
Offering a terrace and views of the city, The Sunshine House is located in Asmara. Free private parking is available on site. All rooms come with a TV. The Sunshine House
Featuring free WiFi, Albergo Italia offers accommodation in Asmara, 1 km from Independence Stadium (Asmara). Guests can enjoy the on-site bar. Free private parking is available on site. Albergo Italia
Africa Pension offers accommodation in Asmara. There is a shared lounge at the property. Independence Stadium (Asmara) is 1 km from Africa Pension, while Asmara Paediatric Hospital is 1.2 km away.
169255|6,178394,180140,173978,169255|3,177770,176822,177358,174230,169255,173748,176707,180808,169251,177258,178210,173978|1,176971,174945,174995,180483,178577

value: This website is a Dutch online travel agency for lodging reservations & other travel products, and a subsidiary of Booking Holdings. It is headquartered in Amsterdam.The website has over 28 million listings.