text:
Patent US20050269629 - Fin field effect transistors and methods of fabricating the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin....http://www.google.com/patents/US20050269629?utm_source=gb-gplus-sharePatent US20050269629 - Fin field effect transistors and methods of fabricating the sameAdvanced Patent SearchPublication numberUS20050269629 A1Publication typeApplicationApplication numberUS 11/084,922Publication dateDec 8, 2005Filing dateMar 21, 2005Priority dateMar 23, 2004Also published asUS7332386Publication number084922, 11084922, US 2005/0269629 A1, US 2005/269629 A1, US 20050269629 A1, US 20050269629A1, US 2005269629 A1, US 2005269629A1, US-A1-20050269629, US-A1-2005269629, US2005/0269629A1, US2005/269629A1, US20050269629 A1, US20050269629A1, US2005269629 A1, US2005269629A1InventorsChul Lee, Min-Sang Kim, Dong-gun Park, Choong-ho Lee, Chang-Woo Oh, Jae-Man Yoon, Dong-won Kim, Jeong-Dong Choe, Ming Li, Hye-Jin ChoOriginal AssigneeChul Lee, Min-Sang Kim, Park Dong-Gun, Lee Choong-Ho, Chang-Woo Oh, Jae-Man Yoon, Kim Dong-Won, Jeong-Dong Choe, Ming Li, Hye-Jin ChoExport CitationBiBTeX, EndNote, RefManReferenced by (16), Classifications (25), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetFin field effect transistors and methods of fabricating the sameUS 20050269629 A1Abstract A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin. Images(14) Claims(25)
1. A fin field effect transistor (FinFET) comprising: a substrate; a fin that is on and extends laterally along and vertically away from the substrate; a gate electrode covering sides and a top of a portion of the fin; a gate insulation layer between the gate electrode and the fin; and a source region and a drain region in the fin adjacent to opposite sides of the gate electrode, wherein the source region of the fin has a different width than the drain region of the fin. 2. The FinFET of claim 1, wherein: the source region of the fin has a smaller width than the drain region of the fin. 3. The FinFET of claim 1, wherein a portion of the fin under the gate electrode has an abrupt change in width. 4. The FinFET of claim 3, wherein the abrupt change in width of the fin under the gate electrode forms sidewalls of the fin having a T-shape. 5. A fin field effect transistor (FinFET) comprising: a substrate; a fin that is on and extends laterally along and vertically away from the substrate; a gate electrode covering sides and a top of a portion of the fin; a source region and a drain region in the fin adjacent to opposite sides of the gate electrode, wherein the drain region of the fin has a greater width than the source region of the fin; and a channel region in the fin between the source region and the drain region, wherein an impurity concentration of the channel region that is adjacent to the drain region is higher than the impurity concentration of the channel region that is adjacent to the source region. 6. The FinFET of claim 5, wherein a portion of the fin under the gate electrode has an abrupt change in width. 7. The FinFET of claim 6, wherein the abrupt change in width of the fin under the gate electrode forms sidewalls of the fin having a T-shape. 8. The FinFET of claim 5, wherein the fin tapers off from the drain region to the source region. 9. The FinFET of claim 5, wherein: the channel region adjacent to the source region has about the same impurity concentration as the substrate, and the channel region adjacent to the drain region has a higher impurity concentration than the substrate. 10. A fin field effect transistor (FinFET) comprising: a substrate; a fin that is on and extends laterally along and vertically away from the substrate; a pair of gate electrodes, each of the gate electrodes covering sides and a top of adjacent portions of the fin; a gate insulation layer between the pair of gate electrodes and the fin; and a common drain region in the fin between the pair of gate electrodes; and a pair of source regions in the fin, each of the source regions is adjacent to a side of a different one of the pair of gate electrodes and opposite to the common drain region, wherein the source region of the fin has a different width than the common drain region of the fin. 11. The FinFET of claim 10, wherein: the source regions of the fin have a smaller width than the common drain region of the fin. 12. The FinFET of claim 10, wherein a portion of the fin under each of the pair of gate electrodes has an abrupt change in width. 13. The FinFET of claim 10, wherein the fin tapers off in width from the common drain region to the source regions. 14. A fin field effect transistor (FinFET) comprising: a substrate; a fin that is on and extends laterally along and vertically away from the substrate; a pair of gate electrodes, each of the gate electrodes covering sides and a top of adjacent portions of the fin; a gate insulation layer between the pair of gate electrodes and the fin; and a common drain region in the fin between the pair of gate electrodes; a pair of source regions in the fin, each of the source regions is adjacent to a side of a different one of the pair of gate electrodes and opposite to the common drain region; and a channel region in the fin between the common drain region and the source regions, wherein the channel region adjacent to the common drain region has a higher impurity concentration than the channel region adjacent to the source regions. 15. The FinFET of claim 14, wherein: the source regions of the fin have a smaller width than the common drain region of the fin. 16. The FinFET of claim 15, wherein a portion of the fin under each of the pair of gate electrodes has an abrupt change in width. 17. The FinFET of claim 14, wherein the fin tapers off in width from the common drain region to the source regions. 18. The FinFET of claim 14, wherein: the channel region adjacent to the source region has about the same impurity concentration as the substrate, and the channel region adjacent to the common drain region has a higher impurity concentration than the substrate. 19. A method for fabricating a fin field effect transistor (FinFET), the method comprising: providing a substrate; forming a fin on the substrate and extending laterally along and vertically away from the substrate, wherein a first region of the fin has a first fin width and a second region of the fin has a second fin width, wherein the second fin width is larger than the first fin width; forming a gate insulation layer on a portion of the fin; and forming a gate electrode on the gate insulating layer and covering sides and a top of a portion of the fin. 20. The method of claim 19, wherein forming a fin comprises: patterning the substrate to form the fin therefrom, wherein the formed fin has the second fin width; forming a mask pattern on the fin; oxidizing a sidewall of the fin to form a sacrificial oxide layer while using the mask pattern as an oxidation barrier layer; removing the sacrificial oxide layer to form the first region of the fin having the first fin width; and removing the mask pattern to expose the second region of the fin having the second fin width. 21. The method of claim 20, wherein providing a substrate comprises: providing a support substrate; forming a buried insulating layer on the support substrate; forming a semiconductor layer on the buried insulating layer, and wherein patterning the substrate to form the fin therefrom comprises patterning the semiconductor substrate to form the fin therefrom. 22. The method of claim 19, wherein: providing a substrate comprises providing a semiconductor substrate; and forming a fin on the substrate comprises patterning the semiconductor substrate to form the fin therefrom, and further comprising forming a device isolation layer on the semiconductor substrate and the fin. 23. The method of claim 22, wherein forming a device isolation layer comprises: forming a liner layer on the semiconductor substrate and the fin; forming an insulation layer on the liner layer; recessing a portion of the insulation layer to expose the liner layer; and recessing the liner layer to partially expose sidewalls of the fin. 24. A method for fabricating a fin field effect transistor (FinFET), the method comprising: providing a substrate; forming a fin on the substrate and extending laterally along and vertically away from the substrate, wherein a first region of the fin has a first fin width and a second region of the fin has a second fin width, wherein the second fin width is larger than the first fin width; forming a gate insulation layer on a portion of the fin; forming a gate electrode on the gate insulating layer and covering sides and a top of a portion of the fin; implanting impurities of a first conduction type into one side of the gate electrode; and implanting impurities of a second conduction type into the fin, using the gate electrode as an ion implanting mask, to form a source region in the first region, to form a drain region in the second region, and to form a first diffusion layer in a channel region adjacent to the drain region, wherein the source and drain regions define the channel region. 25. The method of claim 24, wherein: implanting impurities of a second conduction type into the fin comprises implanting the second conduction type impurities with a shorter lateral diffusion distance than a lateral diffusion distance of the first conduction-type impurities. Description
RELATED APPLICATION This application claims the benefit of and priority to Korean Patent Application No. 10-2004-0019711, filed Mar. 23, 2004, and to Korean Patent Application No. 10-2004-0071798, filed Sep. 8, 2004, the disclosures of which are hereby incorporated herein by reference. FIELD OF THE INVENTION The present invention relates to semiconductor devices, and, more particularly, a fin field effect transistor with a vertical channel and related methods of fabricating fin field effect transistors. BACKGROUND OF THE INVENTION The continuing trend to fabricate semiconductor devices with smaller device features has led to some difficulties when trying to scale-down transistors that have a horizontal channel (hereinafter referred to as �horizontal channel transistors�). Two difficulties that can arise when trying to scale-down horizontal channel transistors are short channel effect and drain induced barrier lower (DIBL) effect. When a channel length of a transistor is reduced to 50 nanometers or less, the dispersion of device characteristics can become high due to fabrication process variations. When the channel length is 30 nanometers or less, the channel effect and DIBL effect can become so severe that the resulting transistor will operate abnormally. Various different types of transistors have been developed to overcome some of the limitations associated with fabricating horizontal channel transistors. One such transistor is a double gate transistor. The double gate transistor includes a channel that may have a length of 30 nanometers or less, and a single gate on the channel or two gates on opposite sides of the channel. Because a conventional transistor has a gate electrode formed only over a horizontal channel, an electric field is asymmetrically applied to a top and bottom of the channel to prevent the turning on/off of the transistor from being controlled by the gate electrode. In contrast, because a double gate electrode has two gate electrodes on opposite sides of a thin channel, an entire area of the channel is affected by the gate electrode. Thus, when the transistor is turned off, charge flow between a source and a drain may be suppressed to reduce power dissipation and to control the turning on-off of the transistor. A double gate transistor using a damascene gate is disclosed in U.S. Patent Publication No. 2002/0177263 entitled �DAMASCENE DOUBLE-GATE MOSFET WITH VERTICAL CHANNEL REGIONS�, issued to Hussein et al. FIG. 1 is a perspective view of a damascene double gate MOS transistor, such as that disclosed in U.S. Patent Publication No. 2002/0177263. As illustrated in FIG. 1, a transistor 14 includes a silicon layer 10 on an insulator 12 and a gate electrode 28 that extends across the silicon layer 10. A hard mask pattern 18 is on the silicon layer 10, and the gate electrode 28 is on the hard mask pattern 18. A gate insulator 30 is between the gate electrode 28 and a sidewall of the silicon layer 10. A source/drain region 22 is formed in the silicon layer 10 adjacent to opposite sides of the gate electrode 28. As previously discussed, a double MOS transistor with a vertical channel has a narrow silicon layer in which a channel is formed. The gate may thereby exhibit a high controllability for the channel. Because a typical silicon layer has a width ranging from several nanometers to dozens of nanometers, the transistor is often called a fin field effect transistor (hereinafter referred to as �FinFET�) due to its shape. One difficulty in using FinFETs is that threshold voltages can vary considerably depending upon variations in their fabrication processes. Consequently, it can be difficult to control the threshold voltage of the transistor and provide cell uniformity in a high-density memory device. Lowering of the threshold voltage of a transistor can increase the sub-threshold voltage leakage. Leakage current of a transistor results in degradation of the devices made therefrom. For example, leakage current can result in degradation of the data retention characteristics of a DRAM device. Consequently, it can be important to minimize leakage current of, for example, a source region to which a capacitor is connected. A channel concentration can be raised to increase a threshold voltage of the transistor. However, increased threshold voltage can cause a decrease in the turn-on current of the transistor, and increased channel concentration can cause an increase in junction current. Therefore, when such a transistor is used in a DRAM device, the decreased turn-on current can reduce a write margin, and the increased storage node junction leakage can deteriorate a data retention characteristic of the DRAM device. SUMMARY OF THE INVENTION In some embodiments of the present invention, a fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region are in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin. In some further embodiments of the present invention, the source region of the fin has a smaller width than the drain region of the fin. A portion of the fin under the gate electrode can have an abrupt change in width. The abrupt change in width of the fin under the gate electrode can form sidewalls of the fin that have a T-shape. In some other embodiments of the present invention, a FinFET includes a substrate, a fin, a gate electrode, source and drain regions in the fin, and a channel region in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top portion of the fin. The source region and the drain region in the fin are adjacent to opposite sides of the gate electrode. The drain region of the fin has a greater width than the source region of the fin. The channel region in the fin is between the source region and the drain region. An impurity concentration of the channel region that is adjacent to the drain region is higher than the impurity concentration of the channel region that is adjacent to the source region. In some further embodiments of the present invention, a portion of the fin under the gate electrode has an abrupt change in width. The abrupt change in width of the fin under the gate electrode can form sidewalls of the fin that have a T-shape. The fin can taper off from the drain region to the source region. The channel region that is adjacent to the source region can have about the same impurity concentration as the substrate, and the channel region that is adjacent to the drain region can have a higher impurity concentration than the substrate. In some other embodiments of the present invention, a FinFET includes a substrate, a fin, a pair of gate electrodes, a gain insulating layer, a common drain region in the fin, and a pair of source regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. Each of the gate electrodes cover sides and a top of adjacent portions of the fin. The gate insulating layer is between the pair of gate electrodes and the fin. The common drain region in the fin is between the pair of gate electrodes. Each of the source regions is adjacent to a side of a different one of the pair of gate electrodes and opposite to the common drain region. The source regions of the fin have a different width than the common drain region of the fin. In some further embodiments of the present invention, the source regions of the fin have a smaller width than the common drain region of the fin. A portion of the fin under each of the pair of gate electrodes can have an abrupt change in width. The fin can taper off in width from the common drain region to the source regions. In some other embodiments of the present invention, a FinFET includes a substrate, a fin, a pair of gate electrodes, a gain insulating layer, a common drain region in the fin, a pair of source regions in the fin, and a channel region in the fin. The fin is on and extends laterally along and vertically away from the substrate. Each of the gate electrodes cover sides and a top of adjacent portions of the fin. The gate insulating layer is between the pair of gate electrodes and the fin. The common drain region in the fin is between the pair of gate electrodes. Each of the source regions is adjacent to a side of a different one of the pair of gate electrodes and opposite to the common drain region. The channel region in the fin is between the common drain region and the source regions. The channel region adjacent to the common drain region has a higher impurity concentration than the channel region adjacent to the source regions. In some further embodiments of the present invention, the source regions of the fin have a smaller width than the common drain region of the fin. A portion of the fin under each of the pair of gate electrodes can have an abrupt change in width. The fin can taper off in width from the common drain region to the source regions. The channel region that is adjacent to the source region can have about the same impurity concentration as the substrate, and the channel region that is adjacent to the common drain region can have a higher impurity concentration than the substrate. In some other embodiments of the present invention, a method for fabricating FinFET includes providing a substrate. A fin is formed on the substrate and extends laterally along and vertically away from the substrate. A first region of the fin has a first fin width and a second region of the fin has a second fin width, where the second fin width is larger than the first fin width. A gate insulation layer is formed on a portion of the fin. A gate electrode is formed on the gate insulating layer and covers sides and a top portion of the fin. In some further embodiments of the present invention, formation of the fin includes patterning the substrate to form the fin with the second fin width therefrom. A mask pattern is formed on the fin. A sidewall of the fin is oxidized to form a sacrificial oxide layer while using the mask pattern as an oxidation barrier layer. The sacrificial oxide layer is removed to form the first region of the fin having the first fin width. The mask pattern is removed to expose the second region of the fin having the second fin width. In yet some further embodiments of the present invention, providing the substrate includes providing a support substrate and patterning the semiconductor substrate to form the fin therefrom. A buried insulating layer is formed on the support substrate. A semiconductor layer is formed on the buried insulating layer. In yet some further embodiments of the present invention, the substrate comprises a semiconductor substrate. The semiconductor substrate is patterned to form the fin therefrom. A device isolation layer is formed on the semiconductor substrate and the fin. In yet some further embodiments of the present invention, formation of the device isolation layer includes forming a liner layer on the semiconductor substrate and the fin, forming an insulation layer on the liner layer, recessing a portion of the insulation layer to expose the liner layer, and recessing the liner layer to partially expose sidewalls of the fin. In some other embodiments of the present invention, a method for fabricating a FinFET includes providing a substrate. A fin is formed on the substrate and extends laterally along and vertically away from the substrate. A first region of the fin has a first fin width and a second region of the fin has a second fin width, where the second fin width is larger than the first fin width. A gate insulation layer is formed on a portion of the fin. A gate electrode is formed on the gate insulating layer and covers sides and a top portion of the fin. Impurities of a first conduction type are implanted into one side of the gate electrode. Impurities of a second conduction type are implanted into the fin using the gate electrode as an ion implanting mask, and to form a source region in the first region, to form a drain region in the second region, and to form a first diffusion layer in a channel region adjacent to the drain region. The source and drain regions define the channel region. In some further embodiments of the present invention, the impurities of the second conduction type are implanted into the fin with a shorter lateral diffusion distance than a lateral diffusion distance of the first conduction-type impurities.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a conventional vertical double gate transistor. FIG. 2 is a perspective view of a FinFET according to a first embodiment of the present invention. FIG. 3 is a graph that illustrates an exemplary threshold voltage of the FinFET shown in FIG. 2. FIG. 4 is a top plan view of a portion of a DRAM cell array with the FinFETs of FIG. 2 in accordance with some embodiments of the present invention. FIGS. 5, 6, 7A, 8A, and 9A are top plan views that illustrate a method of fabricating a DRAM cell array with the FinFETs of FIG. 2 in accordance with some embodiments of the present invention. FIGS. 7B, 7C, 7D, 8B, and 9B are cross-sectional views that illustrate a method of fabricating the DRAM cell with the FinFETs of FIG. 2 in accordance with some embodiments of the present invention. FIGS. 10A and 10B are top plan views of alternate embodiments of the FinFET of FIG. 2 in accordance with some other embodiments of the present invention. FIG. 11 is a top plan view of a FinFET according to a second embodiment of the present invention. FIGS. 12A and 12B are graphs that illustrate doping concentrations and an energy band that vary along a line II-II′ in FIG. 11. FIGS. 13A and 13B are graphs that illustrate energy band shapes during operation of the FinFET of FIG. 11 in accordance with some other embodiments of the present invention. FIGS. 14A and 14B are top plan views of alternate embodiments of the FinFET of FIG. 11 in accordance with some other embodiments of the present invention. FIG. 15 is a perspective view of an alternate embodiment of the FinFET of FIG. 11 in accordance with some other embodiments of the present invention. FIGS. 16A through 16D are diagrams that illustrate methods of fabricating the FinFET of FIG. 15 in accordance with some embodiments of the present invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that there is no intent to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Like reference numbers signify like elements throughout the description of the figures. It will be understood that when an element or layer is referred to as being �on,� �connected to,� or �coupled to� another element or layer, it can be directly on, connected, or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being �directly on,� �directly connected to,� or �directly coupled to� another element or layer, there are no intervening elements or layers present. As used herein, the term �and/or� includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout the description. It will be understood that although the terms first and second are used herein to describe various regions, layers and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section may be termed a first region, layer or section without departing from the teachings of the present invention. Furthermore, relative terms, such as �lower� or �bottom� and �upper� or �top� may be used herein to describe one element's relationship to another elements as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the �lower� side of other elements would then be oriented on �upper� sides of the other elements. The exemplary term �lower� can, therefore, encompass both an orientation of �lower� and �upper,� depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as �below� or �beneath� other elements would then be oriented �above� the other elements. The exemplary terms �below� or �beneath� can, therefore, encompass both an orientation of above and below. Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from an implanted to a non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms �a,� �an,� and �the� are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms �comprises� and/or �comprising,� when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. FIG. 2 is a perspective view of a FinFET in accordance with a first embodiment of the present invention. The FinFET includes a fin 200 that is on a substrate, such as the substrate 12 of FIG. 1, and that extends laterally along the substrate and vertically away from the substrate. Accordingly, fin 200 may be referred to as vertically extending fin 200. The fin 200 includes a first region having a first fin width W1 and a second region having a second fin width W2 that is larger than the first fin width W1. A gate electrode 210 covers sides and a top of a portion of the fin 200. A gate insulation layer 208 is between the gate electrode 210 and the fin 200. A source region 202 s and a drain regions 202 d are formed in the fin 200 adjacent to opposite sides of the gate electrode 210. The source region 202 s is formed in the first region of the fin 200, and the drain region 202 d is formed in the second region 202 s of the fin 200. The gate electrode 210 covers a portion of the fin 200 that includes a boundary region between the first and second regions. The portion of the fin 200 that is covered by the gate electrode 210 corresponds to a channel region of the FinFET. The channel region is between the source region 202 s and the drain regions 202 d. As shown, a portion of the fin 200 under the gate electrode 210 can have an abrupt change in width, and sidewalls of the fin 200 may have a T-shape. Instead of having an abrupt change in width, the fin 200 may taper off from the drain region 202 d to the source region 202 s. FIG. 3 is a graph of an exemplary threshold voltage of the FinFET of FIG. 2 in accordance with some embodiments of the present invention. In the graph, a transversal axis denotes a fin width and a longitudinal axis denotes a threshold voltage. As illustrated in this figure, as the fin width decreases below a determined width, the threshold voltage rapidly decreases. For example, when the fin width is W1, a threshold voltage Vth1 is located where the rate of change (ΔVth/ΔW) is high, and where a small change in the fin width can significantly change the threshold voltage. When the fin width is W2, a threshold voltage Vth2 is located where the rate of change is low, and where a relatively larger change in fin width, such as due to fabrication process variations, does not cause a significant change in the threshold voltage. Accordingly, it can be preferable for a FinFET to have a fin width that is of sufficient width such that small changes in the width do not cause significant changes in the threshold voltage. A FinFET in accordance with some embodiments of the present invention has two different fin widths, and can include a larger fin width region and a smaller fin width region. A source region can be formed in the small fin width region, which may lower source junction leakage current and suppress occurrences of soft error. Accordingly, the threshold voltage may be made less sensitive to fabrication process variations without increasing the fin width. The FinFET may be used in DRAM devices because the source junction leakage current can be low and the generation of soft errors can be suppressed. A FinFET can operate when the gate overlapped fin inside is fully depleted. As a result, the FinFET can have a much higher current driving efficiency than a typical planar transistor. When the fin that is adjacent to a source is wide and the fin that is adjacent to a drain is narrow, the driven current may be effectively increased with little or no increase in drain current. FIG. 4 is a top plan view showing a portion of a DRAM cell array with the FinFET shown in FIG. 2 in accordance with some embodiments of the present invention. Referring to FIG. 4, a DRAM cell array includes a plurality of fins 112 that are formed on a substrate. The substrate may be a SOI substrate or a bulk semiconductor substrate. If the substrate is a SOI substrate, the fins are disposed on an insulation layer. If the substrate is a bulk semiconductor substrate, the fins may be formed by etching the bulk semiconductor substrate. The fin 122 includes a first region 112 a having a first fin width and a second region 112 b having a second fin width. The first region 112 a is adjacent to opposite sides of the fin, and the second region 112 b is between the first regions 112 a. A pair of gate electrodes 10 p cross over the respective fins 112, so that each of the gate electrodes 10 p cover sides and a top of adjacent portions of the fins 112. Each gate electrode 110 overlaps an upper part of a boundary region of the first region 112 a and the second region 112 b. Source region 112 s are formed in the fins 112 and are adjacent to a side of a different one of the pair of gate electrodes 110 and opposite to a common drain region 112 d. The common drain region 112 d is formed in the fin 112 between the gate electrodes 110. Although not shown in this figure, a capacitor is connected to the source region 112 s and a bitline is connected to the common drain region 112 d. A channel region can be defined in each of the fins 112 between the source region and the source regions 112 s and the common drain regions 112 d. The channel region can include two channel portions having different threshold voltages. The source region 112 s can be formed in the smaller width region of the fins 112, and the drain regions 112 d can be formed in the larger width region of the fins 112, which may lower source junction leakage current and suppress the generation of soft errors. Because, the fin width is larger along a portion of a gate electrode 110, a threshold voltage of the FinFETs may be increased which may enhance its controllability and avoid lowering of the drain current. The FinFETs of FIGS. 2 and 4 may be formed on a SOI substrate or a bulk silicon substrate, and may be formed using a conventional gate process or a damascene gate process, but modified as described herein in accordance with some embodiments of the present invention. FIGS. 5, 6, 7A, 8A, and 9A illustrate methods of fabricating a DRAM cell array in accordance with the first embodiment of the present invention. FIGS. 7B, 7C, 7D, 8B, and 9B are cross-sectional views that illustrate a method of fabricating the DRAM cell with the FinFETs of FIG. 2 in accordance with some embodiments of the present invention. Referring to FIG. 5, a substrate is provided, and a plurality of fins 52 are formed on the substrate. The fins 52 are formed on the substrate and extend laterally along and vertically away from the substrate. The substrate may be a SOI substrate or a semiconductor bulk substrate. In case of a SOI substrate, the fins 52 are formed on an insulation layer. In case of a semiconductor bulk substrate, the fins 52 can be on and extend away from the substrate. A semiconductor layer of the SOI substrate or the semiconductor bulk substrate may be formed from silicon, germanium, silicon germanium, germanium silicon germanium and/or combinations thereof. Referring to FIG. 6, a mask pattern 53 is formed on the substrate and crossing over center portions of the fins 52. Using the mask pattern 53 as an oxidation barrier layer, the fin 52 is thermally oxidized to form a sacrificial oxide layer 54 on sidewalls of the fins 52. Through the thermal oxidation, a layer of the exposed portion of the fins 52 is removed so that the width of the exposed portions of the fins 52 is reduced. Thus, a thermal oxidation layer is formed on first regions 52 a on both sides of the fins 52, and is not formed on a second region 52 b between the first regions 52 a. The first region 52 a has a first fin width, and the second region 52 b has a second fin width that is greater than the first fin width (i.e., the second fin width is the initial fin width of the fins 52). Referring to FIG. 7A, the mask pattern 53 and the sacrificial oxide layer 54 are removed to form a first region 52 a at both sides of the fins 52 and to expose the second region 52 b between the first regions 52 a. The first region 52 a has a first fin width, and the second region 52 b has a second fin width which larger than the first fin width. FIG. 7B illustrates a cross-sectional view of fins 52 formed on an SOI substrate. The vertically extending fins 52 are on a buried insulation layer 51, and on a support substrate 50. In FIG. 7B, the fins 52 are formed on a bulk substrate and extend vertically away from the substrate. When the fins 52 are formed on an SOI substrate, the fins 52 are formed on an insulation layer 51 that is isolated from the substrate. When the fins 52 are formed over a bulk substrate, the fins 52 are interconnected to the substrate. Thus, when a FinFET is formed using a bulk substrate, a device isolation layer 55 is formed between the fins 52 to isolate the fins 52 from one another, as illustrated in FIG. 7D. Although not shown in the figures, a conventional gate process or a damascene gate process may be applied to form a gate electrode on and crossing over the fins 52. Some other methods for isolating fins that are formed on a bulk substrate will now be described hereinafter. Referring to FIGS. 8A and 8B, after the first and second regions of the fins 52, a liner layer 56 is conformally formed on the surface of the substrate and the fins 52. The liner layer 56 may include a material having an etch selectivity with respect to the fins 52. For example, the liner layer 56 may include silicon nitride. An insulation layer 58 is formed on the liner 56. The insulation layer 58 may include a material having an etch selectivity with respect to the liner 56 and the substrate, may have good gap-filling efficiency. For example, the insulating layer 58 may include PECVD, HDPCVD, and/or P3-TEOS. Referring to FIGS. 9A and 9B, the insulation layer 58 is recessed to expose the liner layer 56. The exposed liner layer 56 is recessed to expose at least a portion of the sidewalls of the fins 52. A device isolation layer, which includes the recessed insulation layer 58 and the liner layer 56, is formed on a region between the fins 52 to isolate the respective fins 52. Impurities can be implanted into the fins 52 to form a channel diffusion layer. The implantation of the impurities may be carried out using oblique ion implantation. The channel diffusion layer may be formed by implanting boron or boron fluoride at a dose of 1011 atoms/cm2 to about 1014 atoms/cm2 and at a concentration of 1015 atoms/cm3 to about 1019 atoms/cm3. Impurities may be further implanted vertically into a bottom of an exposed portion of the fins 52 according to a projection range (Rp). As a result, the impurities diffused from the channel diffusion layer may overlap the vertically implanted impurities to form an anti-punch-through diffusion layer of a high concentration. The anti-punch-through diffusion layer inhibits punch-through from occurring through a bottom of a channel diffusion layer which is not readily controlled by a gate. The channel diffusion layer and the anti-punch-through diffusion layer may be formed after formation of the fins shown in FIG. 5, or in the step of FIG. 7D in which a sidewall of the fins is partially recessed and a device isolation layer is formed. When the fins 52 are formed on a SOI substrate, formation of an anti-punchthrough diffusion layer is not needed because an underlying insulation layer can prevent punch-through. Referring to FIGS. 9A and 9B, a gate insulation layer 59 is formed on the exposed sidewall of the fin 52. The gate insulation layer 59 may be made from metal oxide, silicon oxide and/or silicon oxynitride, and may be formed by thermal oxidation or chemical vapor deposition (CVD). A conductive layer is formed on the substrate and the gate insulation layer 59. The conductive layer is patterned to form a gate electrode 60 crossing over the fin 52. As illustrated, because a device isolation layer is disposed between the fins, a width of the gap area is smaller than that of the gap area shown in FIG. 7D. The conductive layer may have a planar top surface. The gate electrode 60 may be formed using a damascene process. More particularly, formation of the gate electrode 60 may include forming a mold layer to cover an entire surface, patterning the mold layer to form an opening exposing the fin 52, forming a gate insulation layer on a surface of the exposed fin 52, and filling the opening with a conductive layer to form the gate electrode 60. The gate electrode 60 overlaps an upper portion of a boundary region of the first and second regions 52 b of the fin 52. Using the gate electrode 60 as an ion implanting mask, impurities are implanted into the fin 52 to form a source region 62 s and a drain region 62 d. FIGS. 10A and 10B are top plan views of alternate embodiments of the FinFET of FIG. 2 in accordance with some other embodiments of the present invention. Referring to FIGS. 10A and 10B, although a width of the gate electrode 110 is constant, the threshold voltage may be controlled by the overlap between the gate electrode 110 and the fin 112. When the gate electrode 110 overlaps more of the first region 112 a than the second region 112 b of the fin 112, the threshold voltage of the transistor decreases. In contrast, when the gate electrode 110 overlaps more of the second region 112 b than the first region 112 a, the threshold voltage of the transistor increases. FIG. 11 is a top plan view of a FinFET according to a second embodiment of the present invention. Similar to the first embodiment of FIG. 2, the FinFET illustrated in FIG. 11 has a vertically extending fin 202. The fin 202 includes a first region having a first fin width and a second region having a second fin width which is larger than the first fin width. A gate electrode 210 crosses over and covers a portion of the fin 202. A gate insulation layer 208 is between the gate electrode 210 and the fin 202. A source region 202 s and a drain region 202 d are formed in the fin 202 and adjacent to opposite sides of the gate electrode 210. The source region 202 s is formed in a first region having a relatively smaller width, and the drain region 202 d is formed in a second region having a relatively larger width. A channel region 201 of the transistor is defined in a portion of the fin 202 that is covered by the gate electrode 210, and is between the source region 202 s and the drain region 202 d. Therefore, the channel region 201 is also disposed through the first and second regions. An impurity diffusion layer 204 of a higher doping concentration than the other channel regions 201 is formed in a channel region adjacent to the drain region 202 d. A conduction type of the impurity diffusion layer 204 is different from that of the source region 202 s and the drain region 202 d. FIGS. 12A and 12B are graphs that illustrate doping concentrations and an energy band that vary along a line II-II′ in FIG. 11. In these figures, a region (1) denotes a source region, a region (2) denotes a channel region, a region (3) is a channel region adjacent to a drain region, and a region (4) denotes a drain region. A doping concentration of the source region (1) and the drain region (4) is higher than a doping concentration of the channel region (2), such as illustrated in these figures. When the FinFET is used in a DRAM cell transistor, the channel region (2) may have a typical p-type well concentration or p-type substrate concentration. P-type impurities such as boron or boron fluoride are additionally implanted into the p-type well or p-type substrate to more heavily dope the channel region (3) adjacent to the drain region. The source region (1) and the drain region (4) are doped with n-type impurities such as phosphorus (P) or arsenic (As). As illustrated in FIG. 12B, an impurity concentration of the channel region (3) adjacent to the drain region is higher than that of the channel region (2) adjacent to the source region. For this reason, a potential barrier Φd is formed between a channel region and a drain region to offer a very advantageous characteristic to the FinFET according to the present invention. FIG. 13A and FIG. 13B are graphs that illustrate energy band shapes during operation of the FinFET of FIG. 11 in accordance with some other embodiments of the present invention. FIG. 13A illustrates the state that charges are stored in a storage capacitor of a memory cell in which the storage capacitor is connected to the source region 202 s and a bitline is connected to the drain region 202 d. The impurity diffusion layer 204 produces a potential barrier Φd in a channel region (3) adjacent to the drain region 202 d. Thus, while the transistor is turned off, the potential barrier Φd prevents electrons from flowing from the drain region (4) to reduce a transistor off leakage. FIG. 13B illustrates a turn-on state of a transistor in which Vcc is applied to the drain region 202 d through the bitline of a memory cell. Since the potential barrier Φd is disposed around a drain region of a high voltage level while a transistor is turned on, a peak of Φd is at a level which is Φd lower than a channel of the source side. Accordingly, there is a rare influence on the flow of electrons from the source region (1) to the drain region (4). Thus, the transistor has a low threshold voltage depending on a channel region (2) adjacent to the source region. As previously explained, the FinFET according to the second embodiment of the present invention may have a high threshold voltage while being turned off, so that the off leakage is low. The FinFET may also have a low threshold voltage while being turned on, so that a transistor on current is low. Because a doping concentration of the channel region that is adjacent to the source region is low, a junction leakage between a source region and a channel may be suppressed. As shown in FIG. 11, the boundary region of the first region and the second region is covered by the gate electrode 210. In accordance with some embodiments of the present invention, the FinFET may include a fin that tapers off from a drain region 302 d to a source region 302 s (see FIG. 14A), or it may have a fin that has a larger width as it extends toward the drain region 312 d than as it extends toward the source region 212 s (e.g., FIG. 14B). FIG. 15 is a perspective view of an alternate embodiment of the FinFET of FIG. 11 in accordance with some other embodiments of the present invention. Referring to FIG. 15, a fin 300 tapers down from a drain region 302 d to a source region 302 s. Accordingly, in contrast to the fin 200 of FIG. 11 that has an abrupt change in width, with an associated T-shape sides, in the channel region 201, the fin 300 shown in FIG. 15 does not have an abrupt change in width in a channel region 301. As illustrated in this figure, the fin 300 is on and extends away from a substrate. A gate electrode 310 crosses over the fin 300 and is on sidewalls and a top surface of a portion of the fin 300. A gate insulation layer 308 is between the gate electrode 310 and the fin 300. The source region 302 s and the drain region 302 d are formed in the fin 300 and are adjacent to opposite sides of the gate electrode 310. The fin 300 becomes increasingly wider from the source region 302 s to the drain region 302 d. Because the cross-sectional area of the fin 300 in the source region 302 s is small, the junction leakage is decreased. Because the area of the fin 300 in the drain region 302 d increases, the transistor on current increases. The channel region 301 is defined in the fin 300 in a portion that is covered by the gate electrode 310 and between the source region 302 s and the drain region 302 d. An impurity concentration of a portion of the channel region 301 that is adjacent to the drain region 302 d is higher than a portion of the channel region 301 that is adjacent to the source region 302 s. Accordingly, the impurity concentration of the channel region 301 can be lowered to increase the on current of the transistor, while a high-concentration diffusion layer 304 that is adjacent to the drain region 302 d can inhibit electrons from flowing from the drain region 302 d to the source region 302 s. Consequently, the channel region 301 may be maintained at the initial impurity concentration of the substrate without forming a channel diffusion layer. FIG. 16A through FIG. 16D are diagrams that illustrate methods of fabricating the FinFET of FIG. 15 in accordance with some embodiments of the present invention. Referring to FIG. 16A, a vertically extending fin 300 is formed on a semiconductor substrate. As was described above, the fin 300 may be defined using a device isolation layer and etching a semiconductor bulk substrate, and/or it may be formed on a buried oxide layer and isolated by patterning a silicon layer of a SOI substrate. The fin 300 can taper off in width from one end to another, such as shown in FIG. 15, or it may have an abrupt change in width, such as shown in FIG. 11. Alternatively, the fin 300 may have an asymmetry taper shape (see FIG. 14A) or it may have a central region that is narrower than end portions of the fin 300 (see FIG. 14B). Referring to FIG. 16D, a gate insulation layer 308 is formed on the fin 300. A gate electrode 310 is formed on the fin and covering sidewalls and a top surface of a portion of the fin 300. A thick insulation layer may be formed on the top surface of the fin 300 between the gate electrode 310 and the top surface of the fin 300. When the gate electrode 310 is on sidewalls and a top surface of the fin 300, a channel may be formed through three faces of the fin 300. When a thick insulation layer is between the gate electrode 310 and a top surface of the fin 300, a channel may be formed in a portion of the fin 300 that is under the gate electrode 310. Referring to FIG. 16C, impurities of a first conduction type are implanted into the fin 300 using the gate electrode 310 as a mask, and forming a diffusion layer 303 of the first conduction type. The impurities of the first conduction type are implanted into a wider portion of a fin 300, i.e., a portion where a drain of the transistor is to be formed (which will be used as a bitline-connected area in a DRAM cell array). The impurities of the first conduction type have the same conduction type as initial impurities of the fin 300. For example, in a DRAM device that uses NMOS transistors and a p-type substrate or a p-type well, the impurities of the first conduction type may be p-type impurities such as boron or boron fluoride. The diffusion layer 303 of the first conduction type may be laterally diffused to a lower portion of the gate electrode 310. Referring to FIG. 16D, using the gate electrode 310 as an ion implanting mask, impurities of a second conduction type are implanted into the fin 300 to form a source region 302 s and a drain region 302 d in the fin 300 on opposite sides of the gate electrode 310. The source region 302 s is in a narrow portion of the fin 300, and the drain region 302 d is in a wider portion of the fin 300. The impurities of the second conduction type may be phosphorus or arsenic. The impurities of the second conduction type form the drain region 302 d by inverting the first conduction type of the diffusion layer 303. The lateral diffusion distance of the first conduction type impurities can be longer than that of the second conduction type impurities. The diffusion layer 304 of the first conduction type may be in the fin 300 adjacent to the drain region 302 d. The channel region 301 is defined by the source region 302 s and the drain region 302 d. A portion of the fin 300 that is adjacent to the drain region 302 d has a higher impurity concentration than the portion of the fin 300 that is adjacent to the source region 302 s. The operations for forming the first conduction type diffusion layer and the second conduction type diffusion layer can be interchanged. The first conduction type diffusion layer can be subjected to more thermal oxidation than the second conduction type diffusion layer to control the associated diffusion distances. As was explained with reference to FIGS. 9A and 9B, when a plurality of the fins 300 are used in FinFETs in a DRAM device, a device isolation layer can be used to isolate the fins 300. An impurity-implanting dose of the second embodiment can be lower than that of the first embodiment, and a channel diffusion layer may, or may not, be used as was previously explained. An anti-punch-through diffusion layer may be formed on a lower portion of the fin 300. A pair of gate electrodes may be formed on, and crossing over, the fin 300. Impurities of a first conduction type can be implanted into the fin 300 between gate electrodes to form a diffusion layer of the first conduction type. Using the gate electrodes as an ion implanting mask, impurities are implanted into the fin 300 to form a common drain region 302 d in the fin 300 between the gate electrodes 310 and to form a source region 302 s in the fin 300 on opposite sides adjacent to the common drain region 302 d. A bitline can be connected to the common drain region 302 d and a storage capacitor can be connected to the source region 302 s. In concluding the detailed description, it should be noted that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7102181 *Apr 22, 2005Sep 5, 2006International Business Machines CorporationStructure and method for dual-gate FET with SOI substrateUS7312504 *Jul 1, 2005Dec 25, 2007Hynix Semiconductor Inc.Transistor for memory device and method for manufacturing the sameUS7323374 *Sep 19, 2005Jan 29, 2008International Business Machines CorporationDense chevron finFET and method of manufacturing sameUS7906802 *Jan 28, 2009Mar 15, 2011Infineon Technologies AgSemiconductor element and a method for producing the sameUS8048723Dec 5, 2008Nov 1, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Germanium FinFETs having dielectric punch-through stoppersUS8106459May 6, 2008Jan 31, 2012Taiwan Semiconductor Manufacturing Company, Ltd.FinFETs having dielectric punch-through stoppersUS8114723 *Jun 7, 2010Feb 14, 2012International Business Machines CorporationMethod of forming multi-high-density memory devices and architecturesUS8227301 *Dec 9, 2009Jul 24, 2012International Business Machines CorporationSemiconductor device structures with floating body charge storage and methods for forming such semiconductor device structuresUS8263462 *Dec 31, 2008Sep 11, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Dielectric punch-through stoppers for forming FinFETs having dual fin heightsUS8293616Nov 13, 2009Oct 23, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Methods of fabrication of semiconductor devices with low capacitanceUS20100087037 *Dec 9, 2009Apr 8, 2010International Business Machines CorporationSemiconductor device structures with floating body charge storage and methods for forming such semiconductor device structuresUS20120299110 *Jul 31, 2012Nov 29, 2012Taiwan Semiconductor Manufacturing Company, Ltd.Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin HeightsUS20130207079 *Feb 9, 2012Aug 15, 2013International Business Machines CorporationTapered Nanowire Structure With Reduced Off CurrentEP2446466A2 *Jun 2, 2010May 2, 2012International Business Machines CorporationFet with replacement gate structure and method of fabricating the sameWO2007035788A2 *Sep 19, 2006Mar 29, 2007Jochen BeintnerDENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAMEWO2010032174A1 *Sep 10, 2009Mar 25, 2010Nxp B.V.Fin field effect transistor (finfet)* Cited by examinerClassifications U.S. Classification257/327, 257/E21.336, 257/E21.703, 438/157, 257/E29.279International ClassificationH01L21/00, H01L21/20, H01L21/84, H01L31/062, H01L29/786, H01L21/265, H01L29/76, H01L21/336, H01L31/119, H01L29/94, H01L31/113Cooperative ClassificationH01L21/845, H01L29/78624, H01L29/785, H01L21/26513, H01L29/66795European ClassificationH01L21/84F, H01L29/66M6T6F16F, H01L29/786B4B2, H01L29/78SLegal EventsDateCodeEventDescriptionJul 29, 2011FPAYFee paymentYear of fee payment: 4Jun 10, 2008CCCertificate of correctionAug 12, 2005ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, CHUL;KIM, MIN-SANG;PARK, DONG-GUN;AND OTHERS;REEL/FRAME:016635/0678;SIGNING DATES FROM 20050315 TO 20050316RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


text:
As more companies turn to influencers to reach more customers on social media and grow their sales, you need to find ways of getting the most from them.
Also, you need to appreciate the fact that past strategies may not work in 2018.
Therefore, adapting to changes in the current business environment can give you insight on how you can harness the potential of influencer marketing in 2018.
1. Influencer Marketing Trends To Watch In 2018
2. As more companies turn to influencers to reach more customers on social media and grow their sales, you need to find ways of getting the most from them. Also, you need to appreciate the fact that past strategies may not work in 2018. Therefore, adapting to changes in the current business environment can give you insight on how you can harness the potential of influencer marketing in 2018. Here are some of the trends that will promote influencer marketing success this year. Image Credit: Spotify
3. As much as Instagram is the leading platform for influencers, it is wrong to assume that this is where you should draw all your attention. In fact, it is not surprising to discover that some of these experts are not on Instagram. Hence, as you check Pinterest, Facebook, YouTube, Snapchat, and Twitter, you will realize that they are active on these channels as well. The fact that most influencers are on Instagram means that you expect to pay more for their services. On the contrary, those using other channels may have cheaper rates, which can yield your firm a better return on investment. Therefore, in addition to accessing better conversions, you stand a better chance in 2018 by working with influencers who are not on Instagram. Focusing On Other Social Media Channels
4. Using photos of an influencer holding your product as they explain how much they love it is no longer the in thing. These are generics ads that will do little to propel your business forward in 2018. Leveraging Useful Content Photo Credit: New Hope Network Most buyers are looking for content that educates, entertains, and what invokes some emotion. Therefore, you need to shift from such ads to content marketing to achieve your goal. Backing your influencer marketing campaigns with the right content will help you convey the right message to your audience for the achievement of desirable results.
5. In most cases, the relationship between business operators and influencers is purely transactional. The implication is that when such entrepreneurs access the services they require for a particular amount, it marks the end of interactions between the two. Establishing Long-term Relationships Unfortunately, such influencers tend to act as short-term contracted who may not satisfy your expectations. As a result, your audience may not connect to your brand once they capture that from an influencer. The solution, in that case, is seeking to build lasting relationships with your influencer to promote enthusiasm and earn their loyalty to your brand.
6. If you need more information on influencer marketing trends for 2018,contact us today!
7. If you need more information on influencer marketing trends for 2018,contact us today!

type: global

value: This website is an American hosting service, now owned by Scribd, for professional content including presentations, infographics, documents, and videos. Users can upload files privately or publicly in PowerPoint, Word, PDF, or OpenDocument format.


text:
Patent US8011589 - Wireless IC device and manufacturing method thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA wireless IC device includes a radiation plate, a wireless IC chip, and a substrate provided with a feed circuit that includes a resonant circuit and/or the matching circuit including an inductance element and that is electromagnetically coupled to the radiation plate. The substrate is made of a resin...http://www.google.com/patents/US8011589?utm_source=gb-gplus-sharePatent US8011589 - Wireless IC device and manufacturing method thereofAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8011589 B2Publication typeGrantApplication numberUS 12/961,599Publication dateSep 6, 2011Filing dateDec 7, 2010Priority dateJun 25, 2008Fee statusPaidAlso published asUS7871008, US20090321527, US20110073664Publication number12961599, 961599, US 8011589 B2, US 8011589B2, US-B2-8011589, US8011589 B2, US8011589B2InventorsNoboru Kato, Yutaka Sasaki, Masahiro OzawaOriginal AssigneeMurata Manufacturing Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (368), Non-Patent Citations (93), Referenced by (6), Classifications (37), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetWireless IC device and manufacturing method thereof
US 8011589 B2Abstract
For example, the recess 21 is made preferably by pressing a convex mold having a protrusion corresponding to the size and shape of the recess 21 against the upper surface 22 a of the resin sheet substrate 22. The substrate 22 may be heated as necessary and a recess may be formed by pressing the softened substrate 22. For example, a resin sheet is disposed on a hot plate and heated to about 300° C. and a recess is formed on the resin sheet using a mold.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3364564Jun 28, 1965Jan 23, 1968Gregory Ind IncMethod of producing welding studs dischargeable in end-to-end relationshipUS4794397Oct 11, 1985Dec 27, 1988Toyota Jidosha Kabushiki KaishaAutomobile antennaUS5232765Jul 22, 1991Aug 3, 1993Ngk Insulators, Ltd.Distributed constant circuit board using ceramic substrate materialUS5253969May 11, 1992Oct 19, 1993Sms Schloemann-Siemag AktiengesellschaftFeeding system for strip material, particularly in treatment plants for metal stripsUS5337063Apr 13, 1992Aug 9, 1994Mitsubishi Denki Kabushiki KaishaAntenna circuit for non-contact IC card and method of manufacturing the sameUS5374937Jan 28, 1994Dec 20, 1994Nippon Telegraph And Telephone CorporationRetractable antenna systemUS5399060Jun 25, 1993Mar 21, 1995Sms Schloemann-Siemag AktiengesellschaftFeeding system for strip material, particularly in treatment plants for metal stripUS5491483Jan 5, 1994Feb 13, 1996Texas Instruments IncorporatedSingle loop transponder system and methodUS5528222Sep 9, 1994Jun 18, 1996International Business Machines CorporationRadio frequency circuit and memory in thin flexible packageUS5757074Jul 29, 1996May 26, 1998Hughes Electronics CorporationMicrowave/millimeter wave circuit structure with discrete flip-chip mounted elementsUS5854480Jul 11, 1996Dec 29, 1998Oki Electric Indusry Co., Ltd.Tag with IC capacitively coupled to antennaUS5903239May 26, 1995May 11, 1999Matsushita Electric Industrial Co., Ltd.Micro-patch antenna connected to circuits chipsUS5936150Apr 13, 1998Aug 10, 1999Rockwell Science Center, LlcThin film resonant chemical sensor with resonant acoustic isolatorUS5955723Nov 3, 1997Sep 21, 1999Siemens AktiengesellschaftContactless chip cardUS5995006Jan 15, 1996Nov 30, 1999Intermec Ip Corp.Radio frequency tagUS6104311Aug 26, 1996Aug 15, 2000Addison TechnologiesInformation storage and identification tagUS6107920Jun 9, 1998Aug 22, 2000Motorola, Inc.Radio frequency identification tag having an article integrated antennaUS6172608Jun 18, 1997Jan 9, 2001Integrated Silicon Design Pty. Ltd.Enhanced range transponder systemUS6181287Mar 3, 1998Jan 30, 2001Precision Dynamics CorporationReactively coupled elements in circuits on flexible substratesUS6190942Sep 22, 1997Feb 20, 2001Pav Card GmbhMethod and connection arrangement for producing a smart cardUS6249258Sep 11, 1996Jun 19, 2001Aeg IdentifikationssystemeTransponder arrangementUS6259369Sep 30, 1999Jul 10, 2001Moore North America, Inc.Low cost long distance RFID readingUS6271803Jun 30, 1999Aug 7, 2001Murata Manufacturing Co., Ltd.Chip antenna and radio equipment including the sameUS6335686Aug 5, 1999Jan 1, 20023M Innovative Properties CompanyApplication for a radio frequency identification systemUS6362784Dec 10, 1998Mar 26, 2002Matsuda Electric Industrial Co., Ltd.Antenna unit and digital television receiverUS6367143Mar 5, 1999Apr 9, 2002Smart Card Technologies Co. Ltd.Coil element and method for manufacturing thereofUS6378774May 11, 2000Apr 30, 2002Toppan Printing Co., Ltd.IC module and smart cardUS6406990Nov 21, 2000Jun 18, 2002Omron CorporationMethod of mounting a semiconductor chip, circuit board for flip-chip connection and method of manufacturing the same, electromagnetic wave readable data carrier and method of manufacturing the same, and electronic component module for an electromagnetic wave readable data carrierUS6448874Feb 7, 2000Sep 10, 2002Alps Electric Co., Ltd.Resonant line constructed by microstrip line which is easy to be trimmedUS6462716Aug 2, 2001Oct 8, 2002Murata Manufacturing Co., Ltd.Antenna device and radio equipment having the sameUS6542050Mar 20, 2000Apr 1, 2003Ngk Insulators, Ltd.Transmitter-receiverUS6600459Oct 26, 2001Jul 29, 2003Mitsubishi Materials CorporationAntennaUS6634564Oct 23, 2001Oct 21, 2003Dai Nippon Printing Co., Ltd.Contact/noncontact type data carrier moduleUS6664645Apr 16, 2002Dec 16, 2003Omron CorporationMethod of mounting a semiconductor chip, circuit board for flip-chip connection and method of manufacturing the same, electromagnetic wave readable data carrier and method of manufacturing the same, and electronic component module for an electromagnetic wave readable data carrierUS6763254Apr 27, 2001Jul 13, 2004Matsushita Electric Industrial Co., Ltd.Portable information terminal having wireless communication deviceUS6812707May 19, 2003Nov 2, 2004Mitsubishi Materials CorporationDetection element for objects and detection device using the sameUS6828881Jun 27, 2002Dec 7, 2004Ngk Insulators, Ltd.Stacked dielectric filterUS6837438Oct 29, 1999Jan 4, 2005Hitachi Maxell, Ltd.Non-contact information medium and communication system utilizing the sameUS6861731Feb 27, 2002Mar 1, 2005Koninklijke Philips Electronics N.V.Module and electronic deviceUS6927738Jan 10, 2002Aug 9, 2005Hanex Co., Ltd.Apparatus and method for a communication deviceUS6963729May 30, 2001Nov 8, 2005Mitsubishi Materials CorporationAntenna device of interrogatorUS7088249Jul 13, 2001Aug 8, 2006Hanex Co., Ltd.Housing structure for RFID tag, installation structure for RFID tag, and communication using such RFID tagUS7088307Apr 23, 2004Aug 8, 2006Taiyo Yuden Co., Ltd.Antenna matching circuit, mobile communication device including antenna matching circuit, and dielectric antenna including antenna matching circuitUS7112952Jan 27, 2005Sep 26, 2006Semiconductor Energy Laboratory Co., Ltd.Inspection system, inspection method, and method for manufacturing semiconductor deviceUS7119693Mar 13, 2002Oct 10, 2006Celis Semiconductor Corp.Integrated circuit with enhanced couplingUS7129834Mar 27, 2003Oct 31, 2006Kabushiki Kaisha ToshibaString wireless sensor and its manufacturing methodUS7248221Nov 30, 2004Jul 24, 2007Fujitsu LimitedRadio tag antenna structure for an optical recording medium and a case for an optical recording medium with a radio tag antennaUS7250910Jan 30, 2004Jul 31, 2007Matsushita Electric Industrial Co., Ltd.Antenna apparatus utilizing minute loop antenna and radio communication apparatus using the same antenna apparatusUS7276929Sep 22, 2006Oct 2, 2007Semiconductor Energy Laboratory Co., Ltd.Inspection system, inspection method, and method for manufacturing semiconductor deviceUS7317396May 26, 2005Jan 8, 2008Funai Electric Co., Ltd.Optical disc having RFID tag, optical disc apparatus, and system for preventing unauthorized copyingUS7405664Feb 9, 2005Jul 29, 2008Hitachi, Ltd.Radio frequency IC tag and method for manufacturing the sameUS20020011967Jul 19, 2001Jan 31, 20023M Innovative Properties CompanyApplication for a radio frequency identification systemUS20020015002Jun 21, 2001Feb 7, 2002Hidenori YasukawaAntenna coil for IC card and manufacturing method thereofUS20020044092Aug 2, 2001Apr 18, 2002Yuichi KushihiAntenna device and radio equipment having the sameUS20020067316Oct 26, 2001Jun 6, 2002Mitsubishi Materials CorporationAntennaUS20020093457Jan 9, 2002Jul 18, 2002Hiroki HamadaAntenna deviceUS20030006901Jun 1, 2001Jan 9, 2003Ji-Tae KimPassive transponder identification and credit-card type transponderUS20030020661Jul 26, 2002Jan 30, 2003Tdk CorporationAntenna device capable of being commonly used at a plurality of frequencies and electronic equipment having the sameUS20030045324Aug 26, 2002Mar 6, 2003Murata Manufacturing Co., Ltd.Wireless communication apparatusUS20030169153Feb 7, 2001Sep 11, 2003Philipp MullerRfid-label with an element for regulating the resonance frequencyUS20040001027Jun 27, 2002Jan 1, 2004Killen William D.Dipole arrangements using dielectric substrates of meta-materialsUS20040026519Jun 27, 2003Feb 12, 2004Mitsuo UsamiSemiconductor devices and manufacturing method therefor and electronic commerce method and transponder readerUS20040056823Sep 18, 2003Mar 25, 2004Zuk Philip C.RFID tag wide bandwidth logarithmic spiral antenna method and systemUS20040066617Dec 4, 2002Apr 8, 2004Takayuki HirabayashiCircuit board device and its manufacturing methodUS20040217915Apr 23, 2004Nov 4, 2004Tatsuya ImaizumiAntenna matching circuit, mobile communication device including antenna matching circuit, and dielectric antenna including antenna matching circuitUS20040219956Feb 5, 2004Nov 4, 2004Hiroshi IwaiPortable radio communication apparatus provided with a boom portion and a part of housing operating as an antennaUS20040227673Feb 5, 2004Nov 18, 2004Hiroshi IwaiPortable radio communication apparatus provided with a part of housing operating as an antennaUS20040252064Jun 2, 2004Dec 16, 2004Alps Electric Co., Ltd.Small-sized and high-gained antenna-integrated moduleUS20050092836Oct 29, 2004May 5, 2005Kazuhiro KudoLoop coilantennaUS20050099337Jul 30, 2004May 12, 2005Hitachi, Ltd.Antenna, method for manufacturing the antenna, and communication apparatus including the antennaUS20050125093Sep 21, 2004Jun 9, 2005Sony CorporationRelaying apparatus and communication systemUS20050134460Dec 3, 2004Jun 23, 2005Mitsuo UsamiAntenna for radio frequency identificationUS20050134506Dec 23, 2003Jun 23, 20053M Innovative Properties CompanyUltra high frequency radio frequency identification tagUS20050138798Jul 30, 2004Jun 30, 2005Isao SakamaRadio IC tag, method for manufacturing radio IC tag, and apparatus for manufacturing radio IC tagUS20050140512Dec 23, 2004Jun 30, 2005Isao SakamaWireless IC tag, and method and apparatus for manufacturing the sameUS20050232412Apr 14, 2005Oct 20, 2005Matsushita Electric Industrial Co., Ltd.Line state detecting apparatus and transmitting apparatus and receiving apparatus of balanced transmission systemUS20050236623Apr 22, 2005Oct 27, 2005Nec CorporationSemiconductor deviceUS20050275539Feb 9, 2005Dec 15, 2005Isao SakamaRadio frequency IC tag and method for manufacturing the sameUS20060001138Feb 18, 2005Jan 5, 2006Hitachi, Ltd.IC-tag-bearing wiring board and method of fabricating the sameUS20060044192Oct 25, 2005Mar 2, 20063M Innovative Properties CompanyUltra high frequency radio frequency identification tagUS20060055601Jul 3, 2003Mar 16, 2006Shozaburo KamedaAntenna with built-in filterUS20060071084Dec 14, 2001Apr 6, 2006Electrox CorporationProcess for manufacture of novel, inexpensive radio frequency identification devicesUS20060109185Dec 30, 2005May 25, 2006Hiroshi IwaiPortable radio communication apparatus provided with a part of a housing operating as an antennaUS20060145872Dec 15, 2005Jul 6, 2006Denso CorporationIC tag and IC tag attachment structureUS20060158380Dec 7, 2005Jul 20, 2006Hae-Won SonAntenna using inductively coupled feeding method, RFID tag using the same and antenna impedence matching method thereofUS20060170606Jun 21, 2005Aug 3, 2006Fujitsu LimitedMeander line antennaUS20060214801Mar 7, 2006Sep 28, 2006Nobuo MurofushiRadio frequency tag and method for regulating the sameUS20060220871Sep 22, 2005Oct 5, 2006Fujitsu LimitedRFID tagUS20060244676Apr 28, 2006Nov 2, 2006Kouichi UesakaSignal processing circuit, and non-contact IC card and tag with the use thereofUS20060267138May 22, 2006Nov 30, 2006Semiconductor Energy Laboratory Co., Ltd.Semiconductor deviceUS20070004028Mar 10, 2006Jan 4, 2007Gen-Probe IncorporatedSignal measuring system for conducting real-time amplification assaysUS20070018893Sep 28, 2006Jan 25, 2007Manabu KaiRadio tag antenna structure for an optical recording medium and a case for an optical recording medium with a radio tag antennaUS20070040028Nov 29, 2005Feb 22, 2007Fujitsu LimitedRFID tagUS20070052613Sep 23, 2005Mar 8, 2007Sebastian GallschuetzRadio frequency identification transponder antennaUS20070057854Aug 8, 2006Mar 15, 2007Kabushiki Kaisha ToshibaMobile transceiver and antenna deviceUS20070069037Aug 10, 2006Mar 29, 2007Wakahiro KawaiAntenna unit and noncontact IC tagUS20070132591Dec 8, 2005Jun 14, 2007Ncr CorporationRFID deviceUS20070164414Jan 18, 2007Jul 19, 2007Murata Manufacturing Co., Ltd.Wireless ic device and component for wireless ic deviceUS20070200782Oct 27, 2006Aug 30, 2007Kosuke HayamaAntenna and RFID tagUS20070252700May 18, 2005Nov 1, 2007Iwata Label Co., Ltd.Affixing Method of Rfid Label and its Affixing ApparatusUS20070252703Apr 26, 2007Nov 1, 2007Murata Manufacturing Co., Ltd.Electromagnetic-coupling-module-attached articleUS20070285335Dec 24, 2004Dec 13, 2007Mitsubishi Materials CorporationAntenna Device and Communication ApparatusUS20070290928Sep 20, 2006Dec 20, 2007Industrial Technology Research InstituteBroadband antennaUS20080024156Sep 27, 2007Jan 31, 2008Semiconductor Energy Laboratory Co., Ltd.Inspection System, Inspection Method, and Method for Manufacturing Semiconductor DeviceUS20080087990Dec 21, 2005Apr 17, 2008Semiconductor Energy Laboratory Co., LtdSemiconductor DeviceUS20080169905Sep 27, 2005Jul 17, 2008Hewlett-Packard Development Company, L.P.Inductive Coupling in DocumentsUS20080272885Jan 21, 2005Nov 6, 2008Mikoh CorporationModular Radio Frequency Identification Tagging MethodUS20090002130Sep 16, 2008Jan 1, 2009Murata Manufacturing Co., Ltd.Wireless ic deviceUS20090009007Sep 22, 2008Jan 8, 2009Murata Manufacturing Co., Ltd.Product including power supply circuit boardUS20090065594Nov 24, 2008Mar 12, 2009Murata Manufacturing Co., Ltd.Wireless ic device and wireless ic device composite componentUS20090109102Jan 8, 2009Apr 30, 2009Murata Manufacturing Co., Ltd.Antenna and radio ic deviceUS20090160719Dec 17, 2008Jun 25, 2009Murata Manufacturing Co., Ltd.Radio frequency ic deviceUS20090262041Jul 2, 2009Oct 22, 2009Murata Manufacturing Co., Ltd.Wireless ic deviceDE102006057369A1Dec 4, 2006Jun 5, 2008Airbus Deutschland GmbhRadio frequency identification tag for e.g. identifying metal container, has radio frequency identification scanning antenna with conductor loop that is aligned diagonally or perpendicularly to attachment surfaceEP0694874A2Jul 21, 1995Jan 31, 1996Toppan Printing Co. Ltd.Biodegradable cardsEP0977145A2Jul 26, 1999Feb 2, 2000Kabushiki Kaisha ToshibaRadio IC cardEP1010543A1Dec 22, 1997Jun 21, 2000Rohm Co., Ltd.Card mounted with circuit chip and circuit chip moduleEP1160915A2May 30, 2001Dec 5, 2001Mitsubishi Materials CorporationAntenna device of interrogatorEP1170795A2May 31, 2001Jan 9, 2002Murata Manufacturing Co., Ltd.Electronic component with side contacts and associated method of fabricationEP1227540A1Dec 22, 2001Jul 31, 2002Alps Electric Co., Ltd.Partial ground connection of a metal housing for realising certain electrical lenghts for the ground connection of a chip antennaEP1280232A1Jul 26, 2002Jan 29, 2003TDK CorporationAntenna device capable of being commonly used at a plurality of frequencies and electronic equipment having the sameEP1280350A1Jul 26, 2001Jan 29, 2003Irdeto Access B.V.Time validation systemEP1343223A1Apr 23, 2001Sep 10, 2003Samsung Electronics Co., Ltd.AntennaEP1357511A2Apr 23, 2003Oct 29, 2003Smart Card Co., Ltd.IC tag systemEP1548872A1Jul 3, 2003Jun 29, 2005Ube Industries, Ltd.Antenna with built-in filterEP1703589A1Dec 22, 2005Sep 20, 2006Fujitsu Ltd.Tag antennaEP1841005A1Nov 9, 2006Oct 3, 2007Fujitsu Ltd.Plane antennaEP2009738A1Mar 6, 2007Dec 31, 2008Murata Manufacturing Co. Ltd.AntennaEP2148449A1May 9, 2008Jan 27, 2010Murata Manufacturing Co., LtdWireless ic deviceGB2305075A Title not availableJP3075400U Title not availableJP3653099B2 Title not availableJP4069958B2 Title not availableJP6260949A Title not availableJP9512367A Title not availableJP10069533A Title not availableJP10171954A Title not availableJP10193849A Title not availableJP10193851A Title not availableJP10293828A Title not availableJP10505466A Title not availableJP11039441A Title not availableJP11075329A Title not availableJP11085937A Title not availableJP11102424A Title not availableJP11103209A Title not availableJP11149536A Title not availableJP11149537A Title not availableJP11149538A Title not availableJP11175678A Title not availableJP11219420A Title not availableJP11220319A Title not availableJP11328352A Title not availableJP11346114A Title not availableJP11515094A Title not availableJP50143451A Title not availableJP62127140U Title not availableJP2000021639A Title not availableJP2000022421A Title not availableJP2000059260A Title not availableJP2000085283A Title not availableJP2000090207A Title not availableJP2000132643A Title not availableJP2000137778A Title not availableJP2000137779A Title not availableJP2000137785A Title not availableJP2000148948A Title not availableJP2000172812A Title not availableJP2000209013A Title not availableJP2000222540A Title not availableJP2000243797A Title not availableJP2000251049A Title not availableJP2000261230A Title not availableJP2000276569A Title not availableJP2000286634A Title not availableJP2000286760A Title not availableJP2000311226A Title not availableJP2000321984A Title not availableJP2000349680A Title not availableJP2000510271A Title not availableJP2001028036A Title not availableJP2001043340A Title not availableJP2001168628A Title not availableJP2001188890A Title not availableJP2001240046A Title not availableJP2001256457A Title not availableJP2001257292A Title not availableJP2001319380A Title not availableJP2001331976A Title not availableJP2001332923A Title not availableJP2001339226A Title not availableJP2001344574A Title not availableJP2001351084A Title not availableJP2001352176A Title not availableJP2001505682A Title not availableJP2001514777A Title not availableJP2002024776A Title not availableJP2002026513A Title not availableJP2002042076A Title not availableJP2002063557A Title not availableJP2002076750A Title not availableJP2002150245A Title not availableJP2002157564A Title not availableJP2002158529A Title not availableJP2002175508A Title not availableJP2002183690A Title not availableJP2002185358A Title not availableJP2002204117A Title not availableJP2002230128A Title not availableJP2002232221A Title not availableJP2002252117A Title not availableJP2002259934A Title not availableJP2002280821A Title not availableJP2002298109A Title not availableJP2002308437A Title not availableJP2002319008A Title not availableJP2002319009A Title not availableJP2002319812A Title not availableJP2002362613A Title not availableJP2002373029A Title not availableJP2002373323A Title not availableJP2002374139A Title not availableJP2002505645A Title not availableJP2002522849A Title not availableJP2003006599A Title not availableJP2003016412A Title not availableJP2003026177A Title not availableJP2003030612A Title not availableJP2003046318A Title not availableJP2003067711A Title not availableJP2003069335A Title not availableJP2003076947A Title not availableJP2003078336A Title not availableJP2003085501A Title not availableJP2003085520A Title not availableJP2003099720A Title not availableJP2003099721A Title not availableJP2003110344A Title not availableJP2003132330A Title not availableJP2003134007A Title not availableJP2003155062A Title not availableJP2003158414A Title not availableJP2003168760A Title not availableJP2003179565A Title not availableJP2003187207A Title not availableJP2003187211A Title not availableJP2003188338A Title not availableJP2003188620A Title not availableJP2003198230A Title not availableJP2003209421A Title not availableJP2003216919A Title not availableJP2003218624A Title not availableJP2003233780A Title not availableJP2003242471A Title not availableJP2003243918A Title not availableJP2003249813A Title not availableJP2003288560A Title not availableJP2003309418A Title not availableJP2003317060A Title not availableJP2003331246A Title not availableJP2003332820A Title not availableJP2003529163A Title not availableJP2004040597A Title not availableJP2004082775A Title not availableJP2004096566A Title not availableJP2004127230A Title not availableJP2004234595A Title not availableJP2004253858A Title not availableJP2004280390A Title not availableJP2004287767A Title not availableJP2004297249A Title not availableJP2004297681A Title not availableJP2004319848A Title not availableJP2004326380A Title not availableJP2004334268A Title not availableJP2004336250A Title not availableJP2004343000A Title not availableJP2004362190A Title not availableJP2004362341A Title not availableJP2004362602A Title not availableJP2004505481A Title not availableJP2004519916A Title not availableJP2004527864A Title not availableJP2005124061A Title not availableJP2005128592A Title not availableJP2005129019A Title not availableJP2005136528A Title not availableJP2005137032A Title not availableJP2005165839A Title not availableJP2005167327A Title not availableJP2005167813A Title not availableJP2005190417A Title not availableJP2005191705A Title not availableJP2005210676A Title not availableJP2005210680A Title not availableJP2005217822A Title not availableJP2005229474A Title not availableJP2005236339A Title not availableJP2005244778A Title not availableJP2005275870A Title not availableJP2005284352A Title not availableJP2005293537A Title not availableJP2005295135A Title not availableJP2005311205A Title not availableJP2005321305A Title not availableJP2005322119A Title not availableJP2005335755A Title not availableJP2005345802A Title not availableJP2005346820A Title not availableJP2005352858A Title not availableJP2006025390A Title not availableJP2006031766A Title not availableJP2006102953A Title not availableJP2006107296A Title not availableJP2006148518A Title not availableJP2006151402A Title not availableJP2006174151A Title not availableJP2006195795A Title not availableJP2006203187A Title not availableJP2006203852A Title not availableJP2006217000A Title not availableJP2006232292A Title not availableJP2006237674A Title not availableJP2006270212A Title not availableJP2006270766A Title not availableJP2006285911A Title not availableJP2006295879A Title not availableJP2006302219A Title not availableJP2006309401A Title not availableJP2006311239A Title not availableJP2006323481A Title not availableJP2006513594A Title not availableJP2007007888A Title not availableJP2007043535A Title not availableJP2007048126A Title not availableJP2007096768A Title not availableJP2007102348A Title not availableJP2007122542A Title not availableJP2007150642A Title not availableJP2007150868A Title not availableJP2007159083A Title not availableJP2007159129A Title not availableJP2007228325A Title not availableJP2007266999A Title not availableJP2007312350A Title not availableJP2008160874A Title not availableNL9100176A Title not availableNL9100347A Title not availableWO02/061675A1 Title not availableWO02/097723A1 Title not availableWO03/079305A1 Title not availableWO2000/10122A2 Title not availableWO2004/036772A1 Title not availableWO2004/070879A Title not availableWO2004/072892A1 Title not availableWO2006/045682A Title not availableWO2008/007606A Title not availableWO2099/67754A1 Title not availableWO2005073937A Title not availableWO2005115849A1May 18, 2005Dec 8, 2005Iwata Label Co., Ltd.Rfid label attachment method and attachment deviceWO2007083574A1Jan 12, 2007Jul 26, 2007Murata Manufacturing Co., Ltd.Radio ic device and radio ic device partWO2007083575A1Jan 12, 2007Jul 26, 2007Murata Manufacturing Co., Ltd.Radio ic deviceWO2007119310A1Mar 6, 2007Oct 25, 2007Murata Manufacturing Co., Ltd.AntennaWO2007125683A1Mar 6, 2007Nov 8, 2007Murata Manufacturing Co., Ltd.Article provided with electromagnetically coupled moduleWO2007138857A1May 16, 2007Dec 6, 2007Murata Manufacturing Co., Ltd.Radio frequency ic device and composite component for radio frequency ic deviceWO2008140037A1May 9, 2008Nov 20, 2008Murata Manufacturing Co., Ltd.Wireless ic deviceWO2009011376A1Jul 17, 2008Jan 22, 2009Murata Manufacturing Co., Ltd.Wireless ic deviceWO2009081719A1Dec 8, 2008Jul 2, 2009Murata Manufacturing Co., Ltd.Radio ic deviceNon-Patent CitationsReference1Dokai et al.: "Antenna and Radio IC Device"; U.S. Appl. No. 12/350,307, filed Jan. 8, 2009.2Dokai et al.: "Optical Disc"; U.S. Appl. No. 12/326,916, filed Dec. 3, 2008.3Dokai et al.: "System for Inspecting Electromagnetic Coupling Modules and Radio IC Devices and Method for Manufacturing Electromagnetic Coupling Modules and Radio IC Devices Using the System"; U.S. Appl. No. 12/274,400, filed Nov. 20, 2008.4Dokai et al.: "Test System for Radio Frequency IC Devices and Method of Manufacturing Radio Frequency IC Devices Using the Same"; U.S. Appl. No. 12/388,826, filed Feb. 19, 2009.5Dokai et al.: "Wireless IC Device and Component for Wireless IC Device"; U.S. Appl. No. 11/624,382, filed Jan. 18, 2007.6Dokai et al.: "Wireless IC Device and Component for Wireless IC Device"; U.S. Appl. No. 12/359,690, filed Jan. 26, 2009.7Dokai et al.: "Wireless IC Device and Component for Wireless IC Device," U.S. Appl. No. 12/543,553, filed Aug. 19, 2009.8Dokai et al.: "Wireless IC Device, and Component for Wireless IC Device"; U.S. Appl. No. 11/930,818, filed Oct. 31, 2007.9English translation of NL9100176, published on Mar. 2, 1992.10English translation of NL9100347, published on Mar. 2, 1992.11Ikemoto et al.: "Wireless IC Device and Electronic Apparatus," U.S. Appl. No. 12/503,188, filed Jul. 15, 2009.12Ikemoto et al.: "Wireless IC Device"; U.S. Appl. No. 11/851,651, filed Sep. 7, 2007.13Ikemoto et al.: "Wireless IC Device," U.S. Appl. No. 12/496,709, filed Jul. 2, 2009.14Ikemoto: "Wireless IC Device and Manufacturing Method Thereof," U.S. Appl. No. 12/579,672, filed Oct. 15, 2009.15Kataya et al.: "Radio Frequency IC Device and Electronic Apparatus"; U.S. Appl. No. 12/235,753, filed Sep. 23, 2008.16Kataya et al.: "Radio Frequency IC Device and Electronic Apparatus"; U.S. Appl. No. 12/959,454, filed Dec. 3, 2010.17Kataya et al.: "Wireless IC Device and Electronic Device"; U.S. Appl. No. 11/851,661, filed Sep. 7, 2007.18Kataya et al.: "Wireless IC Device, Electronic Apparatus, and Method for Adjusting Resonant Frequency of Wireless IC Device," U.S. Appl. No. 12/861,945, filed Aug. 24, 2010.19Kato et al.: "Antenna"; U.S. Appl. No. 11/688,290, filed Mar. 20, 2007.20Kato et al.: "Antenna"; U.S. Appl. No. 11/928,502, filed Oct. 30, 2007.21Kato et al.: "Article Having Electromagnetic Coupling Module Attached Thereto"; U.S. Appl. No. 12/401,767, filed Mar. 11, 2009.22Kato et al.: "Component of Wireless IC Device and Wireless IC Device"; U.S. Appl. No. 12/944,099, filed Nov. 11, 2010.23Kato et al.: "Container With Electromagnetic Coupling Module"; U.S. Appl. No. 12/426,369, filed Apr. 20, 2009.24Kato et al.: "Data Coupler"; U.S. Appl. No. 12/252,475, filed Oct. 16, 2008.25Kato et al.: "Electromagnetic-Coupling-Module-Attached Article"; U.S. Appl. No. 11/740,509, filed Apr. 26, 2007.26Kato et al.: "Inductively Coupled Module and Item With Inductively Coupled Module"; U.S. Appl. No. 12/398,497, filed Mar. 5, 2009.27Kato et al.: "Product Including Power Supply Circuit Board"; U.S. Appl. No. 12/234,949, filed Sep. 22, 2008.28Kato et al.: "Radio Frequency IC Device and Radio Communication System," U.S. Appl. No. 12/859,340, filed Aug. 19, 2010.29Kato et al.: "Radio Frequency IC Device"; U.S. Appl. No. 12/336,629, filed Dec. 17, 2008.30Kato et al.: "Wireless IC Device and Component for Wireless IC Device"; U.S. Appl. No. 12/339,198, filed Dec. 19, 2008.31Kato et al.: "Wireless IC Device and Manufacturing Method Thereof," U.S. Appl. No. 12/432,854, filed Apr. 30, 2009.32Kato et al.: "Wireless IC Device and Wireless IC Device Composite Component"; U.S. Appl. No. 12/276,444, filed Nov. 24, 2008.33Kato et al.: "Wireless IC Device System and Method of Determining Authenticity of Wireless IC Device"; U.S. Appl. No. 12/940,105, filed Nov. 5, 2010.34Kato et al.: "Wireless IC Device" U.S. Appl. No. 12/902,174, filed Oct. 12, 2010.35Kato et al.: "Wireless IC Device"; U.S. Appl. No. 12/042,399, filed Mar. 5, 2008.36Kato et al.: "Wireless IC Device"; U.S. Appl. No. 12/211,117, filed Sep. 16, 2008.37Kato et al.: "Wireless IC Device"; U.S. Appl. No. 12/390,556, filed Feb. 23, 2009.38Kato et al.: "Wireless IC Device"; U.S. Appl. No. 12/903,242, filed Oct. 13, 2010.39Kato et al.: "Wireless IC Device"; U.S. Appl. No. 12/940,103, filed Nov. 5, 2010.40Kato et al.: "Wireless IC Device," U.S. Appl. No. 12/469,896, filed May 21, 2009.41Kato et al.: "Wireless IC Device," U.S. Appl. No. 12/510,340, filed Jul. 28, 2009.42Kato et al.: "Wireless IC Device," U.S. Appl. No. 12/510,347, filed Jul. 28, 2009.43Kato et al.: "Wireless IC Device," U.S. Appl. No. 12/603,608, filed Oct. 22, 2009.44Kato et al.: "Wireless IC Device," U.S. Appl. No. 12/688,072, filed Jan. 15, 2010.45Kato et al.: "Wireless IC Device," U.S. Appl. No. 12/859,880, filed Aug. 20, 2010.46Kato et al.; "Information Terminal Device"; U.S. Appl. No. 12/267,666, filed Nov. 10, 2008.47Kato: "Composite Antenna," U.S. Appl. No. 12/845,846, filed Jul. 29, 2010.48Kato: "Wireless IC Device and Electromagnetic Coupling Module," U.S. Appl. No. 12/890,895, filed Sep. 27, 2010.49Kato: "Wireless IC Device"; U.S. Appl. No. 11/964,185, filed Dec. 26, 2007.50Kato: "Wireless IC Device"; U.S. Appl. No. 12/429,346, filed Apr. 24, 2009.51Kato: "Wireless IC Device," U.S. Appl. No. 12/510,344, filed Jul. 28, 2009.52Kimura et al.: "Wireless IC Device," U.S. Appl. No. 12/510,338, filed Jul. 28, 2009.53Mukku-Sha, "Musen IC Tagu Katsuyo-no. Subete" "(All About Wireless IC Tags"), RFID, pp. 112-126.54Official Communication issued in corresponding Japanese Patent Application No. 2010-506742, mailed on Apr. 6, 2010.55Official communication issued in counterpart European Application No. 08 77 7758, dated on Jun. 30, 2009.56Official communication issued in counterpart International Application No. PCT/JP2008/051853, mailed Apr. 22, 2008.57Official communication issued in counterpart International Application No. PCT/JP2008/055567, mailed May 20, 2008.58Official communication issued in counterpart International Application No. PCT/JP2008/056026, mailed Jul. 1, 2008.59Official communication issued in counterpart International Application No. PCT/JP2008/057239, mailed Jul. 22, 2008.60Official communication issued in counterpart International Application No. PCT/JP2008/058168, mailed Aug. 12, 2008.61Official communication issued in counterpart International Application No. PCT/JP2008/062886, mailed Oct. 21, 2008.62Official communication issued in counterpart International Application No. PCT/JP2008/062947, mailed Aug. 19, 2008.63Official communication issued in counterpart International Application No. PCT/JP2008/071502, mailed Feb. 24, 2009.64Official communication issued in counterpart Japanese Application No. 2008-103741, mailed on May 26, 2009.65Official communication issued in counterpart Japanese Application No. 2008-103742, mailed on May 26, 2009.66Official communication issued in European Application No. 07706650.4, mailed on Nov. 24, 2008.67Official Communication issued in International Application No. PCT/JP2007/066007, mailed on Nov. 27, 2007.68Official Communication issued in International Application No. PCT/JP2007/066721, mailed on Nov. 27, 2007.69Official Communication issued in International Application No. PCT/JP2007/070460, mailed on Dec. 11, 2007.70Official communication issued in International Application No. PCT/JP2008/050356, mailed on Mar. 25, 2008.71Official communication issued in International Application No. PCT/JP2008/050358, mailed on Mar. 25, 2008.72Official communication issued in International Application No. PCT/JP2008/058614, mailed on Jun. 10, 2008.73Official Communication issued in International Application No. PCT/JP2008/061955, mailed on Sep. 30, 2008.74Official Communication issued in International Patent Application No. PCT/JP2008/050945, mailed on May 1, 2008.75Official Communication issued in International Patent Application No. PCT/JP2008/061442, mailed on Jul. 22, 2008.76Official Communication issued in International Patent Application No. PCT/JP2008/063025, mailed on Aug. 12, 2008.77Official Communication issued in International Patent Application No. PCT/JP2009/053690, mailed on Jun. 2, 2009.78Official Communication issued in International Patent Application No. PCT/JP2009/053693, mailed on Jun. 9, 2009.79Official Communication issued in International Patent Application No. PCT/JP2009/055758, mailed on Jun. 23, 2009.80Official Communication issued in International Patent Application No. PCT/JP2009/056698, mailed on Jul. 7, 2009.81Official Communication issued in International Patent Application No. PCT/JP2009/056934, mailed on Jun. 30, 2009.82Official Communication issued in International Patent Application No. PCT/JP2009/057482, mailed on Jul. 21, 2009.83Official Communication issued in International Patent Application No. PCT/JP2009/059259, mailed on Aug. 11, 2009.84Official Communication issued in International Patent Application No. PCT/JP2009/059410, mailed on Aug. 4, 2009.85Official Communication issued in International Patent Application No. PCT/JP2009/059669, mailed on Aug. 25, 2009.86Official communication issued in Japanese Application No. 2007-531524, mailed on Dec. 12, 2007.87Official communication issued in Japanese Application No. 2007-531524, mailed on Sep. 11, 2007.88Official communication issued in Japanese Application No. 2007-531525, mailed on Sep. 25, 2007.89Official communication issued in related U.S. Appl. No. 12/042,399; mailed on Aug. 25, 2008.90Osamura et al.: "Packaging Material With Electromagnetic Coupling Module," U.S. Appl. No. 12/536,663, filed Aug. 6, 2009.91Osamura et al.: "Packaging Material With Electromagnetic Coupling Module," U.S. Appl. No. 12/536,669, filed Aug. 6, 2009.92Shioya et al.: "Wireless IC Device," U.S. Appl. No. 12/551,037, filed Aug. 31, 2009.93Taniguchi et al.: "Antenna Device and Radio Frequency IC Device"; U.S. Appl. No. 12/326,117, filed Dec. 2, 2008.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8232630 *Mar 23, 2011Jul 31, 2012Toppan Printing Co., Ltd.Contactless communication mediumUS8837159 *Oct 28, 2009Sep 16, 2014Amazon Technologies, Inc.Low-profile circuit board assemblyUS8877558Feb 7, 2013Nov 4, 2014Harris CorporationMethod for making electronic device with liquid crystal polymer and related devicesUS9131623Aug 14, 2014Sep 8, 2015Amazon Technologies, Inc.Low-profile circuit board assemblyUS9293438Jul 3, 2013Mar 22, 2016Harris CorporationMethod for making electronic device with cover layer with openings and related devicesUS20110169146 *Mar 23, 2011Jul 14, 2011Toppan Printing Co., Ltd.Contactless communication medium* Cited by examinerClassifications U.S. Classification235/486, 257/678, 235/487, 257/679, 235/492, 257/700International ClassificationG06K7/00, H01L23/12, H01L23/02, G06K19/00, G06K19/06Cooperative ClassificationY10T29/49124, H05K2203/0278, H01L2924/07802, G06K19/07749, H05K3/0061, H01L2924/14, H01L2224/13139, H01L24/97, H05K1/183, H01L23/49827, H01L2924/3011, H01L23/49822, H01L23/13, H01L2224/16, H05K1/112, H01L24/16, H01L2224/13144, H01L23/49855, H01L2924/01079, H05K2201/10674European ClassificationH01L23/13, H01L23/498E, H05K1/18C2, G06K19/077T, H01L23/498D, H01L23/498KLegal EventsDateCodeEventDescriptionDec 7, 2010ASAssignmentOwner name: MURATA MANUFACTURING CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KATO, NOBORU;SASAKI, YUTAKA;OZAWA, MASAHIRO;REEL/FRAME:025460/0668Effective date: 20090427Feb 18, 2015FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services

value: This website is a search engine provided by Google. Handling over 3.5 billion searches per day, it has a 92% share of the global search engine market.