text:
Kalmar Lamp | eBay
Midcentury German KALMAR Ice Crystal Glass Accent Boudoir Lamp
Terrific 1950s era German Kalmar ice crystal boudoir or accent lamp. Total height approx 8.25”, glass shade itself is 7” tall and 3” dia with wooden base. Fresh from a fine old Denver estate, and offe...
User ID denverdish (Feedback score 13921)
Terrific pair of 1950s era German Kalmar ice crystal boudoir or accent lamps. Total height approx 8.25”, glass shade itself is 7” tall and 3” dia with wooden base. Fresh from a fine old Denver estate,...
Mid Century KINKELDEY Tulipan Chandelier Pendant Lamp Kalmar Era Palwa Sciolari
VERY rare, spectacular, large, stepless height adjustable, ORIGINAL 1960s Kinkeldey International "Belvedere" chandelier. Fully functional (see pictures). : Height: 33,46" (85 cm.). Note: We've used b...
Signed KAISER drum ice glass CHANDELIER GERMANY 60´s lamp kalmar bauhaus dell
It has 12 thick-walled (1,5 cm / 0.60 in.). The wiring is perfect, so it´s in fine working condition. It´s made of high quality and best materials. The body of the lamp is approx.16 cm / 6.30 in. tall...
Kalmar Stilnovo RARE 50s 60s mid-century source reference book of lamp design
Text written in German and in the back. First edition of this very hard-to-find book. With 100's of b/w photographs of. Feel free to ask - I will answer asap. it includes english and french translatio...
Great KALMAR AUSTRIA ice glass TUBE PENDANT LAMP 60´s kaiser doria panton eames
Up for sale is this beautiful midcentury KALMAR / AUSTRIA tube pendant lamp which can be dated VIENNA around 1950 -1960. The glass body is approx. 17 cm / 6.69 in. tall and has a width of 17 cm / 6.69...
CITRUS ICE GLASS FLUSH MOUNT LAMP, signed J.T. Kalmar, Vienna 1960's
Design: J. T. Kalmar. Manufacturer: Studio Kalmar, made in Austria. Content: 1 lamp.
Ice Glass Wall Lamp / Sconce Hillbrand Kalmar style - Length 15 inches (38 cm)
Made of three thick walled glass parts mounted to a slim tall glass shade. the glass parts are sanded inside. the outside is clear with structured snake lines.
Ice Glass CHANDELIER Ceiling Lamp by J.T. KALMAR 1960s
8 x E14 sockets.
Glass Height: 25 cm (10 in).
XL Hillebrand Flush Mount Lamp Brass Bubble Ice Glass light 60s 70s kalmar
Beautiful flush mount light fixture. Brass shows minor tarnish and is a little bit dusty, but this is over 40 years old. The fixture has an german wiring. Works with five E14 / 110 volt Light bulbs.
Tulipan wall lamps by Kalmar 60s Set of 2
J. T. Kalmar for Kalmar 60s.
1/2 LARGE Mid Century Modern COPPER Ceiling Light PENDANT LAMP J.T. KALMAR attr.
DESIGNED AND MANUFACTURED PROBABLY BY J.T. KALMAR, VIENNA IN 1950s / 1960s. Up for sale a rare, large and gorgeous mid century modern uplight ceiling lamp | pendant lamp. Designed and manufactured pro...
A large and wonderful multi-tiered chandelier in the style of Kalmar, Austria, manufactured in Mid-Century, circa 1970. The light takes six small base Edison bulbs E14 up to 40Watt or lower. (not incl...
KALMAR lamp glass hanging fixture vintage chandelier retro pendant sputnik
Glass Globe TABLE LAMP Sputnik Desk Light by J.T. Kalmar 1960s clear chrome
Original Kalmar ice glass lamp, fixture, little pendant, Austria 1960's - 70's
W ear consistent with age and use.
Elegant, high quality gilt brass and clear textured ice glass flush mount or ceiling light by Kalmar Franken Austria 1970s. This lamp is an eyecatcher. It would be a perfekt addition and upgrade for a...
Kalmar Tulipan Chandelier Glass Flush Mount Tulip Lamp VTG 1950's - 60's
1950' - 1960's flush mount by Kalmar - Modell Tulipan (tulip).
MANUFACTURED IN 1950s | J.T. KALMAR | BORIS LACROIX ERA. Lamp shades adjustable. Manufactured in 1950s. signs of use and age. They are wired and work.
J.T. Kalmar CHANDELIER Ice Glass Ceiling Lamp 1960s
Gorgeous hand blown ice glass chandelier from the design manufacturer J.T. Kalmar, Vienna 1960s. Takes 3 small edison bulbs. Height: appr.
VINTAGE KALMAR ICE GLASS massive BEDSIDE LAMP 1960 NICE
KALMAR VIENNA - HIGH QUALITY. FROM APPROX 1960. UM 1960. FITS WELL IN A BED ROOM. THE LAMP IS IN WORKING CONDITION. GOOD ORIGINAL CONDITION. SCHÖNER ORIGINAL ZUSTAND. HÖHE 25 CM.
Great J.T. KALMAR AUSTRIA midcentury TUBE PENDANT LAMP 60´s kaiser ponti doria
The big glass cylinder is made of clear glass with a nice wavy structure. The glass body is approx. 30 cm / 11.81 in. tall and has a width of 15 cm / 5.91 in., the total length including wire is 150 c...
Original Kalmar Ice Glass Wall Lamp Mid Century Sconce Vintage 1960-1970`s 2/2
Original 1960's 1970's Kalmar pull switch wall lamp. total width 16 " - height 9" - depth 4.7" - glass parts 7" x 7". made of asteel mounting with mouthblown glass ti les.
Vintage glass ceiling lamp, sconce, fixture, 1960s, Kaiser- Germany, Kalmar- Era
Kalmar- Era. Kalmar- style. 1960s, Kaiser- Germany. by Kaiser- Germany,1960s. Height glass: 5,9 in / 15 cm. Weight: 5,7 lbs / 2,6 kg. Very good overall condition, electrical tested and functional.
Original Kalmar Ice Glass Wall Lamp Mid Century Sconce Vintage 1960-1970`s 1/2
Original 1960's 1970's Kalmar pull switch wall lamp. nearly mint without any chip or crack. total width 16 " - height 9" - depth 4.7" - glass parts 7" x 7". made of asteel mounting with mouthblown gla...
VINTAGE MID C SOLID HEAVY KALMAR ICE GLASS WALL LAMP L 14" FUNCTION 1960
SOLID MASSIVE ICE GLASS LAMP. THE LAMP WAS IN WORKING CONDITION. THE LAMP HAS BEEN CLEANED. IN FUNCTION. L CA 14 ". GOOD ORIGINAL CONDITION - MINOR TRACES OF WEAR - CABLES OK -. A 8010 GRAZ.
Vintage Kalmar Pendant Lamp Glass Chandelier Light Mid Century 60`s 70`s
Exceptional Kalmar pendant lamp. made of 4 heavy glass leaves fixed at a steel mounting. height glass 15.4" (39 cm). weight 10.6 kg. you need a 110 volt E27 bulb to operate.


text: Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5761064 *Oct 6, 1995Jun 2, 1998Advanced Micro Devices, Inc.Defect management system for productivity and yield improvementUS5896294 *Mar 11, 1997Apr 20, 1999Advanced Micro Devices, Inc.Method and apparatus for inspecting manufactured products for defects in response to in-situ monitoringUS6035293 *Oct 20, 1997Mar 7, 2000Advanced Micro Devices, Inc.Validating process data in manufacturing process managementUS6165805 *Oct 29, 1998Dec 26, 2000Advanced Micro Devices, Inc.Scan tool recipe serverUS6185474Mar 2, 1998Feb 6, 2001Canon Kabushiki KaishaExposure unit, exposure system and device manufacturing methodUS6415193 *Jul 8, 1999Jul 2, 2002Fabcentric, Inc.Recipe editor for editing and creating process recipes with parameter-level semiconductor-manufacturing equipmentUS6465263 *Jan 4, 2000Oct 15, 2002Advanced Micro Devices, Inc.Method and apparatus for implementing corrected species by monitoring specific state parametersUS20020183950 *Jul 24, 2001Dec 5, 2002Ming-Rong FuRecipe comparison systemUS20030204281 *Apr 30, 2002Oct 30, 2003Yeaun-Jyh SuSemiconductor wafer manufacturing execution system with recipe distribution management database* Cited by examinerNon-Patent CitationsReference1W. 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D., "Run-to-Run Control of Photolithography Processes," Special Focus Lithography, Yield Management Solutions, Summer 2000, pp. 65-68.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6898471 *Dec 31, 2003May 24, 2005Taiwan Semiconductor Manufacturing CompanyMultivariate RBR tool aging adjusterUS6898478 *Aug 20, 2003May 24, 2005Precision Automation, Inc.Systems and methods of processing materialsUS6957116 *Oct 3, 2003Oct 18, 2005Taiwan Semiconductor Manufcturing Co., Ltd.Quality assurance system and methodUS7248936 *Jan 31, 2006Jul 24, 2007International Business Machines CorporationAutomated tool recipe verification and correctionUS7280885 *Dec 1, 2004Oct 9, 2007Advanced Micro Devices, Inc.Method and apparatus to reconcile recipe manager and manufacturing execution system context configurationsUS7283882 *Feb 15, 2006Oct 16, 2007Kla-Tencor Technologies CorporationAutomatic recipe validationUS7305320Feb 15, 2006Dec 4, 2007International Business Machines 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2006Aug 24, 2006Lam Research CorporationProcessing information management in a plasma processing toolWO2006089208A3 *Feb 16, 2006Dec 13, 2007Chung-Ho HuangProcessing information management in a plasma processing tool* Cited by examinerClassifications U.S. Classification700/121, 700/110, 700/96, 717/170, 707/999.203, 707/999.202International ClassificationG06F19/00, G05B19/418Cooperative ClassificationY02P90/18, Y02P90/20, Y10S707/99953, Y10S707/99954, G05B2219/31186, G05B2219/34253, G05B2219/32097, G05B2219/45031, G05B19/41865European ClassificationG05B19/418PLegal EventsDateCodeEventDescriptionOct 21, 2002ASAssignmentOwner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOU, ALTON;WEI, CHEN-HSIEN;REEL/FRAME:013414/0535Effective date: 20021015Sep 21, 2004CCCertificate of correctionSep 20, 2007FPAYFee paymentYear of fee payment: 4Sep 19, 2011FPAYFee paymentYear of fee payment: 8Dec 18, 2015REMIMaintenance fee reminder mailedMay 11, 2016LAPSLapse for failure to pay maintenance feesJun 28, 2016FPExpired due to failure to pay maintenance feeEffective date: 20160511RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services

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text:
9780813042060: Digging Miami - AbeBooks - Robert S. Carr: 0813042062
Robert S. Carr Digging Miami
ISBN 13: 9780813042060
“A wonderful, moving narrative of the archaeology of greater Miami.”—Paul George, editor of Tequesta
“Amazing. In spite of the intense urban development of southeast Florida, valuable archaeological contexts are still present and continually being discovered.”—Randolph Widmer, University of Houston
“Through the work and writing of Bob Carr, the current generation can connect to the myriad of human beings who came before them and called South Florida home. As an archaeologist and writer, Carr has exposed, documented, and described in a thoroughly readable manner a unique place and 10,000 years of human habitation.”—Arva Moore Parks, author of Miami Then and Now
3. Digging Miami (Hardback)
4. Digging Miami (Hardback)
5. Digging Miami -
6. Digging Miami
Book Description University Press of Florida, 2012. Hardcover. Condition: New. book. Seller Inventory # M0813042062
7. Digging Miami
Book Description Univ Pr of Florida, 2012. Hardcover. Condition: Brand New. 352 pages. 6.50x5.98x0.98 inches. In Stock. Seller Inventory # z-0813042062
8. Digging Miami
Book Description University Press of Florida, 2012. Hardcover. Condition: New. Never used!. Seller Inventory # P110813042062
9. Digging Miami (Hardcover)

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text:
Ksport Kontrol Pro Coilovers Shocks Springs Hyundai Genesis Sedan 4 6L V8 | eBay Skip to main contenteBayShop by categoryEnter your search keywordAll CategoriesAdvanced or register':' style="margin-right:3px">Hi -User-!'.replace(/-User-/,escape(a)))+"")}catch(b){document.write("")}})();Hi (Sign in to bid or buy)Daily DealsGift CardsSellHelp & ContactMy eBayExpand My eBaySummaryBids/OffersWatch listWish listAll listsPurchase historySellingMy CollectionsFollowed searchesMessagesNotification Back to home page
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Details about Ksport Kontrol Pro Coilovers Shocks Springs - Hyundai Genesis Sedan 4.6L V8
Ksport Kontrol Pro Coilovers Shocks Springs - Hyundai Genesis Sedan 4.6L V8
11:36:34 PST
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eBay item number:350466388917
Sep 27, 2011 20:09:21 PDT View all revisions
Portions of the information contained in this table have been provided by solowspeed
Surface Finish: Black / Orange
Manufacturer Part Number: CHY153-KP
xlevelonlinedotcom
Spring Rates 9.8kg/mm (549lbs.in.) F
8.5kg/mm (476lbs.in.) R
KSP-CHY153-KP
*Pictures may not be application specific.
This item is very popular and may sell out from time to time. If you need the item right away, please call to check stock. If it is sold out, they will usually ship within 2 weeks. The maximum wait will be three weeks and the item will be drop shipped directly to you so as to not delay your order further.
36-way adjustable damping. Simultaneously adjust compression & rebound.
Single cylinder design (mono-tube).
6061 billet aluminum collars, brackets, and upper mounts.
SAE-9254 cold wound steel, linear rate springs.
Separate lower bracket allows ride height to be adjusted without sacrificing stroke or preloading the suspension.
Steel shock body is zinc electroplated to resist rust and corrosion.
Front camber adjustable pillow ball top mounts included and feature spherical bearing to give the driver greater feedback. Must re-use OEM rear mounts.
Hyundai Genesis 09+ 4dr. 4.6L V8
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Canada’s Economy Rebounds Faster Than Forecast on Exports - Bloomberg For more local news from India, visit Bloombergquint.com Bloomberg the Company & Its ProductsBloomberg Anywhere Remote LoginBloomberg Anywhere LoginBloomberg Terminal Demo Request Bloomberg
Bloomberg Anywhere Remote LoginDownload SoftwareService Center MENU Homepage Markets Stocks Currencies Commodities Rates + Bonds Economics Magazine Benchmark Watchlist Economic Calendar Tech Silicon Valley Global Tech Venture Capital Hacking Digital Media Bloomberg West Pursuits Cars & Bikes Style & Grooming Spend Watches & Gadgets Food & Drinks Travel Real Estate Art & Design Politics With All Due Respect Delegate Tracker Culture Caucus Podcast Masters In Politics Podcast What The Voters Are Streaming Editors' Picks Opinion View Gadfly Businessweek Subscribe Cover Stories Opening Remarks Etc Features 85th Anniversary Issue Behind The Cover More Industries Science + Energy Graphics Game Plan Small Business Personal Finance Inspire GO Board Directors Forum Sponsored Content Sign In Subscribe Canada’s Economy Rebounds Faster Than Forecast on Exports Greg Quinn November 30, 2011 — 4:01 PM EST Share on FacebookShare on TwitterShare on WhatsApp Share on LinkedInShare on RedditShare on Google+E-mailShare on TwitterShare on WhatsApp Share on FacebookShare on TwitterShare on WhatsApp Share on LinkedInShare on RedditShare on Google+E-mailShare on TwitterShare on WhatsApp Canada’s economy rebounded at a faster pace than economists forecast in the third quarter as the biggest jump in exports since 2004 more than offset slower domestic spending.
Companies such as telecommunications firm BCE Inc. and Montreal-based railway tie-maker Stella Jones Inc. expect sales growth next year even as the Bank of Canada and the Organization for Economic Cooperation and Development cut their forecasts. Exporters are being supported by the 3.7 percent decline in Canadian dollar versus its U.S. counterpart in the last six months. The rebound “gives the Canadian economy some much needed momentum against a set of headwinds that will become far more pronounced in early 2012,” said David Tulk, chief Canada macro strategist at Toronto-Dominion Bank’s TD Securities unit. Today the Bank of Canada joined with central banks in the U.S. and Europe to cut the cost of emergency U.S.-dollar funding for banks.
The Canadian dollar held onto gains following the report, rising 1.2 percent to C$1.0200 per U.S. dollar at 3:57 p.m. Toronto time. It earlier gained 1.9 percent, the biggest advance on an intraday basis since May 27, 2010. One Canadian dollar buys 98.04 U.S. cents.
The yield on the 10-year benchmark federal government bond rose 3 basis points to 2.15 percent.
Exports ReboundExports of goods and services rose at a 14.4 percent annualized pace in the third quarter, the fastest since the middle of 2004, rebounding from a 6.4 percent decline in the second quarter. “Although global economic conditions have recently been volatile, the markets we serve in North America should continue to provide Stella-Jones with steady demand for its core products,” Chief Executive Officer Brian McManus said on a Nov. 11 earnings call. The Montreal-based company makes railway ties and telephone poles.
Renewed OutputPart of the gain in output was linked to renewed work by energy companies that had been hampered earlier by wildfires in Alberta and maintenance shutdowns.
One area of strength in domestic spending was housing, with a 2.6 percent increase that was the fastest since the start of last year.
Inventories rose by C$10.4 billion in the third quarter, half of the C$20.8 billion seen in the second
“Today’s numbers showing significant growth in the Canadian economy last quarter are very encouraging,” Prime Minister Stephen Harper told the House of Commons in Ottawa. “At the same time we remain very concerned about problems, particularly in Europe, the problems of debt and deficit.”
Bank of Canada Governor Mark Carney said in Montreal Nov. 23 that Europe’s debt crisis is “barely contained” and he has “flexibility” in keeping interest rates low while meeting his inflation target. The next rate decision is Dec. 6 and economists surveyed by Bloomberg forecast the key policy rate will remain at 1 percent where it’s been since September 2010.
Forecast ChallengeThe U.S. economy grew at a 2 percent annual rate from July through September, according to revised Commerce Department figures published Nov. 22.
The contraction from April to June was the first since the the end of the last recession in mid-2009. The decline and rebound, and their link to temporary factors, leaves questions about the rate of growth that can be sustained, said Ian Pollick, senior fixed income strategist at RBC Capital Markets in Toronto.
Litmus Test“Attention should be paid to the incoming fourth-quarter data as this will be the real litmus test into how the Canadian economy is actually faring,” Pollick said in a note to clients.

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Yoga Pod Cherry Creek - Denver, CO | Groupon
2780 East 6th Avenue, Denver, CO 80206 2780 East 6th Avenue, Denver Directions
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Groupon has verified that the customer actually visited Yoga Pod Cherry Creek.

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Financial Accounting, Study Guide / Edition 3 by Jerry J. Weygandt, Donald E. Kieso, Paul D. Kimmel | | 9780471372660 | Paperback | Barnes & Noble
Financial Accounting, Study Guide / Edition 3
Table of ContentsAccounting in Action. The Recording Process.Adjusting the Accounts.Completion of the Accounting Cycle.Accounting for Merchandising Operations.Inventories.Accounting Principles.Internal Control and Cash.Accounting for Receivables.Plant Assets, Natural Resources, and Intangible Assets.Liabilities.Corporations: Organization, Stock Transactions, Dividends, and Retained Earnings.Investments.The Statement of Cash Flows.Financial Statement Analysis.Appendices.

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text:
Roman Manevich - Semantic Scholar
Shmuel Sagiv70
Thomas W. Reps44
Tal Lev-Ami37
Reinhard Wilhelm36
18Noam Rinetzky
18G. Ramalingam
16Ondrej Lhoták
16Josh Berdine
In this paper, we describe PSE (Postmortem Symbolic Evaluation), a static analysis algorithm that can be used by programmers to diagnose software failures. The algorithm requires minimal information about a failure, namely its kind (e.g. NULL dereference), and its location in the program's source code. It produces a set of execution traces along which the… (More)
Roman Manevich, Eran Yahav, G. Ramalingam, Shmuel Sagiv
Predicate abstraction and canonical abstraction are two finitary abstractions used to prove properties of programs. We study the relationship between these two abstractions by considering a very limited case: abstraction of (potentially cyclic) singly-linked lists. We provide a new and rather precise family of abstractions for potentially cyclic… (More)
Josh Berdine, Tal Lev-Ami, Roman Manevich, G. Ramalingam, Shmuel Sagiv
We present new algorithms for automatically verifying properties of programs with an unbounded number of threads. Our algorithms are based on a new abstract domain whose elements represent thread-quantified invariants: i.e., invariants satified by all threads. We exploit existing abstractions to represent the invariants. Thus, our technique lifts existing… (More)
Tal Lev-Ami, Roman Manevich, Shmuel Sagiv
The course will present TVLA (Three-Valued-Logic Analyzer). TVLA is a ”‘YACC’”’-like framework for automatically constructing abstract interpreters from an operational semantics. The operational semantics is specified as a generic transition system based on first order logic. TVLA has been implemented in Java and was successfully used to prove interesting… (More)
Roman Manevich, Shmuel Sagiv, G. Ramalingam, John Field
One of the continuing challenges in abstract interpretation is the creation of abstractions that yield analyses that are both tractable and precise enough to prove interesting properties about real-world programs. One source of difficulty is the need to handle programs with different behaviors along different execution paths. Disjunctive (powerset)… (More)
Roman Manevich, Tal Lev-Ami, Shmuel Sagiv, G. Ramalingam, Josh Berdine
We demonstrate shape analyses that can achieve a state space reduction exponential in the number of threads compared to the state-of-the-art analyses, while retaining sufficient precision to verify sophisticated properties such as linearizability. The key idea is to abstract the global heap by decomposing it into (not necessarily disjoint) subheaps,… (More)
Combining Shape Analyses by Intersecting Abstractions
Gilad Arnold, Roman Manevich, Shmuel Sagiv, Ran Shaham
We consider the problem of computing the intersection (meet) of heap abstractions.This problem is useful, among other applications, to relate abstract memory states computed by forward analysis with abstract memory states computed by backward analysis. Since dynamically allocated heap objects have no static names, relating objects computed by different… (More)
Michael Emmi, Rupak Majumdar, Roman Manevich
We describe an automatic verification method to check whether transactional memories ensure strict serializability a key property assumed of the transactional interface. Our main contribution is a technique for effectively verifying parameterized systems. The technique merges ideas from parameterized hardware and protocol verification--verification by… (More)

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Patent US6593937 - Method of and apparatus for handling high bandwidth on-screen-display ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsOn-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display device, as a stream of isochronous...http://www.google.com/patents/US6593937?utm_source=gb-gplus-sharePatent US6593937 - Method of and apparatus for handling high bandwidth on-screen-display graphics data over a distributed IEEE 1394 network utilizing an isochronous data transmission formatAdvanced Patent SearchPublication numberUS6593937 B2Publication typeGrantApplication numberUS 09/251,586Publication dateJul 15, 2003Filing dateFeb 17, 1999Priority dateJun 18, 1998Fee statusPaidAlso published asDE69907673D1, DE69907673T2, EP1088449A1, EP1088449B1, US7075557, US20020089517, US20030210252, WO1999066720A1Publication number09251586, 251586, US 6593937 B2, US 6593937B2, US-B2-6593937, US6593937 B2, US6593937B2InventorsHarold Aaron Ludtke, Scott D. Smyers, Mark Kenneth EyerOriginal AssigneeSony Corporation, Sony Electronics, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (60), Non-Patent Citations (16), Referenced by (21), Classifications (65), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethod of and apparatus for handling high bandwidth on-screen-display graphics data over a distributed IEEE 1394 network utilizing an isochronous data transmission formatUS 6593937 B2Abstract On-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display device, as a stream of isochronous data, separate from video data. Each packet of isochronous data within the stream of on-screen-display graphics data includes an address value corresponding to a memory address within the display device forming a buffer. When received by the display device the on-screen-display graphics data is loaded into the appropriate memory locations within the buffer corresponding to the address values. At the display device, an embedded stream processor is utilized to strip the header information from each packet and determine the appropriate memory location that the data is to be stored. A trigger packet is sent at the end of the data stream for a screen of on-screen-display graphics. The trigger packet includes a presentation time value corresponding to a display time for the screen of on-screen-display graphics. When the trigger packet is received, the display device transfers the data stored in the buffer to a VRAM circuit for display at the specified presentation time. The on-screen-display graphics data can be overlaid on video data for display and also displayed separately. Differential encoding is used when transferring frames of data wherein only a portion of data changes from the previous frame.
We claim: 1. A method of transmitting on-screen-display graphics data from a source device to a display device separate from a video stream of data comprising:
a. generating on-screen-display graphics to be displayed on the display device; b. combining the on-screen-display graphics into a stream of data packets, each including an address value corresponding to a memory location within the display device; and c. transmitting the data packets from the source device to the display device separate from the video stream of data. 2. The method as claimed in claim 1 further comprising transmitting a trigger packet on occurrence of a trigger event, the trigger packet including a trigger address value corresponding to a trigger memory location within the display device.
3. The method as claimed in claim 2 wherein the trigger packet includes a trigger bit, which when written into the trigger memory location, signals that storage of a current frame of on-screen-display graphics data is complete.
4. The method as claimed in claim 3 wherein the trigger packet also includes an overlay bit specifying whether or not the on-screen-display graphics are to be combined with video data.
5. The method as claimed in claim 1 wherein the data packets are isochronous packets.
6. The method as claimed in claim 1 wherein the data packets are asynchronous packets.
7. A method of transmitting on-screen-display graphics data from a source device to a display device comprising:
a. generating on-screen-display graphics to be displayed on the display device; b. combining the on-screen-display graphics into a stream of isochronous data packets, each including an address value corresponding to a memory location within the display device; c. transmitting the isochronous data packets from the source device to the display device over an isochronous channel; and d. transmitting a trigger packet on the occurrence of a trigger event, the trigger packet including a trigger address value corresponding to a trigger memory location within the display device. 8. The method as claimed in claim 7 further comprising:
a. receiving the isochronous data packets at the display device; and b. storing data included within each of the isochronous data packets at the memory location specified by the address value included within the isochronous data packet. 9. The method as claimed in claim 8 further comprising:
a. compressing the on-screen-display graphics before the isochronous data packets are formed; and b. decompressing the data at the display device before the storing is completed. 10. The method as claimed in claim 7 wherein the trigger packet further includes a presentation time value specifying a display time for the on-screen-display graphics.
11. The method as claimed in claim 10 wherein the trigger event occurs when all isochronous data packets for a screen of the on-screen-display graphics have been transmitted.
a. receiving the isochronous data packets at the display device; b. storing data included within each of the isochronous data packets at the memory location specified by the address value included within the isochronous data packet; c. receiving the trigger packet at the display device; d. storing the trigger packet at the trigger memory location; and e. displaying the screen of on-screen-display graphics at the display time. 13. The method as claimed in claim 12 wherein the memory locations and the trigger memory location within the display device are included within an on-screen-display graphics buffer.
14. The method as claimed in claim 13 wherein the memory locations are included within an on-screen-display graphics buffer and the trigger memory location is included within a trigger buffer.
15. The method as claimed in claim 13 wherein the trigger packet includes a trigger bit, which when written into the trigger memory location, signals that storage of a current frame of on-screen-display graphics data is complete.
16. The method as claimed in claim 15 wherein the trigger packet also includes an overlay bit specifying whether or not the on-screen-display graphics are to be combined with video data.
17. The method as claimed in claim 13 wherein the isochronous data packets and the trigger packet are transmitted from the source device to the display device over a high speed serial interface.
18. The method as claimed in claim 17 wherein the high speed serial interface is an IEEE 1394 serial bus network.
a. generating a subsequent screen of on-screen-display graphics to be displayed on the display device; b. determining changed pixels within the subsequent screen as compared to a previous screen of on-screen-display graphics; c. combining the on-screen-display data representing only the changed pixels into a differential stream of isochronous data packets, each differential isochronous packet including an address value corresponding to the memory location related to represented changed pixels; and d. transmitting the isochronous data packets from the source device to the display device over the isochronous channel. 20. A method of receiving on-screen-display graphics data, generated by a source device and transmitted in isochronous data packets over an isochronous channel to a display device, each isochronous data packet including an address value corresponding to a memory location within the display device, comprising:
a. receiving an isochronous data packet including on-screen-display graphics data and the address value; b. storing the on-screen-display graphics data included within the isochronous data packet at the memory location within the display device; c. receiving a trigger packet including a trigger address value, corresponding to a trigger memory location within the display device, and presentation time value specifying a display time for the on-screen-display graphics; and d. displaying the on-screen-display graphics at the display time. 21. The method as claimed in claim 20 further comprising storing the trigger packet at the trigger memory location.
22. The method as claimed in claim 21 wherein the trigger packet includes a trigger bit, which when written into the trigger memory location, signals that storage of a current frame of on-screen-display graphics data is complete.
23. The method as claimed in claim 21 further comprising decompressing the on-screen-display graphics, if the on-screen-display graphics had previously been compressed, before the storing is completed.
24. The method as claimed in claim 21 wherein the memory locations and the trigger memory location are included within an on-screen-display graphics buffer.
25. The method as claimed in claim 24 wherein the isochronous data packets and the trigger packet are transmitted from the source device to the display device over a high speed serial interface.
26. The method as claimed in claim 25 wherein the high speed serial interface is an IEEE 1394 serial bus network.
27. An apparatus for transmitting on-screen-display graphics data from a source device to a display device comprising:
a. a graphics source for generating on-screen-display graphics to be displayed by the display device; b. an interface circuit coupled to the graphics source and configured for coupling to the display device for combining the on-screen-display graphics into a stream of isochronous data packets each including an address value corresponding to a memory location within the display device and transmitting the isochronous data packets from the source device to the display device over an isochronous channel; wherein the graphics source also generates a trigger packet which is transmitted by the interface circuit on the occurrence of a trigger event, the trigger packet including a trigger address value corresponding to a trigger memory location within the display device.
28. The apparatus as claimed in claim 27 wherein the trigger event occurs when all isochronous data packets for a screen of on-screen-display graphics have been transmitted from the interface circuit.
29. The apparatus as claimed in claim 28 wherein the trigger packet further includes a presentation time value specifying a display time for the screen of on-screen-display graphics.
30. The apparatus as claimed in claim 29 wherein the trigger packet includes a trigger bit, which when written into the trigger memory location, signals that storage of a current frame of on-screen-display graphics data is complete.
31. The apparatus as claimed in claim 30 wherein the trigger packet also includes an overlay bit specifying whether or not the on-screen-display graphics are to be combined with video data.
32. The apparatus as claimed in claim 29 further comprising a compression circuit coupled to the graphics source and to the interface circuit for compressing the on-screen-display graphics before transmission by the interface circuit.
33. The apparatus as claimed in claim 32 wherein the interface circuit is coupled to the display device by a high speed serial interface.
34. The apparatus as claimed in claim 33 wherein the high speed serial interface is an IEEE 1394 serial bus network.
35. An apparatus for receiving on-screen-display graphics data generated by a source device and transmitted in isochronous data packets over an isochronous channel, each isochronous data packet including an address value corresponding to a memory location, comprising:
a. an interface circuit configured for coupling to the source device for receiving the isochronous data packets from the source device over the isochronous channel; b. a processing device coupled to the interface circuit for receiving the isochronous data packets and separating the address value from the on-screen-display graphics data; c. a memory device coupled to the processing device to store the on-screen-display graphics data in a memory location corresponding to the address value; and d. a display device coupled to the memory device for displaying the on-screen-display graphics at a display time, wherein the display time is received in a trigger packet. 36. The apparatus as claimed in claim 35 wherein the processing device is an embedded stream processor which determines if on-screen-display graphics data is included within the isochronous data packets, strips header information from the isochronous data packets, determines the address value and transmits the address value and the on-screen-display graphics data to the memory device.
37. The apparatus as claimed in claim 36 wherein the memory device includes a buffer and a DMA engine which receives the address value and stores the on-screen-display graphics data in the memory location corresponding to the address value within the buffer.
38. The apparatus as claimed in claim 37 wherein the display device includes a display and a VRAM circuit in which the on-screen-display graphics are stored before being displayed on the display.
39. The apparatus as claimed in claim 38 wherein the interface circuit is coupled to the source device by a high speed serial interface.
40. The apparatus as claimed in claim 39 wherein the high speed serial interface is an IEEE 1394 serial bus network.
41. A system for transmitting on-screen-display graphics data comprising:
a. a source device including: i. a graphics source for generating on-screen-display graphics to be displayed by a display device; and ii. a source interface circuit coupled to the graphics source and configured for coupling to the display device for combining the on-screen-display graphics into a stream of isochronous data packets each including an address value corresponding to a memory location within the display device and transmitting the isochronous data packets from the source device to the display device over an isochronous channel; and b. a display device including: i. a display interface circuit coupled to the source interface circuit for receiving the isochronous data packets from the source device over the isochronous channel; ii. a processing device coupled to the display interface circuit for receiving the isochronous data packets and separating the address value from the on-screen-display graphics data; iii. a memory device coupled to the processing device to store the on-screen-display graphics data in a memory location corresponding to the address value; and iv. a display device coupled to the memory device for displaying the on-screen-display graphics at a display time; wherein the graphics source also generates a trigger packet which is transmitted by the interface circuit on the occurrence of a trigger event, the trigger packet including a trigger address value corresponding to a trigger memory location within the display device.
42. The system as claimed in claim 41 wherein the trigger event occurs when all isochronous data packets for a screen of on-screen-display graphics have been transmitted from the source interface circuit.
43. The system as claimed in claim 42 wherein the trigger packet further includes a presentation time value specifying the display time for the screen of on-screen-display graphics.
44. The system as claimed in claim 43 wherein the trigger packet includes a trigger bit, which when written into the trigger memory location, signals that storage of a current frame of on-screen-display graphics data is complete.
45. The system as claimed in claim 44 wherein the trigger packet also includes an overlay bit specifying whether or not the on-screen-display graphics are to be combined with video data.
46. The system as claimed in claim 41 wherein the processing device is an embedded stream processor which determines if on-screen-display graphics data is included within the isochronous data packets, strips header information from the isochronous data packets, determines the address value and transmits the address value and the on-screen-display graphics data to the memory device.
47. The system as claimed in claim 46 wherein the memory device includes a buffer and a DMA engine which receives the address value and stores the on-screen-display graphics data in the memory location corresponding to the address value within the buffer.
48. The system as claimed in claim 47 wherein the display device includes a display and a VRAM circuit in which the on-screen-display graphics are stored before being displayed on the display.
49. The system as claimed in claim 48 wherein the source interface circuit is coupled to the display interface circuit by a high speed serial interface.
50. The system as claimed in claim 49 wherein the high speed serial interface is an IEEE 1394 serial bus.
RELATED APPLICATIONS This application claims priority under 35 U.S.C. �119(e) of the co-pending U.S. provisional application Serial No. 60,089,798 filed on Jun. 18, 1998 and entitled �A METHOD FOR HANDLING HIGH BANDWIDTH ON-SCREEN-DISPLAY (OSD) OVER A DISTRIBUTED 1394 NETWORK.� The provisional application Serial No. 60,089,798 filed on Jun. 18, 1998 and entitled �A METHOD FOR HANDLING HIGH BANDWIDTH ON-SCREEN-DISPLAY (OSD) OVER A DISTRIBUTED 1394 NETWORK� is also hereby incorporated by reference.
FIELD OF THE INVENTION The present invention relates to the field of displaying on-screen-display graphics data on a display device. More particularly, the present invention relates to the field of displaying on-screen-display graphics data provided from a source device on a display device.
A home audio/video interoperability (HAVi) architecture is defined by �The HAVi Architecture: Specification of the Home Audio/Video Interoperability (HAVi) Architecture,� draft version 0.8n13, Sep. 16, 1998. The HAVi architecture is to be implemented on consumer electronics devices and computing devices. The HAVi architecture provides a set of services which facilitate interoperability and the development of distributed applications on home networks. The HAVi architecture is designed for digital devices coupled together within an IEEE 1394-1995 serial bus network.
SUMMARY OF THE INVENTION On-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display device, as a stream of isochronous data, separate from video data. Each packet of isochronous data within the stream of on-screen-display graphics data includes an address value corresponding to a memory address within the display device forming a buffer. When received by the display device the on-screen-display graphics data is loaded into the appropriate memory locations within the buffer corresponding to the address values. At the display device, an embedded stream processor is utilized to strip the header information from each packet and determine the appropriate memory location that the data is to be stored. A trigger packet is sent at the end of the data stream for a screen of on-screen-display graphics. The trigger packet includes a presentation time value corresponding to a display time for the screen of on-screen-display graphics. When the trigger packet is received, the display device transfers the data stored in the buffer to a VRAM circuit for display at the specified presentation time. The on-screen-display graphics data can be overlaid on video data for display and also displayed separately. The trigger packet includes a trigger bit and an overlay bit. The trigger bit, when written, signals that the storage of the current frame is complete. The overlay bit specifies whether or not the current on-screen-display graphics data frame is to be overlaid on a video data frame. Differential encoding is used when transferring frames of data wherein only a portion of data changes from the previous frame.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An isochronous data format is utilized to transmit on-screen-display graphics from a source device to a display device. The on-screen-display graphics are generated by the source device, such as a VCR, and transmitted to a display device, as a stream of isochronous data, separate from non on-screen-display graphics data. Non on-screen-display graphics data includes other types of data such as video data, audio data and any other appropriate type of data sent from a source device to a display device. The source device preferably does not encode the on-screen-display graphics stream of data into a format such as MPEG. Alternatively, the on-screen-display graphics stream of data is mixed with another stream of data, such as video data, and encoded into a format such as MPEG. Each packet of isochronous data within the stream of on-screen-display graphics data includes an address value. When received by the display device the on-screen-display graphics data is loaded into an on-screen-display buffer at memory locations corresponding to the address values. At the display device, an embedded stream processor is preferably utilized to strip the header information from each packet and determine the appropriate memory location at which the data is to be stored. Alternatively, any other appropriate general or special purpose processing mechanism is used to strip the header information from each packet and determine the appropriate memory location at which the data is to be stored.
The preferred configuration of the on-screen-display graphics memory buffer 78 is illustrated in FIG. 4. The memory buffer 78 includes a number of memory storage locations 120-124 in which collectively a frame of data is stored. Each of the memory storage locations 120-124 is individually addressable. However, when writing to the memory buffer 78, after an address is specified, data is written to successively increasing addresses within the memory buffer 78 until a subsequent address value is provided. Preferably, the final storage location 126 within the memory buffer 78 stores the trigger packet which is used to time the display of data within the memory buffer 78. Alternatively, the trigger packet is stored within any other appropriate and designated trigger memory buffer or location.
In order to provide smooth, flicker-free screen updates, the VRAM circuit 64 within the television 60 is preferably partitioned into two parts, as illustrated in FIG. 5. The VRAM circuit 64 preferably includes two portions, the VRAM circuit 123 and the VRAM circuit 121. Each of the VRAM circuits 121 and 123 preferably have the capacity to store a frame worth of data. The controller 63, within the television 60, manages the switching between the VRAM circuits 121 and 123. The data for a frame is first transferred into the VRAM circuit 123. When the VRAM circuit 123 has a frame of data, then the controller 63 causes the next frame of data to be stored within the VRAM circuit 121. When one of the VRAM circuits 121 and 123 is full, the controller 63 causes the data within the VRAM circuit 121 or 123 to be displayed on the display 62, at the appropriate presentation time.
A preferred format of an isochronous data packet for transmitting on-screen-display graphics data over an IEEE 1394-1995 serial bus network is illustrated in FIG. 8. The format of the data packet also complies with the ISO/IEC 61883 standard. The isochronous data packet includes a packet header and a data field or payload. The isochronous packet header includes a data_length field, a tag field, a channel field, a tCode field, an sy field and a header_CRC field. The data_length field contains a value representing the number of bytes of data within the data field, including the number of bytes within a CIP (common isochronous packet) header included in the packet. The tag field provides a high level label for the format of data carried by the isochronous packet. The channel field contains the channel number on which the isochronous packet is transmitted. The tCode field contains a transaction code for the packet. For isochronous data packets, the tCode field contains either a value of Ah or Ch. The sy field contains a synchronization flag used in some applications to synchronize the data in the current isochronous packet with some application specific event.
A format of the data field of the isochronous packet used to transmit on-screen-display graphics according to the present invention is illustrated in FIG. 9. The data field includes an extended CIP header and a data portion. The extended CIP header includes an end of header bit within each quadlet and a form bit within the two most significant bits of each quadlet. In the preferred format of the extended CIP header, the end of header bit is not set to a logical �1� until the fourth and last quadlet within the extended CIP header. When the end of header bit has a value of logical �1,� this signals that the current quadlet is the last quadlet within the CIP header. Within the CIP header, the SID field contains the source node ID value of the transmitting node. The DBS field contains a value representing the size of the data block in quadlets. The FN field contains a fraction number representing the number of data blocks into which a source packet is divided. The QPC field contains a value representing the number of dummy quadlets added to a source packet to equalize the size of the divided data blocks. If the FN field indicates that the source packet is not divided, then the QPC field will contain a value equal to zero. The SPH flag represents whether or not the source packet includes a source packet header. The SPH flag is set equal to a logical �one� when the source packet does include a source packet header. The rsv field is reserved for future extension. The DBC field is the continuity counter of data blocks to detect a loss of data blocks. The FMT field includes a format identifier which identifies the format of the packet. The FDF field is a format dependent field and depends on the format of the packet. The SYT field is used to synchronize the transmitter and the receiver. The OSD_buffer_address field contains the address to which the on-screen-display graphics data contained within the isochronous packet is to be stored within the on-screen-display graphics data buffer 78. The remaining data portion contains the actual on-screen-display graphics data payload within the isochronous packet.
A trigger packet is preferably an isochronous data packet and has the same format as illustrated in FIG. 8. The data field however is different than the data field for an on-screen-display graphics data packet as illustrated in FIG. 9. The preferred format of a data field for a trigger packet is illustrated in FIG. 10. The format of the extended CIP header portion of the data field is the same as the format illustrated in FIG. 9, and discussed above. The OSD_buffer_address field contains the value representing the address to which the trigger packet is to be written. Within the data payload, the trigger packet preferably includes three quadlets. The first quadlet includes a trigger bit t as the most significant bit, which is set to a value of logical �1� for a trigger packet. The second-most significant bit of the first quadlet within the trigger packet is an overlay bit o. The overlay bit o specifies whether or not the current on-screen-display graphics data frame is to be overlaid on a video data frame. The second and third quadlets within the trigger packet include the presentation_time field which preferably contains a sixty-four bit value representing a time value at which the current frame of on-screen-display graphics data is to be displayed. A presentation_time value of all logical �0�s specifies an immediate presentation time.
The preferred embodiment of the embedded stream processors 84 and 109 are taught in U.S. patent application Ser. No. 08/612,322, filed on Mar. 7, 1996 and entitled �ISOCHRONOUS DATA PIPE FOR MANAGING AND MANIPULATING A HIGH-SPEED STREAM OF ISOCHRONOUS DATA FLOWING BETWEEN AN APPLICATION AND A BUS STRUCTURE,� which is hereby incorporated by reference. The embedded stream processor 84 is programmable and will execute a series of instructions on a stream of data in order to perform operations and manipulations on the data as required to place the data in the appropriate format. Within the present invention, the embedded stream processor 84 receives the isochronous packets containing on-screen-display graphics data, strips the header from the packet, forwards the on-screen-display graphics data payload of the packet to the decompression circuit 76 and forwards the addressing information to the DMA engine 77. Within the present invention, the embedded stream processor 109 receives data from the video source 106 and the graphics source 108, attaches a header to the packets and forwards the packets to the IEEE 1394 interface circuit 102. It should be apparent to those skilled in the art that alternatively, any mechanism with appropriate processing capability can be used in place of the embedded stream processors 84 and 109.
The source packets containing compressed data are then combined into isochronous packets, including an isochronous packet header and a CIP header, by the embedded stream processor 109, at the step 212, and provided to the interface circuit 102. An illustration of a data stream of source packets being combined into isochronous data packets is shown in FIG. 14. Each of the source packets 160-172 include a source packet header and a data payload. A number of source packets are combined into an isochronous data packet. In the illustration shown in FIG. 14, the source packets 160, 162 and 164 are combined into the isochronous data packet 174 and the source packets 166, 168 and 170 are combined into the isochronous data packet 176. Each of the isochronous data packets include an isochronous packet header and a CIP header, as described above.
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46 Verified Hotel Reviews of Waldhotel Forsthaus Dröschkau | Booking.com
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Reviews of Waldhotel Forsthaus Dröschkau
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“Bring your own survivial food to stay at the Twilight Zone.”
눉Returned to property at 18:30 to find office LOCKED and restaurant closed on Saturday night. Difficult to get to room until someone told me that our keys worked in one door in back of hotel. Never saw any staff members again after check-in AND had NO DINNER. No other restaurants for many kilometers. The property signs outside stated "restaurant open until 20:30" but it was closed before 18:30, lights out. Next morning, more of same: NO staff present at 07:30 Sunday and NO BREAKFAST. No one to assist in checkout at 07:30, so I left the key in room and departed.
눇Early check-in allowed at 13:00 to meet my scheduled appointment in Belgern.
눇the receptionist, the girl with the blond hair. She is so sweet and helpfull!
533337,587067|1,598117,581907,587067,581897,600087,578107,601637,576247,595967,587067|2

value: This website is a Dutch online travel agency for lodging reservations & other travel products, and a subsidiary of Booking Holdings. It is headquartered in Amsterdam.The website has over 28 million listings.


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Words that start with contributorie | Words starting with contributorie
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Words that start with contributorie
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