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Patent US20010010092 - Semiconductor integrated circuit with a reduced skew and layout method in ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsThe present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the...http://www.google.com/patents/US20010010092?utm_source=gb-gplus-sharePatent US20010010092 - Semiconductor integrated circuit with a reduced skew and layout method in design for semiconductor integrated circuitAdvanced Patent SearchPublication numberUS20010010092 A1Publication typeApplicationApplication numberUS 09/764,295Publication dateJul 26, 2001Filing dateJan 19, 2001Priority dateJan 20, 2000Also published asDE10102141A1, DE10102141C2, US6543042Publication number09764295, 764295, US 2001/0010092 A1, US 2001/010092 A1, US 20010010092 A1, US 20010010092A1, US 2001010092 A1, US 2001010092A1, US-A1-20010010092, US-A1-2001010092, US2001/0010092A1, US2001/010092A1, US20010010092 A1, US20010010092A1, US2001010092 A1, US2001010092A1InventorsAkitoshi KatoOriginal AssigneeNec CorporationExport CitationBiBTeX, EndNote, RefManReferenced by (15), Classifications (10), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor integrated circuit with a reduced skew and layout method in design for semiconductor integrated circuitUS 20010010092 A1Abstract The present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. Images(12) Claims(33)
What is claimed is: 1. A layout method in design for a semiconductor integrated circuit having clock tree paths, said method comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. 2. The method as claimed in claim 1 , wherein the substitutional delay flip-flop circuits are extracted from a delay flip-flop library. 3. The method as claimed in claim 1 , wherein a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value. 4. The method as claimed in claim 3 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 5. The method as claimed in claim 4 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 6. The method as claimed in claim 1 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. 7. A layout method in design for a semiconductor integrated circuit having clock tree paths, said method comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than: the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. 8. The method as claimed in claim 7 , wherein the delay circuits are extracted from a delay circuit library. 9. The method as claimed in claim 7 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. 10. The method as claimed in claim 9 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 11. The method as claimed in claim 10 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 12. The method as claimed in claim 1 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. 13. A computer program for layout processes in design for a semiconductor integrated circuit having clock tree paths, said computer program comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. 14. The computer program as claimed in claim 13 , wherein the substitutional delay flip-flop circuits are extracted from a delay flip-flop library. 15. The computer program as claimed in claim 13 , wherein a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value. 16. The computer program as claimed in claim 15 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 17. The computer program as claimed in claim 16 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 18. The computer program as claimed in claim 13 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. 19. A computer program for layout processes in design for a semiconductor integrated circuit having clock free paths, said computer program comprising the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. 20. The computer program as claimed in claim 19 , wherein the delay circuits are extracted from a delay circuit library. 21. The computer program as claimed in claim 19 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. 22. The computer program as claimed in claim 21 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 23. The computer program as claimed in claim 22 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 24. The computer program as claimed in claim 19 , further comprising the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. 25. A semiconductor integrated circuit having a common clock input terminal, plural Slip-flop circuits, and clock tree paths extending from the common clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of the clock tree paths, and second type flip-flop circuits having a delay which compensates a difference between the average delay value and the maximum value. 26. The semiconductor integrated circuit as claimed in claim 25 , wherein the second type flip-flop circuit comprises a flip-flop circuit configuration only, and the second type flip-flop circuit comprises both the flip-flop circuit configuration and a delay circuit configuration provided on a previous stage of the flip-flop circuit configuration. 27. The semiconductor integrated circuit as claimed in claim 25 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. 28. The semiconductor integrated circuit as claimed in claim 27 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 29. The semiconductor integrated circuit as claimed in claim 28 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. 30. A semiconductor integrated circuit having a common clock input terminal, plural flip-flop circuits, and clock tree paths extending from the common clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a first range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of the clock tree paths, and second type flip-flop circuits having delay values in a second range between the average delay value and a minimum value of the individual delay values of all of the clock tree paths, and wherein delay circuits having a delay which compensates a difference between the average delay value and the maximum value are provided on previous stages of the second type flip-flop circuits. 31. The semiconductor integrated circuit as claimed in claim 30 , wherein a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. 32. The semiconductor integrated circuit as claimed in claim 31 , wherein the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. 33. The semiconductor integrated circuit as claimed in claim 32 , wherein the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. Description
BACKGROUND OF THE INVENTION [0001] The present invention relates to a semiconductor integrated circuit with a reduced clock skew and a layout method in design of a semiconductor integrated circuit with a reduced clock skew. [0002] In recent years, semiconductor integrated circuits have been on the improvements in high density integration, large scale integration and high speed performances. It is necessary that the high density integration of the semiconductor integrated circuits is realized, whist a clock skew which may cause a hold defective is reduced to improve the reliability of the semiconductor integrated circuit. [0003] As the high density integration has been progressed with change of the design rules from 0.25 micrometers-rule through 0.18 micrometers-rule to 0.13 micrometers-rule, a difference between a maximum value and a minimum value of an interconnection delay becomes remarkable, whereby a phase difference of the clock signals, for example, a clock skew is increased. If the phase difference of the clock signals or the clock skew becomes larger than a holding value of a flip-flop circuit, then a holding defective appears on the flip-flop circuits. [0004]FIG. 1 is a circuit diagram illustrative of first and second flip-flop circuits provided in a semiconductor integrated circuit to explain a holding defective of the flip-flop circuits. If a clock signal delay �N� becomes lower than a sum of a delay value �L�, a first internal delay value of a first flip-flop circuit F/F1, a delay value �M�, and a second internal delay value of a second flip-flop circuit F/F2, then the holding defective appears. [0005] The clock skew value as the difference in delay of the clock signals is presumable but only after the layout and placement have been completed. For this reason, it is possible that after an automatic layout has been completed, the clock skew value is increased to cause the holding defective on the flip-flop circuit, whereby a malfunction of the flip-flop circuit may appear. [0006] The following has been proposed to have solved the above problem. On the basis of delay informations after the automatic layout has been completed, then change of the circuit configuration, re-study and re-execution of the automatic layout are repeated until the clock skew is reduced. [0007]FIG. 2 is a flow chart illustrative of a first conventional circuit design method. [0008] In a step S81, the process is started. [0009] In a step S82, a circuit design is carried out to form a net-list. [0010] In a step S83, layout and placement of cells are executed by use of the net-list to form real interconnection data. [0011] In a step S84, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library. [0012] In a step S85, a circuit design operation is confirmed and further a timing and the clock skew value are also confirmed. [0013] In a step S86, it is verified whether or not any delay adjustment is needed. If the delay adjustment is needed, then the process will back to the step S82 for changing the circuit design or the step S83 for changing the cell layout. Those automatic layout processes will be repeated until the delay adjustment is not needed. If the delay adjustment is not needed, then the process is ended in a step S87. [0014] In Japanese laid-open patent publication No. 10-327047, a second conventional technique is disclosed. A data input terminal or a data output terminal of a flip-flop circuit is coupled with a logic cell having a flip-flop circuit and being free of any delay circuit. Subsequently, a logic simulation is executed on the basis of the layout information. A timing information as the result of the logic simulation is investigated with reference to a design specification of the semiconductor integrated circuit to verify a possibility of malfunction due to the timing variation. The logic cell is replaced by another logic cell which has a delay circuit, so that the logic cell with the delay circuit is connected to the data input or output terminal of the flip-flop circuit. [0015] It is considered that the clock signal is supplied from the common clock input terminal to the plural flip-flop circuits. A clock tree system causes that the number of the buffer circuits between the individual flip-flop circuits and the common clock input terminal becomes the same, whereby the clock skew value is reduced. [0016] In this case, however, it is necessary, to compensate the delay amount. A second conventional technique has been proposed. FIG. 3 is a flow chart illustrative of a second conventional circuit design method. [0017] In a step S91, the process is started. [0018] In a step S92, a circuit design is executed to form a let-list. [0019] In a step S93, layout and placement of cells are executed by use of the net-list to form real interconnection data. [0020] In a step S94, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library. [0021] In a step S95, on the basis of the post-layout delay information and the clock skew value, a delay value of all paths of the clock-tree is extracted. [0022] In a step S96, on the basis of the delay value of all paths of the clock-tree, a difference between the delay value of all paths of the clock-tree and a maximum value is calculated. [0023] In a step S97, a delay circuit, which compensates to the calculated difference between the delay value of all paths of the clock-tree and the maximum value, is selected from a delay circuit library and the delay circuit is inserted into a logic cell to form a delay circuit cell. [0024] In a step S98, a layout of tie delay circuit cell is executed to form real interconnection data. [0025] In a step S99, on the basis of the real interconnection data and a previously prepared delay circuit library, a delay information and a clock skew value are re-prepared to complete the circuit design process in a step S100. [0026] The above first and second conventional circuit layout methods prepare individual logic cell libraries for individual paths to verify the individual delays, whereby a design turnaround time is long. [0027] In case of the above clock tree shown in FIG. 3, the individual delay circuits, which compensate the difference between the delay value of all circuits of the clock tree and the maximum value, is inserted into the logic cell connected to the data input or output terminal of the flip-flop circuit. There are a large number of inserting positions into which the delay circuits are inserted. In case, a layout correction is difficult. As another method, it is possible to increase the length of the interconnections so that the fast path is adjusted to a delay path. This method is, however, unavailable to the high density interconnection region. [0028] In the above circumstances, it had been required to develop a novel layout method in design of a semiconductor integrated circuit free from the above problem. SUMMARY OF THE INVENTION [0029] Accordingly, it is an object of the present invention to provide a novel layout method in design of a semiconductor integrated circuit free from the above problems. [0030] It is a further object of the present invention to provide a novel layout method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit. [0031] It is a still further object of the present invention to provide a novel method in design of a semiconductor integrated circuit to reduce a clock skew to a half of a maximum clock skew value for increasing a design efficiency and shortening a turnaround time. [0032] It is yet a further object of the present invention to provide a novel semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit. [0033] The present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0034] The present invention also provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0035] The above and other objects, features and advantages of the present invention will be apparent from the following descriptions. BRIEF DESCRIPTION OF THE DRAWINGS [0036] Preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings [0037]FIG. 1 is a circuit diagram illustrative of first and second flip-flop circuits provided in a semiconductor integrated circuit to explain a holding defective of the flip-flop circuits. [0038]FIG. 2 is a flow chart illustrative of a first conventional circuit design method. [0039]FIG. 3 is a flow chart illustrative of a second conventional circuit design method. [0040]FIG. 4 is a flow hart illustrative of a first novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a first embodiment in accordance with the present invention. [0041]FIG. 5 is a diagram illustrative of a distribution of a delay value of clock tree paths to extracted flip-flop circuits in a first embodiment in a Accordance with the present invention. [0042]FIG. 6 is a block diagram illustrative of an extracted clock tree in a first novel design method in a first embodiment in accordance with the present invention. [0043]FIG. 7 is a block diagram illustrative of a substituted clock tree in a first novel design method in a first embodiment in accordance with the present invention. [0044]FIG. 8 is a circuit diagram illustrative of a substituted delay flip-flop circuit in FIG. 7. [0045]FIG. 9 is a diagram illustrative of a distribution of a delay value of clock tree paths to the substituted delay flip-flop circuits in a first embodiment in accordance with the present invention. [0046]FIG. 10 is a flow hart illustrative of a second novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a second embodiment in accordance with the present invention. [0047]FIG. 11 is a block diagram illustrative of a batch-processed clock tree in a second novel design method in a second embodiment in accordance with the present invention. [0048]FIG. 12 is a circuit diagram illustrative of a delay circuit in FIG. 11. DISCLOSURE OF THE INVENTION [0049] The first present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0050] It is preferable that the substitutional delay flip-flop circuits are extracted from a delay flip-flop library. [0051] It is preferable that a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value. [0052] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0053] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. [0054] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. [0055] The second present invention provides a layout method in design for a semiconductor integrated circuit having clock tree paths. The method comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0056] It is preferable that the delay circuits are extracted from a delay circuit library. [0057] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. [0058] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0059] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. [0060] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted, flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. [0061] The third present invention provides a computer program for layout processes in design for a semiconductor integrated circuit having clock tree paths. The computer program comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-substituting process for batch-substituting all of the extracted flip-flop circuits by substitutional delay flip-flop circuits which have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0062] It is preferable that the substitutional delay flip-flop circuits are extracted from a delay flip-flop library. [0063] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-substituting process is limited within a range between the average delay value and the maximum delay value. [0064] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0065] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. [0066] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the substitutional delay flip-flop circuits to prepare real interconnection data; and preparing a delay information and a skew value on the basis of both the read interconnection data and a previously prepared delay library. [0067] The fourth present invention provides a computer program for layout processes in design for a semiconductor integrated circuit having clock tree paths. The computer program comprises the steps of: extracting delay values of all of the clock tree paths; calculating an average delay value from the extracted delay values; comparing each of the delay values of the clock tree paths to the average delay value for extracting flip-flop circuits connected to the clock tree paths which have delay values smaller than the average delay value; and carrying out a batch-inserting process for batch-inserting delay circuits onto previous stages of all of the extracted flip-flop circuits, and the delay circuits have a delay compensating a difference between the average delay value and a maximum value of the delay values of all of the clock tree paths. [0068] It is further preferable that the delay circuits are extracted from a delay circuit library. [0069] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. [0070] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0071] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. [0072] It is preferable to further comprise the step of: carrying out a layout process for cells including the extracted flip-flop circuits and the delay circuits to prepare real interconnection data; and preparing a delay information and a skew value on: the basis of both the read interconnection data and a previously prepared delay library. [0073] The fifth present invention provides a semiconductor integrated circuit having a common clock input terminal, plural flip-flop circuits, and clock tree paths extending from the common Clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of; the clock tree paths, and second type flip-flop circuits having a delay which compensates a difference between the average delay value and the maximum value. [0074] It is preferable that the second type flip-flop circuit comprises a flip-flop circuit configuration only, and the second type flip-flop circuit comprises both the flip-flop circuit configuration and a delay circuit configuration provided on a previous stage of the flip-flop circuit configuration. [0075] It is also preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. [0076] It is further preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0077] It is further more preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. [0078] The sixth present invention provides a semiconductor integrated circuit having a common clock input terminal, plural flip-flop circuits, and clock tree paths extending from the common clock input terminal to the flip-flop circuits, wherein the flip-flop circuits are classified into first type flip-flop circuits having delay values in a first range between an average delay value of individual delay values of the clock tree paths and a maximum value of the individual delay values of all of the clock tree paths, and second type flip-flop circuits having delay values in a second range between the average delay value and a minimum value of the individual delay values of all of the clock tree paths, and wherein delay circuits having a delay which compensates a difference between the average delay value and the maximum value are provided on previous stages of the second type flip-flop circuits. [0079] It is preferable that a distribution in the number of the clock tree paths over delay value after the batch-inserting process is limited within a range between the average delay value and the maximum delay value. [0080] It is also preferable that the number of the clock tree paths is higher in the vicinity of the average delay value and the maximum delay value than at an intermediate delay value between the average delay value and the maximum delay value. [0081] It is further preferable that the distribution in the number of the clock tree paths over delay value is substantially symmetrical with reference to the intermediate delay value between the average delay value and the maximum delay value. PREFERRED EMBODIMENT FIRST EMBODIMENT [0082] A first embodiment according to the present invention will be described in detail with reference to the drawings. FIG. 4 is a flow hart illustrative of a first novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a first embodiment in accordance with the present invention. [0083] In a step S11, the process is started. [0084] In a step S12, a circuit design is executed to form a let-list. [0085] In a step S13, layout and placement of cells are executed by use of the net-list to form real interconnection data. [0086] In a step S14, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library. [0087] In a step S15, on the basis of the post-layout delay information and the clock skew value, a delay value of all paths of the clock-tree is extracted. [0088] In a step S16, on the basis of the delay values of all paths of the clock-tree, an average of the delay values is calculated. [0089] In a step S17, it is verified whether or not the calculated average is within an acceptable range which has previously been set, wherein the acceptable range has a range center which corresponds to an intermediate value between the maximum and minimum values of the delay values. FIG. 5 is a diagram illustrative of a distribution of a delay value of clock tree paths to extracted flip-flop circuits in a first embodiment in accordance with the present invention. The distribution of the delay value of the clock tree paths is symmetrical with reference to the average value �C� which is intermediate between the maximum and minimum delay values. It is preferable that the distribution of the delay value of the clock tree paths is the normal distribution, wherein the average value corresponds to the center of the acceptable range. If the calculated average is within the acceptable range, then the calculated average is not so different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is almost symmetrical with reference to the center of the maximum and minimum delay values. In this case, the following batch process is carried out. If the calculated average is out the acceptable range, then the calculated average is largely different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is largely asymmetrical with reference to the center of the maximum and minimum delay values. In this case, individual processes are executed in place of the batch-process. [0090] In a step S18, if the calculated average is within the acceptable range, then each of the extracted individual delay values of the individual clock tree paths is compared to the calculated average value. [0091] In a step S19, clock tree paths faster than the average value are extracted. [0092]FIG. 6 is a block diagram illustrative of an extracted clock tree in a first novel design method in a first embodiment in accordance with the present invention. A clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three flip-flop circuits 41. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three flip-flop circuits 42. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three flip-flop circuits 43. The clock signal is furthermore transmitted from the seventh buffer circuit 57 through a tree path 64 to three flip-flop circuits 44. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 6, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 to the three flip-flop circuits 41. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 to the three flip-flop circuits 42. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 to the three flip-flop circuits 43. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 to the three flip-flop circuits 44. Whereas the four clock tree paths are faster than the average delay value, it is probable that six clock tree paths are extracted as faster than the average value in cause of the twelve flip-flop circuits. [0093] In a step S20, a batch-replacing process is carried out, wherein the flip-flop circuits coupled to the clock tree paths faster in delay value than the average value are substituted with substitute flip-flop circuits with delays which compensate to a difference between the average value and the maximum value. The substitute delay flip-flop circuits are selected from a previously prepared delay flip-flop circuit library. [0094]FIG. 7 is a block diagram illustrative of a substituted clock tree in a first novel design method in a first embodiment in accordance with the present invention. A clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three substituted delay flip-flop circuits 41A. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three substituted delay flip-flop circuits 42A. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three substituted delay flip-flop circuits 43A. The clock signal is furthermore transmitted from the seventh buffer circuit 57 through a tree path 64 to three substituted delay flip-flop circuits 44A. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 7, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 to the three substituted delay flip-flop circuits 41A. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 to the three substituted delay flip-flop circuits 42A. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 to the three substituted delay flip-flop circuits 43A. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 to the three substituted delay flip-flop circuits 44A. The three substituted delay flip-flop circuits 41A, the three substituted delay flip-flop circuits 42A, the three substituted delay flip-flop circuits 43A, and the three substituted delay flip-flop circuits 44A are the same as each other in delay amount. Each of the three substituted delay flip-flop circuits 41A, the three substituted delay flip-flop circuits 42A, the three substituted delay flip-flop circuits 43A, and the three substituted delay flip-flop circuits 44A has the same circuit configuration. FIG. 8 is a circuit diagram illustrative of a substituted delay flip-flop circuit in FIG. 7. Each of the substituted delay flip-flop circuits 41A, 42A, 43A and 44A comprises a flip-flop circuit region and a delay circuit region, wherein the flip-flop circuit region comprises series connections of plural flip-flop circuits and the delay circuit region comprises series connections of plural delay circuits. Each of the flip-flop circuits comprises a pair of first and second inverter circuits, wherein an input terminal of the first inverter circuit is connected to an output terminal of the second inverter circuit, and further an output terminal of the first inverter Circuit is connected to an input terminal of the second inverter circuit. Each of the delay circuits comprises a pair of an inverter circuit and a capacitance, wherein the capacitance is connected between an output terminal of the inverter and a ground line. The series connection of the plural delay circuits is provided on the pre-stage of the series connection of the flip-flop circuit. [0095]FIG. 9 is a diagram illustrative of a distribution of a delay value of clock tree paths to the substituted delay flip-flop circuits in a first embodiment in accordance with the present invention. The delay value is limited between the maximum value and the average value, wherein the variation in delay values is reduced. Namely, the clock skew value is reduced to a half. This �-reduced clock skew value is in the acceptable delay value range, wherein no malfunction appears on the flip-flop circuits. For this reason, in the acceptable range, the number of the paths is larger at both ends, for example, just over the average value and just under the maximum value than the center of the acceptable range, for example, intermediate between the average value and the maximum value as well shown in FIG. 9, whereby a possible uniform distribution can be obtained. [0096] In a step S21, layout of the substitute delay flip-flop circuit cells is carried out to prepare real interconnection data. [0097] In a step S22, on the basis of the real interconnection data and a previously prepared delay circuit library, a delay information and a clock skew value are re-prepared to complete the circuit design process in a step S23. [0098] As described above, in accordance with the first novel method of the present invention, clock tree paths faster in delay value than the average delay value are extracted. A batch-substitution process is carried out for batch-substituting all flip-flop circuits connected to the extracted clock tree paths into substitute delay flip-flop circuits which have a delay compensating a difference between the average value of the delay values and a maximum value of the delay values to reduce the clock skew value into a half. The batch-substitution process results in a reduction in the number of the processes for obtaining the reduced clock skew. SECOND EMBODIMENT [0099] A second embodiment according to the present invention will be described in detail with reference to the drawings. FIG. 10 is a flow hart illustrative of a second novel method in design of a semiconductor integrated circuit with a reduced clock skew to increase a design efficiency and shorten a turnaround time without providing any substantive influence to the semiconductor integrated circuit in a second embodiment in accordance with the present invention. [0100] In a step S11, the process is started. [0101] In a step S12, a circuit design is executed to form a let-list. [0102] In a step S13, layout and placement of cells are executed by use of the net-list to form real interconnection data. [0103] In a step S14, a post-layout delay information and a clock skew value are prepared on the basis of the real interconnection data and a previously prepared delay library. [0104] In a step S15, on the basis of the post-layout delay information and the clock skew value, a delay value of all paths of the clock-tree is extracted. [0105] In a step S16, on the basis of the delay values of all paths of the clock-tree, an average of the delay values is calculated. [0106] In a step S17, it is verified whether or not the calculated average is within an acceptable range which has previously been set, wherein the acceptable range has a range center which corresponds to an intermediate value between the maximum and minimum values of the delay values. As shown in FIG. 5, the distribution of the delay value of the clock tree paths is symmetrical with reference to the average value �C� which is intermediate between the maximum and minimum delay values. It is preferable that the distribution of the delay value of the clock tree paths is the normal distribution, wherein the average value corresponds to the center of the acceptable range. If the calculated average is within the acceptable range, then the calculated average is not so different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is almost symmetrical with reference to the center of the maximum and minimum delay values. In this case, the following batch process is carried out. If the calculated average is out the acceptable range, then the calculated average is largely different from the center of the maximum and minimum delay values. This means that the distribution of the delay value of the clock tree paths is largely asymmetrical with reference to the center of the maximum and minimum delay values. In this case, individual processes are executed in place of the batch-process. [0107] In a step S18, if the calculated average is within the acceptable range, then each of the extracted individual delay values of the individual clock tree paths is compared to the calculated average value. [0108] In a step S19, clock tree paths faster than the average value are extracted. [0109] As shown in FIG. 6, a clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three flip-flop circuits 41. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three flip-flop circuits 42. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three flip-flop circuits 43. The clock signal is furthermore transmitted from the seventh buffer, circuit 57 through a tree path 64 to three flip-flop circuits 44. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 6, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 to the three flip-flop circuits 41. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 to the three flip-flop circuits 42. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 to the three flip-flop circuits 43. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 to the three flip-flop circuits 44. Whereas the four clock tree paths are faster than the average delay value, it is probable that six clock tree paths are extracted as faster than the average value in cause of the twelve flip-flop circuits. [0110] In a step S30, a batch-insertion process is carried out, so that insertion delay circuits are inserted onto previous stages of the flip-flop circuits coupled to the clock tree paths faster in delay value than the average value, wherein the insertion delay circuits have a delay which compensates to a difference between the average value and the maximum value. The insertion delay circuits are selected from a previously prepared delay circuit library. [0111]FIG. 11 is a block diagram illustrative Of a batch-processed clock tree in a second novel design method in a second embodiment in accordance with the present invention. A clock signal is generated by a clock generator circuit 58. The clock signal is then inputted into a common clock input terminal 59 of a first buffer circuit 51. The clock signal is then transmitted from the first buffer circuit 51 to second and third buffer circuits 52 and 53. The clock signal is further transmitted from the second buffer circuit 52 to fourth and fifth buffer circuits 54 and 55. The clock signal is further transmitted from the third buffer circuit 53 to sixth and seventh buffer circuits 56 and 57. The clock signal is furthermore transmitted from the fourth buffer circuit 54 through a tree path 61 to three flip-flop circuits 41A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 41A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 41A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The clock signal is furthermore transmitted from the fifth buffer circuit 55 through a tree path 62 to three extracted flip-flop circuits 42A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 42A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 42A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The clock signal is furthermore transmitted from the sixth buffer circuit 56 through a tree path 63 to three extracted flip-flop circuits 43A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 43A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 43A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The clock signal is furthermore transmitted from the seventh buffer circuit 57 through a tree path 64 to three extracted flip-flop circuits 44A, wherein a delay circuit 40 is provided on a previous stage of one of the three flip-flop circuits 44A. The delay circuit 40 is connected to a clock terminal of the flip-flop circuit 44A. The delay circuit 40 has a delay which compensates a difference between the average delay value and the maximum delay value. The above tree paths 61, 62, 63 and 64 are extracted as the faster clock tree paths than the average value. As shown in FIG. 11, the tree path 61 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 54 and the delay circuit 40 to the three extracted flip-flop circuits 41A. The tree path 62 extends from the common clock input terminal 59 through the buffer circuits 51, 52, and 55 and the delay circuit 40 to the three extracted flip-flop circuits 42A. The tree path 63 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 56 and the delay circuit 40 to the three extracted flip-flop circuits 43A. The tree path 64 extends from the common clock input terminal 59 through the buffer circuits 51, 53, and 57 and the delay circuit 40 to the three extracted flip-flop circuits 44A. The delay circuits 40 are the same as each other in delay amount. Each of the delay circuits 40 has the same circuit configuration. FIG. 12 is a circuit diagram illustrative of a delay circuit in FIG. 11. Each of the delay circuits 40 comprises series connections of plural pairs of inverters and capacitors, wherein the capacitor is connected between an output terminal of the inverter and a ground line. The series connection of the plural sets of the inverters and capacitors is provided on the pre-stage of the flip-flop circuit. [0112] As shown in FIG. 9, the delay value is limited between the maximum value and the average value, wherein the variation in delay values is reduced. Namely, the clock skew value is reduced to a half. This �-reduced clock skew value is in the acceptable delay value range, wherein no malfunction appears on the flip-flop circuits. For this reason, in the acceptable range, the number of the paths is larger at both ends, for example, just over the average value and just under the maximum value than the center of the acceptable range, for example, intermediate between the average value and the maximum value as well shown in FIG. 9, whereby a possible uniform distribution can be obtained. [0113] In a step S31, layout of the flip-flop circuit cells is carried out to prepare real interconnection data. [0114] In a step S32, on the basis of the real interconnection data and a previously prepared delay circuit library, a delay information and a clock skew value are re-prepared to complete the circuit design process in a step S33. [0115] As described above, in accordance with the second novel method of the present invention, clock tree paths faster in delay value than the average delay value are extracted. A batch-insertion process is carried out for batch-inserting, inserting delay circuits onto a previous stage of all of flip-flop circuits connected to the extracted clock tree paths, wherein the inserting delay circuits have a delay compensating a difference between the average value of the delay values and a maximum value of the delay values to reduce the clock skew value into a half. The batch-insertion process results in a reduction in the number of the processes for obtaining the reduced clock skew. [0116] Whereas modifications of the present invention will be apparent to a person having ordinary skill in the art, to which the invention pertains, it is to be understood that embodiments as shown and described by way of illustrations are by no means intended to be considered in a limiting sense. Accordingly, it is to be intended to cover by claims all modifications which fall within the spirit and scope of the present invention. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6550045 *Nov 20, 2001Apr 15, 2003Lsi Logic CorporationChanging clock delays in an integrated circuit for skew optimizationUS6557152 *Oct 19, 2000Apr 29, 2003Nec Electronics CorporationMethod of designing signal distribution circuit and system for supporting the sameUS6698006 *Dec 14, 2001Feb 24, 2004Sequence Design, Inc.Method for balanced-delay clock tree insertionUS6782519 *Aug 29, 2002Aug 24, 2004Cadence Design Systems, Inc.Clock tree synthesis for mixed domain clocksUS6800633Dec 1, 2000Oct 5, 2004Osi Pharmaceuticals, Inc.Pyrrolo[2,3d]pyrimidine compositions and their useUS6944840 *Feb 13, 2002Sep 13, 2005Hitachi, Ltd.Design method and system for achieving a minimum machine cycle for semiconductor integrated circuitsUS7302657 *Sep 26, 2002Nov 27, 2007Telefonaktiebolaget L M Ericsson (Publ)Optimization of the design of a synchronous digital circuitUS7818705 *Apr 8, 2005Oct 19, 2010Altera CorporationMethod and apparatus for implementing a field programmable gate array architecture with programmable clock skewUS8640067Sep 17, 2010Jan 28, 2014Altera CorporationMethod and apparatus for implementing a field programmable gate array clock skewUS20130145331 *Oct 31, 2012Jun 6, 2013Synopsys, Inc.Sequential sizing in physical synthesisEP1308862A1 *Oct 29, 2001May 7, 2003Telefonaktiebolaget Lm EricssonOptimization of the design of a synchronous digital circuitEP1456784A1 *Dec 13, 2002Sep 15, 2004Cadence Design Systems, Inc.Clock tree synthesis for mixed domain clocksEP2040381A1 *Jul 25, 2007Mar 25, 2009Panasonic CorporationSemiconductor integrated circuit and layout technique thereofWO2003038687A2 *Sep 26, 2002May 8, 2003Ericsson Telefon Ab L MOptimization of the design of a synchronous digital circuitWO2003052643A1 *Dec 13, 2002Jun 26, 2003Silicon Perspective CorpClock tree synthesis for mixed domain clocks* Cited by examinerClassifications U.S. Classification716/113International ClassificationH01L21/82, H01L21/822, H01L27/04, G06F1/10, G06F17/50Cooperative ClassificationG06F17/5045, G06F1/10European ClassificationG06F1/10, G06F17/50DLegal EventsDateCodeEventDescriptionMay 29, 2007FPExpired due to failure to pay maintenance feeEffective date: 20070401Apr 1, 2007LAPSLapse for failure to pay maintenance feesOct 19, 2006REMIMaintenance fee reminder mailedMar 27, 2003ASAssignmentOwner name: NEC ELECTRONICS CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013892/0309Effective date: 20021101Owner name: NEC ELECTRONICS CORPORATION 1753 SHIMONUMABE NAKAHFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION /AR;REEL/FRAME:013892/0309Jan 19, 2001ASAssignmentOwner name: NEC CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KATO, AKITOSHI;REEL/FRAME:011479/0681Effective date: 20010116Owner name: NEC CORPORATION MINATO-KU 7-1, SHIBA 5-CHOME TOKYOOwner name: NEC CORPORATION MINATO-KU 7-1, SHIBA 5-CHOMETOKYO,Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KATO, AKITOSHI /AR;REEL/FRAME:011479/0681RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google

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Euro & American Motors3060 Middlefield RdRedwood City, CA 94063(650) 368-53540.7 milesAuto Repair & ServiceNew Car DealersWebsiteAdd to mybookRemove from mybookAdded to your car collection!Error when adding to car collectionThis business was removed from the car collection141. Nbs Auto Center1612 El Camino RealRedwood City, CA 94063(650) 361-91000.7 milesNew Car DealersUsed Car DealersAdd to mybookRemove from mybookAdded to your car collection!Error when adding to car collectionThis business was removed from the car collection142. Baeza AutomotiveServicesBBB Rating: A+816 Hurlingame AveRedwood City, CA 94063(650) 298-83430.3 milesAuto Repair & ServiceBrake RepairWebsiteAdd to mybookRemove from mybookAdded to your car collection!Error when adding to car collectionThis business was removed from the car collection143. Deluxe Transmission & Auto Repair415 Macarthur AveRedwood City, CA 94063(650) 364-96260.3 milesAuto TransmissionAuto Repair & ServiceAdd to mybookRemove from mybookAdded to your car collection!Error when adding to car collectionThis business was removed from the car collection144. Jp AutomotiveBBB Rating: A+2623 Middlefield RdRedwood City, CA 94063(650) 701-02120.4 milesAuto Repair & ServiceWebsiteAdd to mybookRemove from mybookAdded to your car collection!Error when adding to car collectionThis business was removed from the car collection145. Ok Radiator CompanyServices2670 Middlefield RdRedwood City, CA 94063(650) 368-84840.4 milesRadiators Automotive Sales & ServiceWebsiteAdd to mybookRemove from mybookAdded to your car collection!Error when adding to car collectionThis business was removed from the car collection146. A & S Automotive2670 Middlefield RdRedwood City, CA 94063(650) 261-91770.4 milesAuto Repair & ServiceAdd to mybookRemove from mybookAdded to your car collection!Error when adding to car collectionThis business was removed from the car collection147. Universal Auto Service2647 Middlefield RdRedwood City, CA 94063(650) 568-05080.4 milesWheel Alignment-Frame &...WebsiteAdd to mybookRemove from mybookAdded to your car collection!Error when adding to car collectionThis business was removed from the car collection148. Peninsula MercedesServices2745 Spring St Ste ARedwood City, CA 94063(650) 367-73800.4 milesWheel Alignment-Frame &...WebsiteAdd to mybookRemove from mybookAdded to your car collection!Error when adding to car collectionThis business was removed from the car collection149. Redwood Motors Sales & RepairBBB Rating: A+721 Warrington AveRedwood City, CA 94063(650) 257-78500.4 milesAuto Repair & ServiceUsed Car DealersWebsiteAdd to mybookRemove from mybookAdded to your car collection!Error when adding to car collectionThis business was removed from the car collection150. H & H AutomotiveBBB Rating: A+2835 Middlefield RdRedwood City, CA 94063(650) 368-70520.5 milesAuto Repair & ServiceRelated Articlesfor Automotivemore related articles »Six Sanity-Saving Tips for Carpooling »Great apps and resources that can help make you the master of headache-free pickups and dropoffs.Seven Ways to Get Your Family Into Back-to-School Mode »Get ready for back to school while you have the time to do it. From shopping and haircuts to dentists and auto repairs.What to do When Your Airbag Light is On »If you see your airbag light on, there could be an issue that prevents the bags from deploying. Find out what's wrong with your ve…Sponsored LinksShowing121-150
of 2017resultsPrevious34567NextAdd a New CollectionOops! There was a problem saving the new custom collection.Please try again.Collection Name cannot be emptyUpload a Photo(optional)Remaining Characters: 100Remaining Characters: 500CancelSaveMap ViewFeatured Auto Repair & Servicein Redwood VillageJapanese Beetle Inc.(7)928 E El Camino Real, Sunnyvale, CA 94087(650) 666-2458We Do Auto Repair, But What We Sell Is Trust!WebsiteCouponsDirectionsMore InfoDidn't find what you were looking for?magnifying glassPlease help others by helping us do better.Suggest a BusinessHelpful Reviews Toy Auto Clinic, LLC Toyota Repair Specialisttimgrx400 ratedI still can't believeHow amazi...I still can't believeHow amazing this guy is I have a 2007 Lexus RX400H and I needed a 90K service on it badly (I was at 120K) A good friend who works at a Toyota dealership said he'd do it for $2200.00. He claimed it would take 2 days and is difficult. Putnam Lexus: 2 grand to do it. Another shop over by Putnam was "more than willing" to do it for $1400. so then I was looking at Yelp and stumbled on Brian. Everyone had rave reviews and he was close by. I called and asked if he had done a 90K on a lexus? "Yup, sure have" then he quoted me $795 OUT THE DOOR!!!! I'm thinking there's no way he's gonna do this. But I went for it. Let me tell you people. Brian is EVERYTHING everyone else is saying. I was in at 8AM and out at 4PM. He had a box of parts by his desk and went through everything thoroughly. He even offered to wash the car. all for $795. I will NEVER go any where else... EVER! Just so you know, He did all this for $795 Timing belt - replace Water pump -replace trans fluid - flushed Coolent - replaced Engine and Cabin Air Filters - replaced Brake inspection Oil pan drain plug gasket - replaced New Oil Filter New tensioner bearing for the timing belt New ideler bearing Rotate tires Inspect everything I'm still just blown away...Toy Auto Clinic, LLC Toyota Repair Specialistlucia ratedI have a 2007 Toyota Prius and...I have a 2007 Toyota Prius and I used to get it serviced at the dealership. I have not heard great things about the Toyota dealers in this area and a friend recommended Toy Auto Clinic. I have had bad experiences with mechanics in the past, haven't we all, but Brian at Toy Auto Clinic is personable and helpful. His prices are better than the dealership and I really felt like he listened to me and asked the right questions. He took the time to look the car over while I was there and answer my concerns and questions. He didn't have the part on site and had to get it from a dealer because Prius parts are still hard to find, but he had it at his shop in the time it took me to walk down the street and have lunch. (at most half an hour) Prior to this repair, I called to find out if it was something they could do because everyone was telling me I HAD to go to the dealer for a Prius repair, but he was helpful and answered my questions and told me to come in any time. I didn't feel that I was getting the brush off that dealers often give you on the phone. Great service, friendly, helpful, great prices. Even though this is a little far from my house, this is where I am taking my car for all repairs from now on! Toy Auto Clinic, LLC Toyota Repair Specialistjustin69 ratedGoing to a mechanic can be an ...Going to a mechanic can be an expensive and stressful event. I have been taking my Toyota Camry to the dealer because they use original parts and have certified techs. However, during my last service at Toyota they quoted me over 800 dollars on repairs! What? Does it need a new engine? I decide to get a second opinion and I am glad I did. Brian is super cool and honest guy! He told me I dont have to do any of the "suggested services" and instead spent only $200! Sure enough, I get me car and its running great, they even cleaned it. It felt like a new car!! I need an oil change. Where do I take my car? Toy Auto Clinic!!!! . Toyota has officially lost my bussiness. Did You Know?Finding An Auto Repair ProfessionalThere are more than 700,000 auto service technicians and mechanics in the U.S. Finding the right one to repair a dent in your car door or fix an engine that won't start can be overwhelming, especially when it's an emergency. Review a few important facts about auto repair professionals and what you can do to get the best possible mechanic working on your vehicle's issues for a fair price.Looking For Reliability

value: This website is a United States-based web site operated by YP Holdings that provides listings for local businesses. In 2013 it was re-branded as YP.com or simply "YP".


text:
2148 hotellia alueella Lesser Antilles, Britt. Neitsytsaaret.
2 148 majoituspaikkaa
Etsi hotelleja alueelta Lesser Antilles
Offering an outdoor pool and a restaurant, Lambert Beach Resort is located in Road Town. This gorgeous beachfront resort has free Wi-Fi and features on-site sports and activities. Dimitris.
"Very nice resort. The beach in front of the resort is gorgeous. The service was excellent and the food at the restaurant delicious."
Set on Grenada Grand Beach, Flamboyant Hotel & Villas offers amazing views of Grand Anse Bay. It features an outdoor swimming pool, gym and accommodation with balconies. Mary.
"We were on our honeymoon and they welcomed us with rose petals on our beef and a bottle of wine, which was so lovely!
Excellent location with amazing views over grand anse."
Kaikki 2 148 hotellia alueella Lesser Antilles
P.O. RB2528, Rodney Bay, Cap Estate, Saint Lucia
Kaya De La Plata 15, Kralendijk, Bonaire, Sint Eustatius ja Saba
Sabal Palm, Kralendijk, Bonaire, Sint Eustatius ja Saba
Kaya Gob. N. Debrot, Kralendijk, Bonaire, Sint Eustatius ja Saba
Loft Pointe de la Verdure
Route des hôtels, Résidence Créole, 97190 Le Gosier, Guadeloupe
Lesser Antilles – Löydä parhaat hotellit, bed and breakfastit, majatalot ja loma-asunnot todellisten asiakkaiden jättämien 77 685 arvion perusteella.
Perustuu 49 704 asiakasarvioon
Lesser Antilles: # 1 yhteensä 472 hotellista
Perustuu 7 016 asiakasarvioon
Perustuu 20 965 asiakasarvioon
Lesser Antilles: # 1 yhteensä 495 loma-asunnosta
Lesser Antilles: # 2 yhteensä 495 loma-asunnosta
Lesser Antilles: # 3 yhteensä 495 loma-asunnosta
”Very good located,easy to reach the bay,and markets,bakeries! Well equipped rooms,kitchenettes. Very friendly housekeeping,and beach-staff. Wi-Fi works in the room (#105),not only at the reception area!!”
”everything !! Rarely write reviews but everything was so perfect and the staff from reception to housekeeping was so professional so keen to help for everything that i had to say it ! Frankly spending lots of time in hotel during the year but this one was by far THE BEST since year. Swimming pool was also the cleanest we had for so long !”
”Great location on the beach . Clean and safe”
”Facilities and staff were outstanding”
”It was a pleasure to get to know kind people and nice places.”
”The great location, friendly personal, very comfortable hotel, good breakfast”
638 huvilaa
630 huoneistoa
187 lomakeskusta
108 huoneistohotellia
237 viiden tähden hotellia
732 neljän tähden hotellia
384 rantahotellia
316 perheille sopivaa hotellia
6444 Majoitukset
6 285 hotellia, joissa on pysäköintimahdollisuus
5 994 hotellia, jossa on WiFi
3 978 uima-altaalla varustettua hotellia
1 767 rantahotellia
1 059 lemmikkiystävällistä hotellia
30 Marriott-hotellia
Sulje kartta 126121,123219,119347,121549,123916,124277,124277|1,125667,117210,125705,124571,124246,117555,124544|1,117129,124369,117841,125427,124131,123340,123979,125501,116441,125928,126093,126134,121344,116790,121412,123803,102958,125350,124544,124972,124827

value: This website is a Dutch online travel agency for lodging reservations & other travel products, and a subsidiary of Booking Holdings. It is headquartered in Amsterdam.The website has over 28 million listings.


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The 10 Best Hotels Near Tombstone Tavern, Cleveland
Best Hotels Near Tombstone Tavern, Cleveland, Ohio
United States›Ohio (OH)›Cleveland›Cleveland Hotels› Hotels near Tombstone Tavern
Hotels near Tombstone Tavern
2240 Fulton Rd, Cleveland, OH 44113-3947 Read Reviews of Tombstone Tavern
Sponsored WoodSpring Suites Cleveland Airport68 reviews#29 of 38 hotels in Cleveland20829 Emerald Pkwy, Cleveland, OH 44135-60308.1 miles from Tombstone TavernMid-rangeFree Parking $$$$$Show Prices The hotel you picked You might also like these Cleveland hotels The Ritz-Carlton, Cleveland640 reviews#8 of 38 hotels in Cleveland1515 W 3rd St, Cleveland, OH 44113-14031.5 miles from Tombstone TavernLuxuryPets Allowed $$$$$$$$Show Prices Aloft Cleveland Downtown376 reviews#25 of 38 hotels in Cleveland1111 W 10th St, Cleveland, OH 44113-44811.5 miles from Tombstone TavernMid-rangePets Allowed $$$$$$Show Prices Renaissance Cleveland Hotel1,035 reviews#17 of 38 hotels in Cleveland24 Public Sq, Cleveland, OH 44113-22131.6 miles from Tombstone TavernLuxuryPool $$$$$$$$Show Prices Cleveland Marriott Downtown at Key Center906 reviews#5 of 38 hotels in Cleveland127 Public Sq, Cleveland, OH 44114-12171.8 miles from Tombstone TavernMid-rangeGreenPool $$$$$$$$Show Prices Residence Inn Cleveland Downtown473 reviews#14 of 38 hotels in Cleveland527 Prospect Ave E, Cleveland, OH 44115-11131.8 miles from Tombstone TavernMid-rangeFree BreakfastPets Allowed $$$$$$Show Prices Hyatt Regency Cleveland at The Arcade1,276 reviews#15 of 38 hotels in Cleveland420 Superior Ave E, Cleveland, OH 44114-12081.8 miles from Tombstone TavernMid-rangeGreen $$$$$$$Show Prices Radisson Hotel Cleveland - Gateway730 reviews#23 of 38 hotels in Cleveland651 Huron Rd E, Cleveland, OH 44115-11161.8 miles from Tombstone TavernMid-range $$$$$Show Prices Drury Plaza Hotel Cleveland Downtown183 reviews#1 of 38 hotels in Cleveland1380 E 6th St, Cleveland, OH 44114-16061.9 miles from Tombstone TavernMid-rangeFree BreakfastPool $$$$$$$$Show Prices Hilton Cleveland Downtown343 reviews#2 of 38 hotels in Cleveland100 Lakeside Ave E, Cleveland, OH 44114-10201.9 miles from Tombstone TavernLuxuryPool $$$$$$$$Show Prices Metropolitan at The 9, Autograph Collection506 reviews#6 of 38 hotels in Cleveland2017 E 9th St, Cleveland, OH 44115-13151.9 miles from Tombstone TavernLuxuryPets Allowed $$$$$$$$Show Prices Holiday Inn Express Cleveland Downtown947 reviews#7 of 38 hotels in Cleveland629 Euclid Ave, Cleveland, OH 44114-30071.9 miles from Tombstone TavernMid-rangeFree Breakfast $$$$$$Show Prices Hilton Garden Inn Cleveland Downtown1,324 reviews#12 of 38 hotels in Cleveland1100 Carnegie Ave, Cleveland, OH 44115-28061.9 miles from Tombstone TavernMid-rangePool $$$$$Show Prices The Kimpton Schofield Hotel142 reviews#13 of 38 hotels in Cleveland2000 E 9th St, Cleveland, OH 44115-13011.9 miles from Tombstone TavernMid-rangePets Allowed $$$$$$$$Show Prices The Westin Cleveland Downtown866 reviews#3 of 38 hotels in Cleveland777 Saint Clair Ave NE, Cleveland, OH 44114-17112.0 miles from Tombstone TavernMid-rangePets Allowed $$$$$$$Show Prices Hampton Inn Cleveland Downtown1,233 reviews#9 of 38 hotels in Cleveland1460 E 9th St, Cleveland, OH 44114-17082.0 miles from Tombstone TavernMid-rangeFree Breakfast $$$$$$Show Prices Oakwood at Statler Arms1127 Euclid Ave, Cleveland, OH 44115-16012.0 miles from Tombstone Tavern $$$$Show Prices Wyndham Cleveland at Playhouse Square2,547 reviews#28 of 38 hotels in Cleveland1260 Euclid Ave, Cleveland, OH 44115-18372.1 miles from Tombstone TavernMid-rangePool $$$$$Show Prices Doubletree Cleveland Downtown / Lakeside1,775 reviews#21 of 38 hotels in Cleveland1111 Lakeside Ave E, Cleveland, OH 44114-11302.2 miles from Tombstone TavernMid-rangePool $$$$$$Show Prices Comfort Inn Downtown567 reviews#19 of 38 hotels in Cleveland1800 Euclid Ave, Cleveland, OH 44115-22442.3 miles from Tombstone TavernMid-rangeFree BreakfastPets Allowed $$$$$Show Prices University Hotel and Suites163 reviews#32 of 38 hotels in Cleveland3614 Euclid Ave, Cleveland, OH 44115-25333.0 miles from Tombstone TavernFree ParkingFree BreakfastBudget $$$$$Show Prices Travelodge Cleveland Lakewood330 reviews#1 of 2 hotels in Lakewood11837 Edgewater Dr, Lakewood, OH 44107-17083.3 miles from Tombstone TavernFree ParkingFree BreakfastBudget $$$$Show Prices Days Inn Cleveland Lakewood154 reviews#2 of 2 hotels in Lakewood12019 Lake Ave, Lakewood, OH 44107-18053.4 miles from Tombstone TavernFree ParkingFree BreakfastBudget $$$$Show Prices Hampton Inn Cleveland Airport-Tiedeman Rd277 reviews#1 of 2 hotels in Brooklyn10305 Cascade Xing, Brooklyn, OH 44144-23204.5 miles from Tombstone TavernFree BreakfastBudgetPool $$$$Show Prices Extended Stay America - Cleveland - Brooklyn65 reviews#2 of 2 hotels in Brooklyn10300 Cascade Xing, Brooklyn, OH 44144-23004.5 miles from Tombstone TavernFree ParkingBudgetPets Allowed $$$$Show Prices Holiday Inn Cleveland Clinic78 reviews#27 of 38 hotels in Cleveland8650 Euclid Ave, Cleveland, OH 44106-20344.6 miles from Tombstone TavernMid-rangePool $$$$$$Show Prices InterContinental Suites Hotel Cleveland413 reviews#26 of 38 hotels in Cleveland8800 Euclid Ave, Cleveland, OH 44106-20384.7 miles from Tombstone TavernMid-rangeGreen $$$$$$$Show Prices InterContinental Hotel Cleveland455 reviews#18 of 38 hotels in Cleveland9801 Carnegie Ave, Cleveland, OH 44106-21004.9 miles from Tombstone TavernGreenLuxury $$$$$$$$Show Prices Days and Night Inn14013 Terminal Ave, Cleveland, OH 44135-20095.0 miles from Tombstone TavernFree ParkingFree BreakfastPool $$$$Show Prices DoubleTree by Hilton The Tudor Arms Hotel1,141 reviews#10 of 38 hotels in Cleveland10660 Carnegie Ave, Cleveland, OH 44106-30195.2 miles from Tombstone TavernMid-range $$$$$Show Prices Cleveland Airport Hotel208 reviews#31 of 38 hotels in Cleveland4181 W 150th St, Cleveland, OH 44135-13035.4 miles from Tombstone TavernMid-rangeFree ParkingPool $$$$$Show Prices *Prices above are the average nightly price provided by partners and may not include all taxes and fees. Any taxes and fees that are shown are estimates only. Please see further details from our partners. PreviousNext123456…9

value: This website is an American online travel company that operates a website and mobile app with user-generated content and a comparison shopping website.


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Ludwig van Beethoven 1770 - 1827 German composer and pianist From The Listeners History of Music published 1925 PosterPrint - Walmart.com
Ludwig van Beethoven 1770 - 1827 German composer and pianist From The Listeners History of Music published 1925 PosterPrint
$54.72$54.72
Ludwig van Beethoven, 1770 - 1827. German composer and pianist. From The Listener's History of Music, published 1925. was reproduced on Premium Heavy Stock Paper which captures all of the vivid colors and details of the original.
Brand New and Packaged carefully in a oversized prote
DPI2430550
Electrode, Comp-389269086, DC-prod-cdc04, ENV-prod-a, PROF-PROD, VER-24.12.4, SHA-fe5eabd678e73ffedf22f999efa2080c42d5639a, CID-

value: This website is an American multinational retail corporation that operates a chain of hypermarkets , discount department stores, and grocery stores from the United States, headquartered in Bentonville, Arkansas.


text:
P. 1Fungsi Dan Tugas Kepala SekolahFungsi Dan Tugas Kepala SekolahRatings: (0)|Views: 5,374|Likes: 30Published by emri-ardi-3678More info:Published by: emri-ardi-3678 on Nov 21, 2011Copyright:Attribution Non-commercialAvailability:Read on Scribd mobile: iPhone, iPad and Android.Free download as PDF, DOC, TXT or read online for free from ScribdFlag for inappropriate content|Add to collectionSee MoreSee lesshttp://www.scribd.com/doc/73319385/Fungsi-Dan-Tugas-Kepala-Sekolah04/11/2013pdftextoriginal You're Reading a Free Preview
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RecommendedTugas Pokok Dan Fungsi Kepala SekolahSyukur Halim AwandanTUGAS KEPALA SEKOLAHjoliebeePeran Dan Fungsi Komite Sekolahyuli_haibarbkm organisasi

value: This website is an American e-book and audiobook subscription service that includes one million titles.


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Custom Personalised 38mm Pin Badges | eBay Skip to main content eBay Shop by category Enter your search keyword All Categories Advanced Daily DealsCollections My eBay Expand My eBay My eBay Summary Bids/Offers Watch List Wish List All Lists Purchase History Selling My Collections Followed Searches Messages Collect & Spend Learn more Sell Expand Sell Sell Sell an item Seller centre International selling Seller protection Seller Fees Sell for Charity Community Expand Community Community Answer Centre Discussion Boards Groups News Help & Contact Help & Contact Contact Us (Phone / Chat / E-mail) FAQs Delivery & Returns Ask the eBay Community Resolution Centre Back to home page
Details about Custom Personalised 38mm Pin Badges
Custom Personalised 38mm Pin Badges
25mm Custom Badges Button Personalised... £0.99
CUSTOM 25mm BADGES, YOUR DESI... £0.99
I Love Your Text Personalised Button... £1.10
Personalised Custom 45mm Button Badg... £1.15
eBay item number:220802548009
ApronsBadges BagsBlackboard Self Adhesive VinylBookmarksClothing - AdultClothing - Kids and BabiesDrinks BottlesDrinks CoastersFridge MagnetsGift SetsHats (Baseball, Chefs Etc)Hi-Vis Clothing HomewareIpad CaseJigsawsKeyringsKitesLabelsLanyardsManicure SetMobile Phone/Mp3/Glasses CaseMoney BoxMouse MatsMugsOffice/School StationaryOven Mitts and GlovesPet TagsPurses/WalletsSignage Design your own 38mm Pin Badge.
Have your Picture, Design, Slogan or Logo on a 38mm Badge. This listing is for one 38mm fully customised pin badge with any design you like!
Ordering is easy, simply complete your purchase then email us on info@tfgraphics.co.uk detailing your design or ideas and attaching any photos/Images or pictures you would like to use. We will then send you back a proof to approve once agreed we will print and despatch the 38mm Badge via 1st class post. ( please note - Postage discounts apply to multiple orders.) <?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />
We are always happy to help with any design requirements and Special requests.
Please email us with your questions on info@tfgraphics.co.uk Discounts are available for quantity orders, please email for information.
N.B - Please ensure all text and words to be printed have been spell checked as we will print as per the email instruction we receive.
Our Badges are printed in full colour then sealed with a mylar sheet for protection. Badges have a plastic back, with a metal pin fastener.
£0.40 P&P for each additional eligible item you buy from tfgraphics, when you use the basket to make your purchase.
Personalised Pin Badges,

value: This website is an American multinational e-commerce corporation based in San Jose, California, that facilitates consumer-to-consumer and business-to-consumer sales through its website.