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Patent US7327204 - Analog delay chain having more uniformly distributed capacitive loads and ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently...http://www.google.com/patents/US7327204?utm_source=gb-gplus-sharePatent US7327204 - Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chainAdvanced Patent SearchPublication numberUS7327204 B2Publication typeGrantApplication numberUS 11/640,079Publication dateFeb 5, 2008Filing dateDec 15, 2006Priority dateAug 27, 2004Fee statusPaidAlso published asUS7190226, US20060044061, US20070115074Publication number11640079, 640079, US 7327204 B2, US 7327204B2, US-B2-7327204, US7327204 B2, US7327204B2InventorsDebanjan Mukherjee, Jishnu BhattacharjeeOriginal AssigneeScintera Networks, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (8), Classifications (10), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetAnalog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chainUS 7327204 B2Abstract A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (Sin(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.
1. A tapped delay chain comprising a plurality of analog delay cells where at least a first delay cell in the chain has associated therewith a follow-on processing unit having an input capacitance and the first delay cell has:
at least two output taps for respectively outputting first and second delayed signals derived from and delayed relative to a received analog input signal of the first delay cell, where the delays of the first and second delayed signals differ from one another,
where a first of the at least two output taps is operatively coupled for feeding forward the corresponding first delayed signal to a next delay cell in the chain, and
where a second of the at least two output taps is operatively coupled for feeding the corresponding second delayed signal to the respective follow-on processing unit of the first delay cell so that the second delayed signal can be processed by the respective follow-on processing unit without loading the first output tap of the first delay cell with the input capacitance of the respective follow-on processing unit.
2. The tapped delay chain of claim 1 wherein:
said follow-on processing unit includes an analog signal multiplier.
3. A tapped delay processing system comprising:
a plurality of analog delay cells where each respective delay cell has associated therewith a respective follow-on processing unit having an input capacitance and each respective delay cell has:
at least two output taps for respectively outputting first and second delayed signals derived from and delayed relative to a received input signal of the respective delay cell, where the delays of the first and second delayed signals differ from one another,
where a second of the at least two output taps is operatively coupled for feeding the corresponding second delayed signal to the respective follow-on processing unit of the respective delay cell so that the second delayed signal can be processed by the respective follow-on processing unit without loading the first output tap of the respective delay cell with the input capacitance of the respective follow-on processing unit; and
a combiner operatively coupled to receive a plurality of processed signals from the follow-on processing units of at least two of said plurality of delay cells and to combine the received plurality of processed signals so as to thereby generate an output signal that is a function of the combined processed signals.
4. The tapped delay processing system of claim 3 where at least two of said follow-on processing units each comprises a programmable multiplier.
5. The tapped delay processing system of claim 3 wherein the combiner includes an adder.
6. A feed-forward equalizer comprising:
a tapped analog delay line having a plurality of delay cells, each delay cell having an input node for receiving a corresponding input signal, a primary output node for outputting a corresponding primary delayed signal to a next of the delay cells and a secondary output node for outputting a corresponding secondary delayed signal, wherein delays of corresponding primary and secondary delayed signals differ substantially from one another;
a plurality of multipliers each coupled to a corresponding one of the secondary output nodes; and
an adder coupled to at least two of the multipliers.
7. The feed-forward equalizer of claim 6 wherein:
each delay cell includes a variable output impedance, and the output impedance has a primary output terminal and a secondary output terminal for respectively defining the corresponding primary and secondary output nodes of the delay cell.
8. The feed-forward equalizer of claim 6 wherein:
each delay cell includes a plurality of matched output impedances, and each of the matched output impedances has a respective primary output terminal and a respective secondary output terminal.
9. The feed-forward equalizer of claim 8 wherein:
each of the matched output impedances is a variable impedance.
CROSS REFERENCE TO CO-OWNED APPLICATIONS The following copending U.S. patent applications are owned by the owner of the present application, and benefit is claimed pursuant to 35 USC �120 at least from the parent patent application denoted below as (A). The disclosures of said application (A) and the others are incorporated herein by reference:
(A) Ser. No. 10/928,420 filed Aug. 27, 2004 by Debanjan Mukherjee and Jishnu Bhattacharjee and entitled �Analog Delay Chain Having More Uniformly Distributed Capacitive Loads and Analog Delay Cell for Use in Chain�;
(B) Ser. No. 10/724,443 filed: Nov. 26, 2003 by Mukherjee et al and originally entitled �Analog Delay Elements�;
(C) Ser. No. 10/724,449 filed: Nov. 26, 2003 by Bhattacharjee et al and originally entitled �Digitally Controlled Transconductance Cell�; and
(D) Ser. No. 10/698,317 filed: Oct. 30, 2003 by Mukherjee et al and originally entitled �Programmable Passive Inductor�.
FIELD OF DISCLOSURE The invention relates generally to analog delay lines with periodically tapped output nodes and more specifically to high frequency applications in which lumped capacitances can have detrimental effects on response bandwidth. The invention relates yet more specifically to high frequency applications where the tapped output nodes of the delay chain are to be utilized, by for example, programmably weighting each and summing them so as define a feedforward equalizer (FFE) or the like.
(A) U.S. Pat. No. 6,545,502 issued Apr. 8, 2003 to Dasgupta et al. and entitled �High frequency MOS fixed and variable gain amplifiers�; and (B) U.S. Pat. No. 6,717,467 issued Apr. 6, 2004 to Renous et al. and entitled �Wideband differential amplifier comprising a high frequency gain-drop compensator device�. DESCRIPTION OF RELATED ART High speed communication links such as optical fiber links or electrically conductive links (e.g., copper links) typically operate at very high serial data rates, 1 Gb/s (one Giga bits per second) to 10 Gb/s for example. If analog processing is desired for the signals transmitted along these high speed links such processing may call for analog circuitry having extremely wide bandwidths. More specifically, if an optical-to-electrical-to-optical repeater is to be constructed that provides high fidelity reconstruction of a series of essentially rectangular pulses that have been passed through a relatively long link (e.g., a fiber link of about 100 meters or greater for the 10 Gb/s rate), the analog bandwidth may be on the order of several GHz. This is so because the frequency domain content of the rectangular pulses often extends to frequencies larger than the maximum bit rate of the transmission itself. Typically the 3 dB drop-off frequency will be rated at about 70% of the maximum bit rate for providing a good-fit solution to the tradeoff between filtering away high-end noise and minimizing inter-symbol-interference (ISI). Special analog design strategies may be needed for processing electrical signals with these types of constraints.
One known type of analog signal processing uses a periodically-tapped delay line. Each tap feeds a respective one of plural programmable multipliers. Each multiplier further receives a respective multiplying coefficient (Mi) and outputs a coefficient weighted version (Mi�S(t−Ti/k) of the delayed signal it has received from the tapped delay line. An adder may then sum together the delayed and weighted signals so as to provide a desired type of filtering function. The combination of the tapped delay line, plural multipliers and adder is sometimes referred to as a feed-forward equalizer (FFE). When the delay taps are equally spaced apart by less than a symbol period (T), the combination is referred to as a fractionally-spaced feed-forward equalizer (FS-FFE, e.g. tau=T/2 or tau=T/3).
DETAILED DESCRIPTION Referring to FIG. 1, an environment 100 in which cascaded delay cells may be employed is first described. Input signal Sin(t) may be a wide bandwidth communications signal such as that obtained from passing a series of substantially rectangular signal pulses through a transmission medium (e.g., a continuous fiber optic link) that exhibits signal dispersion. To correct for the dispersion, filtering is employed. In one embodiment, periodically delayed versions, Sin(t−i�T/k) of the input signal are generated, where i represents successive ones of a sequential series of whole numbers (0, 1, 2, . . . , n), k is a whole number such as 2 or 3, and τ=T/k, where T is a predefined symbol period. The periodically delayed versions of the input signal are respectively multiplied by independent weighting coefficients (Mi) and the resulting product signals (Pi) are added to produce an adaptively equalized output signal, Sout(t). Adaptive equalization may be carried out by changing the weighting coefficients (Mi).
Ideally, the first delay cell 110, and each successive delay cell in the chain, 120, . . . , 1 n 0; provides unity gain and an output delay of time value, τ. The output of the first delay cell 110 couples to a first common node 111, which further connects to the input of the next delay cell 120 and also to the input of the next multiplier 112. Symbol 119 represents the combined capacitance, C1, at node 111 corresponding to the capacitances of the output of the first delay cell 110, the input of the second delay cell 120, the input of the second multiplier 112 and the interconnect routing associated with these terminals, where the effective combined capacitance, C1, can be parasitic in nature and/or intentionally designed in. The output of the second multiplier 112 feeds into input terminal 113 of adder 104. A similar pattern continues for the next successive delay cell and so on. Schematic symbol 129 represents the lumped capacitance, C2 for node 121, this corresponding to the capacitances of the output stage of the second delay cell 120, the input of the third multiplier 122 and the input of the next delay cell (not shown). The actual delay which each of the summed signals experiences includes the plurality of i delay cells the original Sin(t) passes through, plus a commonly-attributed delay, td1 associated with passing through the respective multiplier (e.g. 122) and through the summing unit 104 before emerging as part of the final sum on line 105. Symbol 106 represents this commonly associated delay, td1. The actual output signal on line 105 may be represented by the following equation, Eq. 1:
S out  ( t ) = ∑ i = 0 i = n   M i � S in  ( t - i   τ - t D1 ) Eq .  1 Of importance, the frequency response of each delay stage, 110, 120, . . . , 1 n 0 depends on the magnitude of the lumped capacitances Ci at its input and output nodes, such as those schematically shown at 119, 129, . . . , 1 n 9. If each lumped capacitance, Ci is relatively large, then a greater amount of current will be shunted to ground as frequency increases and the maximum response frequency of the system becomes relatively small. On the other hand, if the lumped capacitance at each common node (e.g., 111) can be made substantially smaller, then less current will be shunted to ground at higher frequencies and the effective bandwidth of the circuit may be made comparatively larger. Reducing the lumped capacitance, Ci is difficult because three terminals meet at the common node 111, namely, the output terminal of the preceding delay cell 110, the input terminal of the next successive delay cell 120 and the input terminal of the associated multiplier 112. Each of these input/output terminals has some amount of parasitic capacitance associated with it and therefore it is not possible to eliminate these sources of additive capacitance under the illustrated architecture 100 of the so-called feedforward equalizer (FFE).
Referring to FIG. 2, an improved structure 200 in accordance with the invention is shown. Each delay cell has at least two output taps rather than just one. For example, the first delay cell in the chain 210 has a first output tap 211 coupling it to the next delay cell 220 and a separate, second output tap 212 coupling it to multiplier 216. Different primary and secondary delays, τ and τ2, are associated respectively with the first and second output taps, 211 and 212. The parasitic capacitance associated with the first output node 211 is of quantity C1b (219 b) while the parasitic capacitance associated with second output node 212 is of quantity C1a (219 a). It is understood that at least one, and typically each of C1a and C1b is less than the combined node capacitance C1 (119) of FIG. 1. Accordingly, because the distributed node capacitances 219 a, 219 b of the structure shown in FIG. 2 are generally smaller than the lumped node capacitance 119 (FIG. 1), the upper bandpass frequency of the delay circuit and multipliers of FIG. 2 can be increased relative to the upper bandpass frequency of the circuit 100 shown in FIG. 1. In one embodiment, the secondary delay, τ2 (207) is approximately 10 pico-seconds (10 ps) as measured between the product output node 203 (P0) of the first stage and the product output node 213 (P1) of the second stage. The primary delay, τ (217) is a larger quantity, of about 30-40 pico-seconds in the one embodiment where τ2 (207) is approximately 10 ps. The primary delay, τ (217) may be measured as the effective signal delay between product output nodes 213 (P1) and 223 (P2). The larger, primary delay τ (represented schematically by arrow-tipped lines 217 and 2 n 7) is the one that dominates the sum of periodically delayed signals output on line 205. Thus the primary delay, τ primarily determines the frequency-domain response of the circuit 200. In one embodiment, the larger, primary delay, τ (217, 2 n 7) is approximately ⅓ of a symbol period (T), which in the case of a bit period of T=100 pico-seconds is approximately 30 to 40 ps.
Although FIG. 2 shows the secondary subtaps, 212, 222, . . . , 2 n 2 as each being coupled to a respective, programmable multiplier, 216, 226, . . . , 2 n 6; it is within the contemplation of the disclosure for the secondary subtaps, 212, 222, . . . , 2 n 2 to instead more generically couple to any appropriate, follow-on unit which is to process the correspondingly delayed signal (e.g., Sin(t−τ2)) as may be desired while avoiding the penalty of having lumped capacitances from joining both the follow-on unit (112 in FIG. 1) and the next delay cell (120 in FIG. 1) to a common node (111 in FIG. 1). It is further within the contemplation of the disclosure for there to be more than just two subtaps (e.g., 211, 212) per delay cell. A plurality of such subtaps may be provided in each delay cell as will become more apparent when FIG. 3 is detailed. The number of subtaps per delay cell may vary depending on application. In some applications it may be desirable to provide a number of different, follow-on functions for each delay cell such as a follow-on multiplication (216), and a separate, follow-on addition (not shown) and/or a separate, follow-on other function where the penalty of added-on and lumped capacitance is avoided by attaching the follow-on function-providing units (e.g., 216) to separate subtaps of the given delay cell.
In the FFE configuration shown in FIG. 2, it is generally desirable to maintain the base gain of each delay cell, 210, 220, 230, . . . , 2 n 0, at approximately unity (gmR�1) so that there will be essentially no increase or decrease in signal strength as an input signal, Sin(t) cascades through a programmably-chosen number of delay cells. Otherwise, a cascaded change of signal strength will skew the weighting coefficients M0-Mn that actually define the summed result produced on output line 205. It will be seen that one of the advantages of the multiply-tapped delay cells 210, 220, etc. is that the unity gain factor of each given cell (e.g., Gain231 of cell 230) can be assured for the first tapped output 211 separately from the specific output gain provided at the secondary tapped output 212. In one embodiment, the output gain of the secondary tapped outputs 212, 222, . . . , 2 n 2 is greater than unity, thereby reducing the need to have a larger multiplier factor, M1, M2, . . . , Mn at each of the respective, follow-on multipliers 216, 226, . . . , 2 n 6. In summary, FIG. 2 shows a feedforward equalizer (FFE) having sub-tapped delay cells and smaller distributed capacitances at the sub-tapped output nodes.
The respective drain impedances of the differentially-opposed transistors, N1 and N2, are symmetrically identical. Each drain impedance includes a series of inductors. For example, the drain impedance of N1 includes the illustrated inductances, L1 a, L2 a, and L3 a. The drain impedance of N2 correspondingly includes the illustrated inductances, L1 b, L2 b, and L3 b. In one embodiment inductors L1 a and L2 a include vertically stacked spiral coils disposed vertically above one another in different, insulatively spaced apart metal layers (conductive interconnect layers) of an integrated circuit and mutually coupled to each other by a coupling factor K12 having a value of approximately one. It is believed, that a mutual coupling factor of K12 of approximately unity provides the most physically compact structure for maximizing the effective, combined inductance of L1 a and L2 a. The third drain inductor L3 a does not have to be mutually coupled to the other two inductances L1 a and L2 a, of the respective N1 drain impedance. Each of the coils typically has associated with it a parasitic series resistance such as illustrated at 371 b, 372 b, and 373 b. In addition to the inductors and their respective, parasitic series resistances (optional), an intentional drain resistance 374 is included in the series path of each of the drain currents, Id1 and Id2. The intentional drain resistance 374 includes a portion (R4a, R4b) separating the remainder of the respective drain impedance from the power rail node 375 (+Vdd). In one embodiment, a programmably-variable resistance 376 (R5) is provided between the lower nodes of R4 a and R4 b (the opposed 374 resistances) for adjusting the effective base gain, gmR, of the primary output node 311. In one embodiment each of R4 a and R4 b is approximately 100 ohms plus or minus 5 ohms. The exact resistance may vary as a function of fabrication process and/or temperature. Adjustment of variable resistance R5 may be used to cause the effective, primary base gain of the amplifier, gmR to be approximately unity at node 311. The base gain at output node 311 is the gain at 0 Hz frequency, which is simply the effective DC drain resistance, as seen by each of the opposing drain currents Id1 and Id2 multiplied by the effective transconductance (gm) of the differential amplifier. Because Id1, and Id2 oppose each other by a differential amount so as to sum to the magnitude of the common current Ic (379) there will be a virtual ground (V=0) somewhere in the mid-point of resistance R5 (376). A variable voltage divider is therefore created for each of the drain legs between the virtual ground and the +Vdd voltage level of node 375. The schematic symbol at 376 a indicates that variable resistance R5 may be implemented as a single P-channel MOS transistor. Gate control signal 377 c′ may be used to programmably vary the resistance of transistor 376 a. An advantage of such a structure is that it is more compact and it automatically generates its own virtual ground (V=0) without having to adjust for process variations and temperature variations about a true ground node.
L1/L2=f(C para , C var , C parb) Eq. 2.
The DC voltage developed at primary output node 311 will be approximately Vdd−Id2�R4b (assuming R5 is very large and RsL3a/b is negligible). Because the parasitic series inductance resistances of L1 and L2, namely, resistances 371 b and 372 b, appear below node 311, the voltage output at the secondary tap 312 will have a higher base gain of gm�(R+RsL1b+RsL2b). In one embodiment, this secondary tap output gain is about 20% greater than unity. Of course, additional resistances may be added in series below node 311 and/or the resistances of the L1 and L2 coils may be purposefully made larger to further increase the base gain of the secondary tap output 312. Because the gain of the secondary tap output 312 can be made greater than one, the subsequent multipliers such as 316 do not have to provide as much of a gain as they otherwise would for achieving a desired weighting factor greater than one. The gain of differential amplifier based, delay unit 310 may therefore be used for simultaneously providing both a weighted gain (>1) at secondary output node 312 and a unity gain at primary output node 311. Thus two functions are provided from a single compact structure 310. Energy is conserved to the extent that the follow-on multipliers (316) do not have to provide greater boosting for attaining the desired weighting coefficient. The delay cell provides some of that as a pre-boost.
Methods for providing variable capacitances such as for capacitances 318 and 318′ of FIG. 3 are well known and need not be detailed here. Discrete switches may be used in combination with metal-insulator-metal (MIM) capacitors and/or voltage sensitive or insensitive MOS capacitors. It is worthy to note that the capacitance-setting switches should be appropriately sized so as to reduce their series resistance. Increasing transistor size also tends to increase the parasitic capacitance. Thus, reduction of switch resistance and switch capacitance trade off with each other.
Methods for providing variable inductances may also be used if desired, for tuning one or more of the inductances (L1, L2 and L3) in the delay cell 310 of FIG. 3. These methods may include a programmable switching in and out of additional inductors and/or changing the mutual inductance between L1 and L2. Such methods are disclosed for example in the above-cited U.S. Ser. No. 10/698,317 originally entitled �Programmable Passive Inductor� and incorporated herein by reference.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5050186 *Jan 4, 1989Sep 17, 1991U.S. Philips Corp.Signal equalizing arrangement and a method of equalizing a received data signalUS5418497Jul 5, 1994May 23, 1995Motorola, Inc.Low voltage VCO having two oscillator circuits of different frequenciesUS6023192Oct 9, 1998Feb 8, 2000Stmicroelectronics S.A.Dual gain amplifier circuitUS6504432Mar 30, 2001Jan 7, 2003Xilinx, Inc.Tunable, dynamic, and self-biasing differential amplifier and application thereofUS20040189387Mar 25, 2004Sep 30, 2004Nec Electronics CorporationFrequency characteristics-variable amplifying circuit and semiconductor integrated circuit deviceUS20060028275Aug 3, 2004Feb 9, 2006Scintera Networks, Inc.Differential amplifier having independently tunable base gain, peak gain and boost frequency, and uses of sameUS20060061415Sep 21, 2004Mar 23, 2006Scintera Networks, Inc.Low voltage broadband gain cellUS20060091954Oct 29, 2004May 4, 2006Hooman DarabiMethod and system for common mode feedback circuitry for RF buffers* Cited by examinerClassifications U.S. Classification333/28.00R, 333/18International ClassificationH04B3/04Cooperative ClassificationH03F2203/45638, H03F2203/45712, H03F3/45183, H03F2203/45688, H03F2203/45652, H03F2203/45631European ClassificationH03F3/45S1B1Legal EventsDateCodeEventDescriptionAug 4, 2011FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google


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A jury in the inquests into the deaths of two young children who died of carbon monoxide poisoning during a holiday on the Greek island of Corfu has been told by a coroner the only conclusion it can come to is unlawful killing.
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The children were found dead in a bungalow in the grounds of the Louis Corcyra Beach Hotel by a chambermaid. Mr and Mrs Shepherd were found in comas but later recovered.
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Patent US4625331 - Automatic frequency control system or an SSB receiver - Google Patents
A frequency control circuit for a single sideband receiver is disclosed wherein the local oscillator is swept at a first rate to enable the acquisition of a transmitted signal. When the signal is acquired, the local oscillator is swept at a second rate in an indicated direction in order to center the...http://www.google.com/patents/US4625331?utm_source=gb-gplus-sharePatent US4625331 - Automatic frequency control system or an SSB receiver
Publication number US4625331 A
Application number US 06/618,609
Publication number 06618609, 618609, US 4625331 A, US 4625331A, US-A-4625331, US4625331 A, US4625331A
Patent Citations (11), Non-Patent Citations (8), Referenced by (17), Classifications (13), Legal Events (6)
Automatic frequency control system or an SSB receiver
US 4625331 A
A frequency control circuit for a single sideband receiver is disclosed wherein the local oscillator is swept at a first rate to enable the acquisition of a transmitted signal. When the signal is acquired, the local oscillator is swept at a second rate in an indicated direction in order to center the signal. Upon centering, the local oscillator is maintained at a frequency which centers the signal in response to the activation of a squelch detector.
1. An automatic frequency control system for a single sideband radio receiver having a local oscillator, mixer, and IF bandpass and receiving a signal containing, inter alia, squelch activation information transmitted by a transmitter comprising:
first means for varying the local oscillator frequency of the radio receiver at a first given rate;
means, responsive to the local oscillator frequency, for acquiring the transmitted signal and indicating a direction in which said local oscillator frequency should be varied to essentially center the transmitted signal in the radio receiver IF bandpass;
means, coupled to said means for acquiring, for detecting the squelch activation information;
second means, coupled to said means for acquiring, for varying said local oscillator frequency of the radio receiver at a second given rate in said indicated direction; and
means, coupled to said squelch activation information detection means, for ceasing variation of said local oscillator frequency by said first and second varying means and maintaining said frequency essentially constant.
2. An automatic frequency control system in accordance with claim 1 wherein said means for detecting the squelch activation information further comprises means for commencing detection of squelch activation information before the transmitted signal is centered.
3. An automatic frequency control system in accordance with claim 2 wherein said means for commencing detection of squelch activation information further comprises means for cancelling said second given rate local oscillator variation therein.
4. An automatic frequency control system in accordance with claim 1 wherein said means for acquiring the transmitted signal further comprises means for providing a beat note output when the transmitted signal is acquired.
5. An automatic frequency control system in accordance with claim 4 wherein said means for acquiring the transmitted signal further comprises means for full wave rectification of said beat-note output.
6. An automatic frequency control system in accordance with claim 5 wherein said means for acquiring the transmitted signal further comprises means for generating a unitary output when said beat-note rectification reaches a predetermined level thereby activating said means for detecting the squelch activation information.
7. An automatic frequency control system in accordance with claim 6 wherein said means for acquiring the transmitted signal further comprises means for maintaining said unitary output for a predetermined period of time after said beat-note rectification falls below said predetermined level thereby providing hysteresis in said unitary output.
8. An automatic frequency control system in accordance with claim 7 wherein said means for maintaining said unitary output further comprises means, sensitive to impulse noise received with the transmitted signal, for modifying said predetermined unitary output maintainance time.
9. An automatic frequency control circuit for a single sideband radio receiver having a local oscillator, mixer, and IF bandpass and which receives a signal transmitted by a transmitter and detects squelch information in the transmitted signal comprising:
means for varying the local oscillator frequency of the radio receiver;
means, responsive to the local oscillator frequency, for acquiring the transmitted signal and indicating a direction in which the local oscillator frequency should be varied to essentially center the transmitted signal in the radio receiver IF bandpass;
means, coupled to said means for acquiring, for commencing detection of squelch information from the transmitted signal when the signal is acquired and for removing said local oscillator frequency variation from the squelch information; and
means for deactivating said local oscillator frequency varying means in response to said squelch detection.
10. An automatic frequency control circuit in accordance with claim 9 wherein said means for acquiring the transmitted signal further comprises means for providing a beat note output when the signal is acquired.
11. An automatic frequency control circuit in accordance with claim 10 wherein said means for acquiring the transmitted signal further comprises means for full-wave rectification of said beat-note output.
12. An automatic frequency control circuit in accordance with claim 11 wherein said means for acquiring the transmitted signal further comprises means for generating a unitary output when said beat-note rectification reaches a predetermined value and maintaining said unitary output for a predetermined period of time after said beat-note rectification falls below said predetermined value.
13. An automatic frequency control circuit in accordance with claim 12 wherein said means for acquiring the transmitted signal further comprises means, sensitive to impulse noise received with the transmitted signal, for modifying said unitary output maintainance time.
14. An automatic frequency control circuit for a single sideband radio receiver in which a local oscillator is varied in frequency to acquire a transmitted signal containing, inter alia, squelch activation information, the automatic frequency control circuit comprising:
means for varying the local oscillator frequency of the radio receiver at a first given rate;
means, responsive to the local oscillator frequency, for determining the acquisition of the transmitted signal and providing a beat-note output when the signal is acquired;
means for full-wave rectification of said beat-note output;
means for providing a unitary output when said beat-note rectification reaches a predetermined value;
means, responsive to said unitary output, for varying the local oscillator frequency at a second given rate; and
means for maintaining said unitary output for a predetermined period of time after said beat-note rectification falls below said predetermined value thereby providing hysteresis in said unitary output.
15. An automatic frequency control circuit in accordance with claim 14 wherein said automatic frequency control circuit further comprises means for commencing detection of squelch activation information from the transmitted signal when the signal is acquired.
16. An automatic frequency control circuit in accordance with claim 14 wherein said automatic frequency control circuit further comprises means, sensitive to impulse noise received with the transmitted signal, for modifying said predetermined period of unitary output maintainance time.
17. An automatic frequency control circuit for a single sideband radio receiver having a local oscillator, mixer, and IF bandpass and receiving a signal transmitted by a transmitter, comprising:
means, responsive to the local oscillator frequency, for acquiring the transmitted signal and providing a beat-note output in response thereto;
means responsive to said unitary output for ceasing said first local oscillator variation at a first rate, and for indicating a direction the local ocsillator frequency should be varied to essentially center the transmitted signal in the radio receiver IF bandpass;
second means, responsive to said unitary output and indicated direction, for varying said local oscillator frequency of the radio receiver at a second given rate in said indicated direction;
means, coupled to said means for acquiring, for commencing detection of squelch information from the transmitted signal before the signal is centered; and
means for deactivating said second varying means in response to said squelch detection.
18. An automatic frequency control circuit in accordance with claim 17 wherein said frequency control circuit further comprises means for maintaining unitary output for a predetermined period of time after said beat-note rectification falls below said predetermined value.
19. An automatic frequency control circuit in accordance with claim 18 wherein said automatic frequency control circuit further comprises means, sensitive to impulse noise received with the transmitted signal, for modifying said predetermined period of unitary maintainance time.
20. A method of controlling the frequency of a single sideband radio receiver having a local oscillator, mixer, and IF bandpass and receiving a signal containing, inter alia, squelch activation information transmitted by a transmitter comprising the steps of:
varying the frequency of the local oscillator of the receiver at a first given rate;
acquiring the transmitted signal in cooperation with the local oscillator and indicating a direction in which said local oscillator frequency should be varied to essentially center the transmitted signal in the radio receiver IF bandpass;
detecting the squelch activation information;
varying said local oscillator frequency at a second given rate in said indicated direction in response to said transmitted signal acquiring step thereby centering the signal; and
ceasing said first and second rates of local oscillator frequency variation, in response to squelch activation information detection, and maintaining said local oscillator frequency at a point where the transmitted signal is essentially centered when said squelch activation information detection occurs.
21. A method for controlling frequency in accordance with the method of claim 20 further comprising the step of commencing detection of squelch activation information before the transmitted signal is centered.
22. A method of controlling frequency in accordance with the method of claim 20 wherein the step of acquiring the transmitted signal further comprises the steps of providing a beat-note, rectifying said beat-note, and generating a unitary output when said beat-note rectification reaches a predetermined value.
23. A method of controlling frequency in accordance with the method of claim 22 wherein the step of acquiring the transmitted signal further comprises the step of maintaining said unitary output for a predetermined period of time.
24. A method of controlling frequency in accordance with claim 23 wherein the step of acquiring the transmitted signal further comprises the step of modifying said predetermined unitary output maintainance time in response to impulse noise received with the transmitted signal.
This invention relates generally to radio receiver frequency control systems and more particularly to an automatic frequency control (AFC) for a single sideband receiver to be used at frequencies designated for land mobile services.
In a single sideband radio system, the tolerable frequency error without significant loss of voice recognition or intelligibility is approximately ±20 Hz. Traditional means of controlling radio frequencies such as crystal frequency standards cannot alone maintain this close tolerance at frequencies greater than approximately 20 MHz. Typical crystal oscillator performance over the temperatures encountered in a mobile radio environment ranges from ±5 parts per million (ppm) to ±1 ppm. The cost of the ±1 ppm oscillator is inherently much greater than that of a ±5 ppm oscillator. Considering a VHF frequency of 150 MHz, these tolerances yield frequency errors of ±750 Hz and ±150 Hz respectively.
To resolve this frequency tolerance problem, continuous phase locked loop (PLL) techniques have been widely adopted among single sideband receiver designers Generally, PLL receiver AFC circuits are realized in a loop that includes a first mixer, an intermediate frequency (IF) filter and gain, product detector with associated reference oscillator, a loop filter, and a voltage controlled oscillator (VCO) which in turn accepts a frequency control voltage from the loop filter and produces the local oscillator (LO) signal for the first mixer. The received SSB signal is demodulated by the product detector. The received signal, which may incorporate a frequency error, is correctly located in the IF filter bandpass by means of the natural acquisition characteristics of the PLL. However, such a continuously controlled PLL exhibits a potential for degrading the adjacent channel interference performance as a result of noise which may be present on the VCO control line due to on-channel modulation or adjacent-channel interference. Various methods, such as dual-bandwidth and split loop techniques have been proposed to diminish the loop noise; however, these AFC techniques described previously may have further shortcomings such as poor demodulator performance when the received signal is subject to multipath signal propagation or inferior acquisition performance. For these reasons, the received AFC to be disclosed in further detail herein employs a directed frequency sweep of the LO in conjunction with a "short loop" phase-locked SSB demodulator following the IF filter and gain in order to maximize demodulator performance in a multipath signal environment, to ensure rapid frequency acquisition, and to eliminate LO noise problems.
Classical frequency sweep schemes utilize a low sweep frequency, usually less than one-half the square of the steady state detector PLL natural frequency, thereby permitting enough time for the acquisition and centering of the received signal or low signal levels. At this sweep frequency, however, the time to simply acquire and center the desired signal with the AFC loop becomes unacceptably long (up to 250 msec) and adds to the receiver squelch operation time such that the initial segments of the message may be lost.
In such classical sweep schemes, a lock detector is commonly used to determine when the desired signal, converted to an IF frequency by the swept local oscillator, falls within a predetermined window around the "centered" position in the IF bandpass. When the signal reaches this window, the local oscillator sweep is terminated and any remaining frequency error is typically irnored. The speed of the lock detector is important in acquiring lock; a slow lock indication may allow the signal to sweep past the centering window and not be centered while a fast lock indication may allow perturbations, like noise, to break lock or cause the detector to fail in initially acquiring the signal.
These conflicting lock detector requirements are reconciled by means of a dual time constant lock detector having the time required to sense the lock condition of the PLL significantly shorter than the time required to sense the unlock condition of the PLL. When this lock detector is utilized to control the sweep, squelch activation can begin before centering of the received signal is fully complete, thereby minimizing the time required for activation of the squelch.
It can be appreciated, then, that previous AFC circuits have required a series of compromises to enable their operation. The present invention enables independent optimization of the key AFC parameters and enables single sideband receivers to approach the performance of well-established frequency modulation receivers.
Therefore, it is an object of the present invention to provide a frequency sweep that allows a rapid acquisition of a received signal.
It is a further object of the present invention to retain AFC lock under conditions of noise and fading.
It is a further object of the present invention to begin squelch activation before centering of the received signal so as to minimize the time during which the audio signal is lost at the beginning of a received transmission.
Accordingly, these and other objects are achieved in the present frequency control system for a single sideband receiver. This invention utilizes one rate of local oscillator sweep to acquire a transmitted signal and, once the signal is acquired, a detector indicates the direction a second sweep rate moves the local oscillator frequency to center the signal in the IF bandpass. When the signal is centered, the local oscillator frequency is maintained at the frequency of centering in response to a detection of receiver squelch.
FIG. 1 is a block diagram of a single sideband receiver incorporating the present invention.
FIG. 2 is a graph of carrier frequency offset versus time showing the result of the dual sweep function of the present invention.
FIG. 3 is a block diagram of the AFC circuit in accordance with the present invention.
FIG. 4 is a block diagram of the digital squelch decoder and sweep cancellation circuit.
FIG. 5 is a block diagram of the lock detector and impulse noise detector.
FIG. 6 is a schematic diagram of the digital sweep generator.
FIG. 7 is a schematic diagram of the control line direction detector.
A single sideband receiver employing the automatic frequency control (AFC) circuit of the present invention is shown in FIG. 1. This receiver is a single conversion superheterodyne receiver which is utilized for frequencies in the range of 150 MHz to 175 MHz. An intermediate frequency (IF) of 10.8 MHz is used in the preferred embodiment and two four-pole upper sideband filters 20, 22, having passbands which include both the carrier and sideband modulation, are used to establish the selectivity of the receiver. A phased-locked loop (PLL) quadrature phase detector demodulator, which locks to the carrier and provides a coherent automatic gain control (AGC), consists of a 10.8 MHz voltage controlled crystal oscillator (VCXO) 26, a phase detector 28 having I and Q outputs, and a loop filter 30 arranged in conventional fashion. A disclosure of a similar phase-locked single sideband detector is given in U.S. Pat. No. 3,100,871 assigned to the assignee of the present application.
In practice, the operation of a PLL demodulator extends the frequency tolerance of the receiver to greater than the 20 Hz described earlier. This arises by virtue of the PLL lock range. Unfortunately, the useable range of frequency tolerance is insufficient to account for practical crystal reference oscillator instabilities under worst case conditions. In the preferred embodiment, the crystal oscillators have a ±2 parts per milion (ppm) stability which, when the stability of both the receiver and transmitter and considered, requires the receiver AFC acquisition range to be ±4 ppm or ±700 Hz at the 175 MHz operating frequency.
It is undesirable to increase the AFC range beyond a ±700 Hz to ±900 Hz range even though lower-priced crystal oscillators could be used in the system. This is because the additional frequency drift would, if permitted, allow transmitters on adjacent channels to operate closer together in frequency thereby exacerbating the serious existing problem of adjacent channel interference. With a nominal spacing of 5 KHz between channels, the adjacent channel interference protection degrades as much as 6 dB when the transmitters are as close as permitted by the use of ±2 ppm crystal oscillators. Greater degradation is experienced with crystal oscillators of greater stability ranges. This interference protection degredation applies to conventional transmitters and those with feedback phase and amplitude correction.
In addition to interference, closely spaced signals or an AFC with a wide lock range can cause a receiver to acquire and lock on a strong undesired adjacent channel. The required difference in level between desired and undesired signals which must be maintained so as to ensure that acquisition of the desired signal will always take place is referred to as the protection ratio. The protection ratio increases rapidly as the AFC range is increased and the frequency spacing between the desired and undesired transmitter frequencies becomes larger.
Another interference problem is that of cochannel interference. The AFC may acquire and lock on an undesired signal being transmitted on the channel and then be presented with a desired signal, perhaps offset in frequency from the undesired signal. The required difference in level between the desired and undesired signals which must be maintained to ensure that the receiver acquires and locks on the desired signal is known as the cochannel interference protection ratio. If an AFC with a ±1000 Hz range is used in a receiver, the cochannel interference protection ratio required is between 30 and 35 dB whereas if an AFC of ±700 Hz is used, the cochannel protection ratio requirement is reduced to 20 dB. In the preferred embodiment of this invention, a sweep range of ±865 Hz is utilized thereby allowing margin over the minimum ±700 Hz defined by a combined receiver-transmitter stability of ±4 ppm but not approaching a lock range which seriously degrades the required cochannel protection ratio.
Referring again to FIG. 1, a digitally-controlled sweep voltage generator 32 varies the oscillation frequency of a 14.4 MHz voltage controlled crystal reference oscillator (VCXO) 34 such that the synthesized local oscillator 36 frequency sweeps back and forth across the ±865 HZ so that a transmitted signal within this range can be positioned in the IF bandpass.
A received frequency is considered "centered" when the carrier and the single sideband modulation are contained within the IF filter bandpass and the demodulated frequency error is less than 100 Hz. Control of the sweep voltage generator 32 is exercised via five control lines from three detectors. These detectors, which will be described in more detail later, are the lock detector 38, the PLL VCXO control line direction comparator 40, and the combination of the digital squelch detector 42 and carrier squelch detector 44.
Because a desired carrier may appear outside the IF filter passband, the local oscillator frequency is swept across the entire AFC frequency range to enable the desired carrier to be found. In this particular embodiment, a digitally generated triangular voltage yields a ±865 Hz total frequency excursion at the local oscillator output in 256 discrete frequency steps of 6.7 Hz each. The rate of sweep has traditionally been established by the PLL natural frequency, such that the sweep frequency is less than one-half the square of the PLL natural frequency. Generally, this results in a slow sweep and unacceptably long signal centering times in conventional AFC implementations, particularly when the signal experiences the rapid fading common at VHF frequencies.
When a carrier first appears within the IF bandwidth of the receiver of FIG. 1, it may be momentarily at a level higher than the steady-state level it will attain when the AGC circuit 46 reduces the receiver gain in the well-known AGC operation. Typical AGC circuits are described in U.S. Pat. No. 4,013,964 and U.S. patent application Ser. No. 534,512 (Automatic Gain Control Responsive to Coherent and Incoherent Signals) filed in behalf of Eastmond on Sept. 21, 1983, both assigned to the assignee of the present application. This transient increase in the IF amplitude above the normal level may be augmented by a transmitter keying circuit which causes the single sideband transmitter to transmit at full peak envelope power for an initial period of time. It has been found possible to use higher sweep rates in the preferred receiver as a direct consequence of this transient increase in the IF amplitude. Specifically, both the natural frequency of the loop and the damping factor of the loop are related to the square root of incremental increases in level of the IF signal thereby allowing an increase in the sweep frequency because of the increase in natural loop frequency. Therefore, a sweep rate frequency of 15 Hz in the preferred embodiment allows reliable signal acquisition at threshold carrier levels as low as -134 dBm when a signal level boost is present. However, because the higher than normal signal is reduced when the detector PLL locks and the AGC operates, the sweep rate is reduced to a slower rate, for example 5 Hz, to permit reliable centering of the signal when the signal level attains its lower steady-state value.
If a long fade should cause the receiver to loose AFC lock and the signal subsequently returns, a signal strength boost may not be present. In this instance, the AFC sensitivity may be increased by holding the local oscillator sweep rate at the 5 HZ rate for a short period of time, which may be 2 seconds, following lock loss. This sweep rate hold is reset if the transmitter is keyed thereby permitting rapid signal acquisitions during message exchanges occurring in less than the hold period. Thus in the preferred embodiment, on long signal fades a high AFC sensitivity is briefly maintained which may be defeated by a keying of the transmitter.
FIG. 2 diagrams the unique dual sweep voltage as a function of time. It can be seen that without a received signal, the sweep continues to vary the local oscillator frequency above and below its nominal frequency. When a signal is applied, the AFC acquires the signal within a lock time 47. At this point a slower, 5 Hz, sweep is applied in a direction indicated by direction control comparators 40 until the signal is centered and the "on-frequency" control line is activated.
A more detailed block diagram of the AFC is shown in FIG. 3. As previously described, until a signal appears, the digital sweep voltage generator 32 sweeps the local oscillator frequency with a triangular waveform at a frequency of 15 Hz. When a signal appears and the AFC begins the acquisition process, the lock detector 38 senses the beat note between the centered frequency and the received signal and outputs a level or unitary output which causes the sweep voltage detector 32 to convert the sweep freqnency from 15 Hz to 5 Hz and which enables the direction control comparators 40 on the PLL VCXO 26 control line so as to provide information to the sweep voltage generator 32 indicating whether the desired signal is too high, too low, or centered on frequency. Once correct centering of the signal has been achieved, all sweep is stopped and squelch detect signals override all other inputs to the sweep controller thereby holding the local oscillator frequency constant. In this way noise present on the other control inputs is prevented from reaching the local oscillator and degrading the adjacent channel interference protection.
This use of a dual-frequency sweep improves the initial signal acquisition but the use of a slower centering sweep frequency has the potential of degrading the speed of squelch operation. Digital squelch is a common method of selective receiver muting in frequency modulation equipment used in the land mobile bands and typically consists of user-specific code words transmitted in an NRZ format at a low-speed bit rate, although higher speeds and modulated pilots may also be used. A single sideband system employing coded squelch is disclosed in U.S. patent application Ser. No. 564,815 Eastmond, et al. (A SSB System with Pilot Carrier Coded Squelch) filed in behalf of Eastmond, et al. on Dec. 22, 1983 and assigned to the assignee of the present application. Because of the data, the low frequency response of the transmission/reception medium must extend to nearly 1 Hz to ensure that the detection sensitivity is uniform for all codes. The input to the digital decoder incorporates a comparator which is referenced to the mean value of the data signal so as to avoid comparator "latch-up" at large steady state values of frequency offset. However, when the sweep voltage appears on the PLL VCXO 26 in addition to the desired signal, as it is during centering, digital squelch detection is disrupted because the mean value is changing fast enough under these conditions to cause comparator latch-up. It is not feasible to wait until centering is complete to begin digital squelch detection since this results in excessive squelch opening times. The lock gated sweep cancellation circuit 48 of the preferred embodiment permits digital squelch detection to commence at the start of the centering process.
The sweep cancellation circuit is detailed in FIG. 4. A standard digital squelch decoder 50 (for example a TLN 2349A decoder manufactured by Motorola Inc.) is preceeded by a cancellation network which is enabled via "or" gate 51 from the lock detector 38 and switch 52 (which may be an MC14066UB circuit manufactured by Motorola Inc.). The sweep voltage and the phase detector 28 VCXO control line are connected via operational amplifiers 53, 54 to realize cancellation of the sweep voltage impressed on the phase detector 28 PLL VCXO control line by the sweep voltage at the input to the digital squelch decoder 50, thereby leaving a residual consisting of digital code to be detected. The digital code is not disturbed by the cancellation; thus, detection may begin as soon as the AFC acquires the signal. Prior to the cancellation process, the input to the digital squelch detector is maintained at the nominal center voltage of PLL VCXO 26 by the action of lock detector 38.
Returning to FIG. 3, the relation of the lock detector circuit 38 to the other structures of the receiver can be ascertained. Outputs from the lock detector 38 are connected to the sweep voltage generator 32 to cause the sweep frequency to convert from 15 Hz to 5 Hz, to the sweep direction comparators 40 to enable monitoring of the control line, and to the sweep cancellation circuit of the digital squelch detector to enable the sweep cancellation. Inputs to the lock detector 38 include a filtered (preferably via 3-pole 150 Hz corner Butterworth filter 55) signal from the Q output of phase detector 28 and an input from the AGC detector 46. The signal present at the Q output of the Phase detector 28 is a beat-note frequency equal to the difference between the received signal and the 10.8 Mhz PLL VCXO 26. This beat-note is filtered by the low pass filter 55 before being presented to the lock detector 38 so that signals greater than 150 Hz, which cannot be tracked by the quadrature detector PLL 26, do not cause a lock detection.
Three major functions comprise the lock detector 38: a full wave rectifier 56, a filter and comparator 57, and an impulse noise detector 58. Referring now to FIG. 5, details of the preferred lock detector can be seen. Input is taken from the low pass filter 55 and full wave rectified by the conventional active full-wave rectifier 56. This novel use of a full-wave rectifier consisting of conventional operational amplifiers and diodes increases the reliability of the beat-note lock detector and ensures that transients due to excitation of the low pass filter 55 always enhance, rather than occasionally degrade, the reliability of the lock detector indication. Lock detection, or detection of AFC signal acquisition, is accomplished by a dual time constant low pass filter (consisting of a charge storing capacitor 60, a charging resistor 61, an isolating diode 62, and a discharge resistor 63) and a comparator 64, which can be an M2121 manufactured by Motorola Inc. and commonly associated circuitry. The selection of time constants for the filter includes consideration of detection speed and lock hold time. The detect time, or charge time, of the filter is a trade-off between a low falsing rate on noise and reliable beat-note detection at low carrier levels. The charge time constant used in the preferred embodiment is 12.5 msec which is large considering that the 15 Hz sweep frequency is equivalent to 52 Hz per msec over the nominal ±865 Hz sweep range but is feasible because the receiver is at a maximum AGC gain at the time of acquisition. The output of the dual time constant filter is therefore able to trigger the comparator 64 faster than a steady state AGC gain would allow because of the larger signal level.
The dual time constant filter decay time, or hold time, which is determined by capacitor 60 and the sum of resistor 63 and resistor 61, is important during signal fading. If the decay time were equal to the charge time, the lock detector would frequently fail after signal acquisition in the presence of fading, especially at high fading rates. After loosing lock, the local oscillator sweep would be forced to resume sweeping and an appreciable delay would be inserted into a voice transmission. In order not to degrade the charging time constant, the decay time was made independent of the charge time and long enough to hold lock indication through the signal fades. The decay time constant was experimentally optimized such that no failures of lock were observed with a simulated 70 MPH fading rate at VHF frequencies. This dictated a decay time of 165 msec.
Although the addition of a substantial hold time solved the problems encountered in a fading envorinment, it raised a question of whether the lock detector would latch-up when exposed to impulse noise such as ignition noise. Experiments proved that impulse noise would result in latch-up and result in acquisition problems under some conditions. Consequently, an impulse noise detector 58 was placed at the detector output of the AGC control circuit 46 in the preferred embodiment to detect the presence of impulse noise and to reduce the hold time of the dual time constant filter 56. The impulse noise detector 58 consists of a conventional single pole high pass active filter 65 with a corner at 32 Hz to remove the lower frequency modulation components such that the threshold of a standard comparator 66 which follows the filter 65 may be adjusted to singularly detect impulsive noise spikes. Because the resultant spikes at the comparator 66 are very short in duration, a monostable 68 (an MC14538B by Motorola Inc. or equivalent) in standard configuration is used to stretch these pulses prior to filtering. A dual time constant fast attack/slow decay filter 70 is used, like the dual time constant filter of the lock detector filter, to allow independence of attack and decay although the time constants of the impulse detector filter 70 may be made longer. The threshold of the conventional comparator 72 is set to provide a reliable detection level and the comparator 72 output is coupled to a semiconductor switch 74 in the lock detector dual time constant filter (which may be an MC14066UB manufactured by Motorola Inc.) which applies a resistor 75 in shunt with discharge resistor 63 in order to reduce the decay time constant in the presence of impulse noise.
The digital sweep generator 32 schematic is shown in FIG. 6. This sweep generator is realized using two CMOS 4-bit up/down counters 80, 82 (such as an MC14516B manufactured by Motorola Inc.) configured to produce an 8-bit output which is sequentially incremented up and down between binary 0 and binary 255 in 256 increments. The output of the counters 80, 82 is level shifted in networks 84 and 86, which may be conventional diode-resistor networks, and passed to a digital-to-analog (D/A) converter 88. The carry output from the most significant bit counter 82 is inverted in "OR" gate 90 and "ANDED" with clock output of bit counter 82 via "OR" gate inverter 92 in "AND" gate 94 to control a conventional "D" flip-flop 96. The "Q" output from the flip-flop 96 controls the count direction (up or down) of the counters 80, 82. Flip-flop 96 is also toggled by a sweep low command signal input to the "set" port or by a sweep high command input to the "reset" port. Counting is halted by switching the carry-in port of the least significant bit counter 80 in response to an inverted (via "OR" gate 98) squelch hold signal.
The D/A converter 88 is an 8-bit multiplying D/A converter, such as an MC1508 manufactured by Motorola Inc., providing a current output which is a product of the digital word input and an analog reference voltage. Thus a triangular current waveform is generated by converter 88 as the counters 80, 82 count sequentially up and down. The current waveform is converted to a voltage sweep waveform by conventional operational amplifier 100 and coupled to the local oscillator reference VCXO 34 via RF filter 102.
An integrated circuit oscillator 104 (an MC1555 by Motorola Inc. or equivalent) is used as the clock for the counters and preferentially oscillates at a frequency 512 times the desired clock frequency. Since it is desired that two clock frequencies, 15 Hz and 5 Hz, be used in the radio local oscillator sweep, a switchable timing resistance is used in the RC timing circuit 108. An inverted lock indication from the lock detector 38 activates integrated circuit switch 106 (an MC14066UB manufactured by Motorola Inc.) which decreases the resistance in the timing circuit 108 and causes the time constant of the oscillator circuit to create a 2560 Hz frequency of oscillation rather than a 7680 Hz frequency of oscillation (corresponding to a 5 Hz and 15 Hz sweep respectively). The sweep frequency is subsequently coupled to the local oscillator reference VCXO 34 to vary the local oscillator frequency.
Frequency sweep control inputs to the sweep voltage generator 32 come from the VCXO direction control comparators 40, shown in detail in FIG. 7. A lock signal from the lock detector 38 is input to inverter 112 and coupled to the switch 106 of sweep voltage generator 32. The inverted lock signal is reinverted by inverter 114 and coupled to one input of each "AND" gate 116, 118, 120 for sweep control. To determine whether the sweep should be positive or negative going, two comparators 122, 124 are used to detect positive control line excursions (comparator 124) or negative control line excursions (comparator 122). In the preferred embodiment, the comparators 122, 124 are part of an MC3302 quad single supply comparator but the comparator function could be performed by operational amplifiers equally successfully.
The VCXO control line input is filtered by a low pass filter 125 and isolated by amplifier 126 before being applied to the comparators 122, 124. The reference voltage for the direction control comparators 122, 124 is the same voltage as is used for the quadrature PLL phase detector 28 in order to avoid DC drift problems. The threshold of the comparators 122 and 124 are set by potentiometers 127, 128 respectively so as to define a ±100 Hz "on-frequency" window which is justified to 0 Hz error by the detector PLL. The output of negative comparator 122 is "ANDED" with the lock signal in gate 116 and presented to the set port of "D" flip- flop 96 to cause the sweep frequency to increment sequentially lower when the threshold of comparator 122 is crossed. Alternately, the output of comparator 124, which is inverted in 130 is, "ANDED" with the lock signal in gate 118, and presented to the reset port of the flip-flop 96 to cause the sweep frequency to increment sequentially higher when the threshold of comparator 124 is crossed. An on-frequency signal, as determined by either a lock indication concurrent with neither sweep direction line being activated or a squelch detection, is made by "OR" gate 132 and coupled to the squelch hold (on-frequency) input of sweep voltage generator 32 via the inverted carry-in port of the up/down counter 80.
Squelch detection, in the preferred embodiment, is a digital squelch detector 50 output but may also be a standard carrier squelch activation. In practical operation it is necessary to logically "and" the digital squelch and the carrier squelch to prevent noise falsing of the digital squelch system from being a problem. This "anding" degrades the opening times slightly at carrier levels below -132 dBm but since the minimum usable signal is -125 dBm or greater, this degredation is of no consequency. The results are well within the desired limits of signal acquisition and squelch opening performance and compare favorably with currently existing frequency modulation equipment for land mobile services. As one might expect, the squelch opening time becomes greater as the initial signal offset becomes greater.
While a particular embodiment of the invention has been described and shown, it should be understood that the invention is not limited thereto since many modifications may be made. It is therefore contemplated to cover by the present application any and all such modifications that fall within the true spirit and scope of the basic underlying principles disclosed and claimed herein.
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U.S. Classification 455/701, 455/260, 455/166.1, 455/203
International Classification H04B1/30, H03J7/04, H04B1/68
Cooperative Classification H04B1/302, H03J7/047, H04B1/68
European Classification H04B1/30B, H03J7/04C, H04B1/68
Owner name: MOTOROLA, INC., SCHAUMBURG, ILL A DE CORP
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:RICHARDSON, JULIAN H.;EASTMOND, BRUCE C.;REEL/FRAME:004358/0355

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Bizarre Fables by Gary Bills, Heather E Geddes |, Paperback | Barnes & Noble® B&N Top 100 NY Times Bestsellers
by Gary Bills, Heather E GeddesGary Bills
True collaboration is often a strange business and in the case of the "Bizarre Fables", the collaboration was between husband and wife. Heather would draw and paint, while the plots developed organically. Gary and Heather shared their visions, day after day and night after night, while the owls hooted incessantly from nearby trees and barns.
The plots developed organically, naturally. From Heather came the idea of a gross man who would find himself pregnant, - the theme of "Bread for Toggle". Also from Heather came the initial idea of a powerful old woman whose soul was captured in a box - a box that was then bound tight with briar. She actually dreamed this, and her husband, Gary, who wrote all the fables, was inspired by her dream. This, of course, was the origin of "Grandma's Soul". There were other strange happenings surrounding the genesis of these tales. The story called "The Blossom Maker" was written in just two hours, as if the writer was taking dictation from a spirit.
9781984297914

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Ferndale, MD Paint & Wall Coverings
Paint & Wall Coverings near Ferndale	Baltimore
1,432 Ferndale, MD Paint, Wallpaper and Wall CoveringsMany builders, designers and DIY experts say that painting is one of the easiest tasks for a homeowner to handle. But plenty of prep work, elbow grease and finesse are involved, and if you don’t have the time, ability or inclination to complete a painting job, hiring a professional is the way to go. Plus, speciality paint treatments, wallpaper and other wall coverings, such as grass cloth, are tricky. Your Ferndale, MD home may need help from a Maryland pro to make any of those happen. You can find more paint & wall coverings in Baltimore, Columbia, Ellicott City, Dundalk and Bowie. More View Ashburn, VA professionals near
Wow Effects-Murals and Fine Art
9 Reviews	(410) 903-7696	Centreville, VA, 20121, United States50 miles from Ferndale
Fine Artist, Tom Taylor started his murals/muralist art business, "Wow Effects," in 1999 and has since been painting award winning murals, trompe l’oeil murals, fine art... Read More Casart Coverings
10 Reviews	889605554	Alexandria, VA, 22314, United States35 miles from Ferndale
Original hand-painted, custom, designer, decorative finishes & murals printed as repositionable, removable and reusable wallcoverings. Slipcovers for Your Walls! Customizable peel... Read More LPDesigns
19 Reviews	(240) 418-9960	Olney, MD, 20832, United States24 miles from Ferndale
At LP Designs we strive to evoke the best of your space with thoughtful, personalized color palettes. Our clients are not simply selecting paint chips; they are witnessing the... Read More ANDY'S PAINTING
12 Reviews	(301) 869-8121	Gaithersburg, MD, 20879, United States30 miles from Ferndale
We provide quality interior/exterior painting, wallpaper removal, drywall repair, stain/varnish and we also power wash houses and finish decks. Est. in 1980 and family owned. We... Read More Hömm Certified Painting Systems
28 Reviews	(866) 701-7077	Alexandria, VA, 22302, United States35 miles from Ferndale
Locally owned company offering high-quality painting services and superior customer service in the Washington, DC metro area. Read More Williams Professional Painting
6 Reviews	(703) 768-8143	Alexandria, VA, 22304, United States37 miles from Ferndale
We are a family owned and operated professional painting company serving Northern Virginia and Washington DC since 1979. We provide expert interior and exterior painting services... Read More Performance Painters LLC
17 Reviews	(703) 919-7426	Fairfax, VA, 22030, United States44 miles from Ferndale
Performance Painters was started in 2001 by our owner, Dennis Salvatore. Originally named Painting by Dennis, the name was changed as the company grew to include multiple teams of... Read More The Great Cover Up- Shawn DeVoe
7 Reviews	(410) 420-3668	Bel Air, MD, 21015, United States30 miles from Ferndale
Professional painter with 30+ years of experience Read More Hands On Painters Inc.
4 Reviews	(410) 242-1737	Baltimore, MD, 21229, United States8 miles from Ferndale
Hands On Painters Inc., one of Maryland’s most trusted privately owned painting and handyman service providers with over 15 years in the business. Now celebrating over 5,000 homes... Read More CertaPro Painters of Columbia
1 Review	(443) 535-1270	Columbia, MD, 21045, United States11 miles from Ferndale
You've probably seen us in your neighborhood painting exteriors and you may have seen our neighborhood CertaPro Painters signs. Now that it's time to paint the house let us have... Read More Monarch Paint & Wallcovering Decor
1 Review	(202) 525-3468	Washington, DC, 20015, United States28 miles from Ferndale
Monarch Paint & Wallcovering offers a complete Home Decorating Center at our Chevy Chase location. You have access to all top design Houses in Wallcovering and Fabrics as well as... Read More Michel Painting LLC
1 Review	(703) 869-3688	Alexandria, VA, 22302, United States35 miles from Ferndale
Michel Painting LLC offers the best service of its kind in the area. We take pride in our work and aim to put a smile on your face upon completion of every job. We are licensed... Read More Kami Tremblay Design, LLC
1 Review	(443) 799-9583	Arlington, VA, 22205, United States34 miles from Ferndale
Kami Tremblay Design, LLC is a full service decorative painting firm. Since 1997, she has completed over 700 decorative painting and design projects for over 250 clients in the DC... Read More ProPaint Systems
3 Reviews	(410) 882-6288	Forest Hill, MD, 21050, United States30 miles from Ferndale
Painting contractor Read More McCormick Paints
3 Reviews	(301) 770-3235	Rockville, MD, 20851, United States27 miles from Ferndale
McCormick Paints is a preferred paint manufacturer and retailer dedicated in serving both professionals and homeowners alike. For over 50 years, architects and designers, painting... Read More List your business here for free - Learn More 1234567891011Next Page What Does a Paint and Wall Covering Contractor Do?Paint and wall covering contractors are experts in the specs, application and removal of paint, wallpaper and other wall coverings. They can help you choose the paint color and finish, wallpaper style or specialty covering that best suits the needs of your Ferndale, MD home, whether the job is for the interior or exterior. In addition, they can strip off old paint or paper and prepare surfaces through sanding, skim coating and other processes. Many can handle decorative paint treatments and materials such as plaster.
A paint and wall covering contractor might work closely with Ferndale, MD interior designers, builders and others, too. Here are some related professionals and vendors to complement the work of paint & wall coverings: Interior Designers & Decorators, Artists & Artisans, Window Treatments, Carpet & Flooring.
Find a paint and wall covering contractor on Houzz. Narrow your search in the Professionals section of the website to Ferndale, MD paint and wall coverings. You can also look through Ferndale, MD photos to find examples of paint jobs and wall coverings that you like, then contact the professional who worked on them.	Professional Categories in Ferndale
Ferndale Residential Contractors · Ferndale Architect & Contractors · Ferndale Interior Decorators · Ferndale Home Designers · Ferndale Kitchen Designers · Ferndale Kitchen & Bath Remodelers · Ferndale House Builders · Ferndale Landscapers · Ferndale Licensed Landscape Contractors · Ferndale Tile Studios · Ferndale Cabinets & Cabinetry · Ferndale Furniture Makers · Ferndale Carpet Installer · Ferndale Residential Paint And Wall Coverings · Ferndale Decks, Patios & Outdoor Enclosures · Ferndale Pool Suppliers · Ferndale Carpenters · Ferndale Doors · Ferndale Garage Doors · Ferndale Custom Closet Designers	· more...
· Ferndale Lighting · Ferndale Window Treatments · Ferndale Windows · Ferndale Design Photographers · Ferndale Roofing & Gutters · Ferndale Siding & Exterior Contractors · Ferndale Muralist · Ferndale Appliance Distributors · Ferndale Bed Linens · Ferndale Hardware Supplies · Ferndale Carpenters · Ferndale Driveways & Paving · Ferndale Electrical Contractors · Ferndale Environmental Services & Restoration · Ferndale Fencing & Gates · Ferndale Custom Hearth · Ferndale Nursery · Ferndale HVAC Contractors · Ferndale Sound System Design & Installation · Ferndale Residential Stagers · Ferndale Ironwork · Ferndale Nursery Designers · Ferndale Cabinetry · Ferndale Lawn & Sprinklers · Ferndale Publishers · Ferndale Outdoor Audio/Visual · Ferndale Outdoor Play Systems · Ferndale Plumbing Contractors · Ferndale Rubbish Removal · Ferndale Septic Tanks and Systems · Ferndale Solar Energy Contractors · Ferndale Sport Courts · Ferndale Staircases · Ferndale Stone, Pavers & Concrete · Ferndale Tree Services · Ferndale Real Estate Agents · Ferndale Upholstery · Ferndale Wine Cellars	Professional Metro Areas

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