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Fusiliers: The Saga of a British Redcoat Regiment in the American Revolution book by Mark Urban | 2 available editions | Alibris Books
The American Revolution from a unique perspective--as seen through the eyes of a redcoat regiment. From Lexington Green in 1775 to Yorktown in 1781, one British regiment marched thousands of miles and fought a dozen battles to uphold British rule in America: the Royal Welch Fusiliers. Their story, and that of all the soldiers England sent across the Atlantic, is one of the few untold sagas of the American Revolution, one that sheds light on the war itself and offers surprising, at times unsettling, insights into the way ... Read More
The American Revolution from a unique perspective--as seen through the eyes of a redcoat regiment. From Lexington Green in 1775 to Yorktown in 1781, one British regiment marched thousands of miles and fought a dozen battles to uphold British rule in America: the Royal Welch Fusiliers. Their story, and that of all the soldiers England sent across the Atlantic, is one of the few untold sagas of the American Revolution, one that sheds light on the war itself and offers surprising, at times unsettling, insights into the way the war was conducted on both sides. Drawing on a wealth of previously unused primary accounts, and with compelling narrative flair, Mark Urban reveals the inner life of the 23rd Regiment, the Fusiliers--and through it, of the British army as a whole--as it fought one of the pivotal campaigns of world history. Describing how British troops adopted new tactics and promoted new leaders, Urban shows how the foundations were laid for the redcoats' subsequent heroic performance against Napoleon. Fighting the climactic battles of the Revolution in the American south, the Fusiliers became one of the crack regiments of the army, never believing themselves to have been defeated. But the letters from members of the 23rd and other archival accounts reveal much more than battle details. Living the Revolution day-to-day, the Fusiliers witnessed acts of kindness and atrocity on both sides unrecorded in histories of the war. Their observations bring the conflict down to human scale and provide a unique insight into soldiering in the late eighteenth century. Fusiliers will challenge the prevailing stereotypes of the enemy redcoats and offer an invaluable new perspective on a defining period in American history. Read Less
ISBN-13: 9780802716477
ISBN: 0802716474
Alibris ID: 13492949235
Very good in very good dust jacket. Clean copy. Tight binding. Glued binding. Paper over boards. With dust jacket. 384 p. Contains: Illustrations, black & white, Illustrations, color, Maps. Audience: General/trade.
Alibris ID: 14742991435
Alibris ID: 14835688398
ISBN-13: 9780802716880
ISBN: 0802716881
Alibris ID: 14860688573
Alibris ID: 14760209703
Alibris ID: 14847721985
Alibris ID: 14736151860
Alibris ID: 14715362129
Alibris ID: 14578020750
Alibris ID: 14782569141
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9780802716880
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Patent US6217547 - Lubricous and readily bondable catheter shaft - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn intraluminal catheter, particularly a dilatation catheter for angioplasty procedures, which has a shaft section formed of a blend of lubricous and bonding polymeric components in proportions to maintain a low coefficient of friction while maintaining the ability to bond non-lubricous polymeric material,...http://www.google.com/patents/US6217547?utm_source=gb-gplus-sharePatent US6217547 - Lubricous and readily bondable catheter shaftAdvanced Patent SearchPublication numberUS6217547 B1Publication typeGrantApplication numberUS 09/289,433Publication dateApr 17, 2001Filing dateApr 9, 1999Priority dateJan 16, 1996Fee statusPaidPublication number09289433, 289433, US 6217547 B1, US 6217547B1, US-B1-6217547, US6217547 B1, US6217547B1InventorsJeong Soo LeeOriginal AssigneeAdvanced Cardiovascular Systems, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (30), Referenced by (15), Classifications (12), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetLubricous and readily bondable catheter shaft
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polyimide layerUS20110172599 *Mar 28, 2011Jul 14, 2011Boston Scientific Scimed, Inc.Catheter having an improved balloon-to-catheter bondWO2005072787A1 *Jan 5, 2005Aug 11, 2005John J ChenCatheter having an improved balloon-to-catheter bondWO2014107178A1 *Mar 6, 2013Jul 10, 2014St. Jude Medical Puerto Rico LlcRapid exchange temporary blood flow cessation device for large bore closure* Cited by examinerClassifications U.S. Classification604/96.01, 604/103International ClassificationA61L29/14, A61M29/02, A61L29/04Cooperative ClassificationA61M25/104, A61L29/049, A61L29/14, A61M2025/1056European ClassificationA61L29/04M, A61M25/10P, A61L29/14Legal EventsDateCodeEventDescriptionSep 27, 2012FPAYFee paymentYear of fee payment: 12Sep 18, 2008FPAYFee paymentYear of fee payment: 8Oct 18, 2004FPAYFee paymentYear of fee payment: 4Apr 9, 1999ASAssignmentOwner name: ADVANCED CARDIOVASCULAR SYSTEMS, INC., CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, JEONG S.;REEL/FRAME:009894/0267Effective date: 19990405RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services

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The Shocking Truth about Energy book by Loreen Leedy | 2 available editions | Alibris Books
Books Children's Nonfiction Science & Nature Environmental Conservation & Protection Hardcover The Shocking Truth about Energy
14101083453
14129755299
14037393589
14113529231
14113558318


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Patent US7229309 - Network connection system - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA network connection system for connecting computer network components, the network connection system including a twisted pair cable having multiple conductors in twisted pairs a cable termination connector affixable at an end of the cable. The cable termination connector includes a slender elongate...http://www.google.com/patents/US7229309?utm_source=gb-gplus-sharePatent US7229309 - Network connection systemAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7229309 B2Publication typeGrantApplication numberUS 11/159,695Publication dateJun 12, 2007Filing dateJun 23, 2005Priority dateJun 24, 2004Fee statusLapsedAlso published asUS20050287873, WO2007084095A2, WO2007084095A3Publication number11159695, 159695, US 7229309 B2, US 7229309B2, US-B2-7229309, US7229309 B2, US7229309B2InventorsJames A. Carroll, Thomas R. FinkeOriginal AssigneeJames A. CarrollExport CitationBiBTeX, EndNote, RefManPatent Citations (46), Non-Patent Citations (3), Referenced by (39), Classifications (17), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetNetwork connection system
US 7229309 B2Abstract
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MattsonConnector with slideable retention feature and patch cord having the same* Cited by examinerClassifications U.S. Classification439/418, 439/460, 439/941International ClassificationH01R24/58, H01R4/24, H01R13/506, H01R24/00Cooperative ClassificationY10S439/941, H01R24/64, H01R2201/04, H01R13/585, H01R4/2404, H01R13/506, H01R2201/06, H01R13/6463European ClassificationH01R23/02B, H01R23/00BLegal EventsDateCodeEventDescriptionOct 19, 2005ASAssignmentOwner name: CARROLL, JAMES A, MINNESOTAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FINKE, THOMAS R;REEL/FRAME:016659/0251Effective date: 20051007Jan 17, 2011REMIMaintenance fee reminder mailedJun 12, 2011LAPSLapse for failure to pay maintenance feesAug 2, 2011FPExpired due to failure to pay maintenance feeEffective date: 20110612RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services


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breathtaking tulips! - Review of The Butchart Gardens, Central Saanich, British Columbia - TripAdvisor
breathtaking tulips! - The Butchart Gardens
“breathtaking tulips!”
breathtaking tulips!
Just had to add my glowing review of my visit to Victoria B.C. in May 2007 for the most amazing spectacular, knock your eyes out colors of tulips I've ever seen in my life. From the moment we drove up the driveway to the parking lot, the landscapings and plantings were arranged in the most beautiful colors. I'm sure the place is beautiful year round, but on this particular visit it was right at the height of the tulips in bloom and that was totally amazing. Worth the ferry ride from Seattle for a visually beautiful visit.
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Write a ReviewReviews (9,563)
8,778 - 8,782 of 9,573 reviews
Breathtakingly beautiful in May sunshine
Having heard, and seen, so much about the Butchart Gardens before going, I was concerned they would not live up to the image I had created of them in my mind but they far, far exceeded my expectations. They have to be, the most beautiful and stunning gardens I have been privileged to see anywhere in the world.
I didn't think the entry price was overly high ($25 Canadian) considering what you can pay in the UK nowadays to view gardens and parks. To me it was worth every cent.
It appeared an advantage going mid May, as the gardens were not overly busy, and it was easy to walk around, photograph or just admire the flowers at will. The gardens were a blaze of colour - apart from the Japanese one which was more subtle and calming but none the less beautiful. People just gasped as they walked around the corner and saw the sunken garden for the first time - as a result of our visit, I would highly recommend May and tulip time to view the gardens (our guide told us that the start of June is probably not the best time to visit as the flowers are being changed over) although I'm sure they are stunning at other times of the year as well.
It was a scorching hot day when we went and the Italian ice cream on sale at the end of the walk around went down very well! Other refreshements and food were available and the gift shop was huge and full of varied souvenirs to buy.
It was a bit of a journey to get there from Vancouver via the ferry (there are other alternatives) but worth it without doubt. Coupled with a visit to delightful Victoria the whole day was one of the highlights of our trip to Canada.
Ask dedicatedtraveller about The Butchart Gardens
jemangepdx2 Portland, Oregon
Yes, it is pretty. But expect A LOT of people clogging up the paths taking pictures. And we didn't even go during the peak season.
The Japanese Garden and Sunken Garden were very nice. Maybe it was just me and my companion, but the Italian Garden was very underwhelming. Perhaps it is better in the high Summer?
The roses in the Rose Garden were not blooming yet, so that was kind of a wash.
Price paid for 2 adults to visit the garden in Mid-May? $50. Would we go again? Probably not. It seemed a bit of a tourist trap to me, but ymmv, of course. Just be aware of the admission price before you go and that it will probably be way crowded.
Ask jemangepdx2 about The Butchart Gardens
Linnybee North Vancouver, Canada
During a recent trip to Victoria we decided to go to Butchart Gardens. We were a little hesitant to go because of the price but, it is well worth the cost of admission. There was almost too much to see! The sunken garden is just unbelievable, we spent alot of time in this area just strolling through the many paths and around the pond. We also climbed up to the look out atop a big rock in the centre of the garden for great birds eye views of the sunken garden. As you are leaving the sunken garden there is an massive, amazing water fountain called the Ross fountain. Be sure to sit a while and take in the water show that it produces. The other gardens were just as spectacular. We loved the Japanese garden, the star fountain and the Italian garden. The rose garden was not in bloom yet but, it was filled with seasonal flowers such as tulips and hyacinth. And I can't imagine how fantastic it must be when all the roses are in bloom! My advice is take your time, there is so much to see! We sat down several times during our visit and just tried to take it all in. A lovely place to sit is infront of the sturgeon fountain, beautiful. The gift shop is HUGE and there are several different places to eat in the gardens however, we didn't eat while we were there. We really enjoyed the Gardens and would highly recommend going. I would love to come back in some of the other seasons to see how the park changes throughout the year and also to see the rose garden in full bloom in the summer!
Ask Linnybee about The Butchart Gardens
3 Thank Linnybee
Amazing Gardens but poor information center
My 2nd favorite garden ever! The paths are easily followed so you can see the entire garden. In mid-September the flowers were still in great shape. Absolutely beautiful. Watch out for the information center though. I spoke with 3 different information workers and not one of them told me it would take at least 15 minutes to get a taxi. So despite knowing when I had to catch the BC Ferry in Swartz Bay, they told me to come to their desk at 5:10 to call for the taxi. We did so and did not get the taxi until 5:30. It is a 35 minute taxi to Swartz Bay –but our taxi cab driver zoomed up there by 5:50! We thought we made it ---but we were misinformed by 3 of the Butchart info persons that the Ferry would leave at 6pm. It was actually 7pm because the scheduled had changed for this season. My advice – get Pacific Coach Lines to take you everywhere. We would have saved a lot of money and time.
Ask John H about The Butchart Gardens
Butchart_Gardens, Public Relations at The Butchart Gardens, responded to this reviewResponded November 14, 2007
I was sorry to read of a recent issue raised of obtaining a taxi at The Butchart Gardens.
As an employee of The Gardens I know staff take great pride in providing useful and timely information to many thousands of visitors each year. As might be expected, taxi availability does vary upon the time of day and the weather. I've brought the matter to the attention of our Visitor Services supervisor to ensure we offer better cautions on how long it may take to obtain a taxi. As we do not have any affiliation with taxi companies the timeliness of service remains out of our control.
Ferry schedules change with some frequency and we do work to ensure we have the most recent information for visitors. We will redouble our efforts in ensuring current schedules are available to staff.
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www.rightmove.co.uk/property/55573317
TWO RECEPTION ROOMS.........We welcome to the market this well presented three bedroom semi detached house situated on Baxter Avenue, Fenham. Briefly comprising of entrance hall, lounge, dining room, kitchen, Stairs to first floor land, bathroom Separate w.c, Three bedrooms. Externally there are gardens to front and rear elevations. This ideal family is a must see, It has gas central heating via combination boiler, UPVC windows and is located near the popular West Road. Viewings are essential to appreciate this ideal family home.
Living Room 12' 8" x 12' 4" (3.87m x 3.76m )
UPVC Double glazed bay window to front elevation, Fire with featured surround, Central heating radiator. Coving to ceiling.
Dining Room 13' 6" x 10' 9" (4.1m x 3.27m )
UPVC Double glazed bay window to rear elevation, Fire with featured surround, Central heating radiator, Coving to ceiling.
UPVC Double glazed window to side elevation, Wall and base units with roll top work surfaces, UPVC door to side elevation, Stainless steel sink and drainer, Integrated oven and gas hob with pull out extractor over head, Part tiling to walls, Space for washing machine,
UPVC Double glazed frosted window to side elevation, Loft access with pull down ladder access, the loft is boarded for ample storage and lighting.
UPVC Double glazed frosted window to side elevation, Two piece white bathroom suite comprising: Pedestal wash hand basin, Paneled bath with shower over head, Part tiling to walls. Central heating radiator.
UPVC Double glazed frosted window to side elevation, low level w.c, Part tiling to walls,
Bedroom 12' 4" x 11' 4" (3.75m x 3.44m )
Bedroom 10' 8" x 11' 8" (3.24m x 3.54m )
Bedroom 8' 0" x 8' 0" (2.44m x 2.43m )
Driveway to front elevation with gated access and small garden area, Gated access to rear garden, Spacious garden to rear elevation with paved walk way.
201076237/2
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Sunraysia Rim 15 x 7 to suit Toyota Nissan six stud | eBay Please enable JavaScript Our new search experience requires JavaScript to be enabled. Please enable JavaScript on your browser, then try again.
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FOXBOROUGH, Mass. -- Friday marked the final day of media access leading into the AFC Championship Game, with head coach Bill Belichick and quarterback Tom Brady holding morning news conferences, followed by an open locker-room period.
Here were a few things that caught our attention.
1. Wilfork packed and ready to go: Defensive captain Vince Wilfork had his suitcase by his locker and was present in the time that reporters were in the locker room. Wilfork has essentially served as another coach for the team since landing on season-ending injured reserve in late September.
2. Belichick credits special-teams coaches: The Patriots ranked No. 1 in the annual special-teams rankings compiled by Rick Gosselin of the Dallas Morning News. It is clear that Belichick respects Gosselin’s work (“he does a great job of that”), and when asked to what he attributes the high ranking,�Belichick first credited special-teams coaches Scott O’Brien and Joe Judge, as well as special-teams captain Matthew Slater.
4. Locker-room scene: From the lighthearted department, rookie cornerback Logan Ryan was donning a red “Blount force trauma” T-shirt, created by running back LeGarrette Blount. ...�About six boxes of Kane’s donuts were spread on a table on one side of the locker room. ... center Ryan Wendell, defensive end Chandler Jones and receivers Julian Edelman and Danny Amendola were among those drawing larger crowds.

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Patent US7823033 - Data processing with configurable registers - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA data processing system includes functional circuitry which performs at least one data processing function, a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing...http://www.google.com/patents/US7823033?utm_source=gb-gplus-sharePatent US7823033 - Data processing with configurable registersAdvanced Patent SearchPublication numberUS7823033 B2Publication typeGrantApplication numberUS 11/460,090Publication dateOct 26, 2010Filing dateJul 26, 2006Priority dateJul 26, 2006Also published asUS20080126769Publication number11460090, 460090, US 7823033 B2, US 7823033B2, US-B2-7823033, US7823033 B2, US7823033B2InventorsWilliam C. Moyer, Jimmy GumuljaOriginal AssigneeFreescale Semiconductor, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (24), Non-Patent Citations (3), Referenced by (1), Classifications (15), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetData processing with configurable registersUS 7823033 B2Abstract A data processing system includes functional circuitry which performs at least one data processing function, a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, where a portion of the plurality of GPRs are reconfigurable as test registers during a test mode, and control circuitry which provides a test enable indicator to the register file. The portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from predetermined circuit nodes within the functional circuitry. In one aspect, the portion of the plurality of GPRs are reconfigured as multiple input shift registers (MISRs) during the test mode and generate signatures based on the test data.
providing a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system;
during the test mode, configuring a portion of the plurality of general purpose registers to operate as at least one multiple input shift register (MISR) wherein a portion of a register line is configured to operate in the test mode and a remaining portion of the register line is configured to remain in a normal mode of operation;
during the test mode, each register in the portion of the plurality of general purpose registers generating a signature;
exiting the test mode; and
after exiting the test mode, using the portion of the plurality of general purpose registers as general purpose registers for normal program execution.
2. The method of claim 1, wherein the configuring the portion of the plurality of general purpose registers to operate as at least one MISR comprises:
implementing one or more bit cells of each register in the portion of the plurality of general purpose registers with at least one logic gate wherein, during the test mode, the at least one logic gate receives a first input from another bit cell and the at least one logic gate provides an output to yet another bit cell; and
providing test data from test points located at predetermined circuit nodes within the data processing system to a second input of the at least one logic gate.
3. The method of claim 1, wherein the portion of the plurality of general purpose registers correspond to a selected subset of registers of the plurality of general purpose registers.
4. The method system of claim 3, wherein the selected subset of registers is selected based on a software Application Binary Interface (ABI).
5. The method of claim 1, wherein the portion of the plurality of general purpose registers corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of general purpose registers.
6. The method of claim 5, wherein remaining bit locations within each register of the selected subset of registers of the plurality of general purpose registers continue to operate as general purpose registers for normal program execution during the test mode.
7. The method of claim 5, wherein the subset of bit locations corresponds to higher order bit locations within the each register of the selected subset of registers of the plurality of general purpose registers.
during test mode, using at least one register in the portion of general purpose registers configured as the at least one MISR as a source register for a processor instruction executed by the data processing system.
9. The method of claim 8, wherein the processor instruction performs an operation selected from a group consisting of an arithmetic operation, a logic operation, or an effective address calculation.
functional circuitry which performs at least one data processing function;
a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, wherein a portion of the plurality of general purpose registers are reconfigurable as at least one test register during a test mode, a portion of a register line of the at least one test register is configured to operate in the test mode and a remaining portion of the register line is configured to remain in a normal mode of operation; and
control circuitry which provides a test enable indicator to the register file, wherein the portion of the plurality of general purpose registers, in response to the test enable indicator indicating the test mode is enabled, operate to accumulate test data from predetermined circuit nodes within the functional circuitry.
11. The data processing system of claim 10, wherein the portion of the plurality of general purpose registers, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from the predetermined circuit nodes within the functional circuitry and generate a signature used to test functionality of the functional circuitry.
12. The data processing system of claim 10, wherein the at least one test register comprises at least one multiple input shift register (MISR).
13. The data processing system of claim 10, wherein the register file further comprises:
selecting circuitry coupled to storage circuitry in each register of the portion of the plurality of GPRs, the selecting circuitry selecting between providing a normal write input to the storage circuitry and providing a test input based at least in part on the test enable indicator.
14. The data processing system of claim 13, wherein the selecting circuitry provides the normal write input when the test enable indicator indicates that test mode is not enabled and provides the test input when the test enable indicator indicates that test mode is enabled.
15. The data processing system of claim 10, wherein the portion of the plurality of general purpose registers corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of general purpose registers.
16. The data processing system of claim 15, wherein remaining bit locations within each register of the selected subset of registers of the plurality of general purpose registers continue to operate as general purpose registers for normal program execution during the test mode.
a register file having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, wherein a portion of the plurality of general purpose registers are reconfigurable as at least one multiple input shift register (MISR) during a test mode, a portion of a register line of the plurality of general purpose registers is configured to operate in the test mode and a remaining portion of the register line is configured to remain in a normal mode of operation; and
control circuitry which provides a test enable indicator to the register file, wherein each register in the portion of the plurality of general purpose registers, in response to the test enable indicator indicating the test mode is enabled, operates as at least a portion of a multiple input shift register (MISR) to generate a signature based on test data received from predetermined circuit nodes within the functional circuitry.
18. The data processing system of claim 17, wherein the register file comprises:
selecting circuitry for each bit cell in each register of the portion of the plurality of general purpose registers, the selecting circuitry selecting between providing a normal write input and providing a test input based at least in part on the test data received from the predetermined circuit nodes within the functional circuitry; and
a logic gate in each bit cell in each register of the portion of the plurality of general purpose registers, each logic gate coupled to receive at least a portion of the test data from the predetermined circuit nodes within the functional circuitry and coupled to provide the test input to the selecting circuitry.
19. The data processing system of claim 18, wherein the selecting circuitry provides the normal write input when the test enable indicator indicates that test mode is not enabled and provides the test input when the test enable indicator indicates that test mode is enabled.
20. The data processing system of claim 17, wherein the portion of the plurality of general purpose registers corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of general purpose registers. Description
RELATED APPLICATION The present invention is related to the applications entitled:
(1) �Method and Apparatus For Testing A Data Processing System� filed on Feb. 16, 2006 and having a U.S. Ser. No. of 11/355,681, now U.S. Pat. No. 7,444,568, and assigned to the same assignee as the present application; and (2) �Pipelined Processor With Deterministic Signature Generation� filed of even date herewith, U.S. Ser. No. 11/460,086, now U.S. Pat. No. 7,627,795, and assigned to the same assignee as the present application. FIELD OF THE INVENTION The present invention relates generally to data processors, and more particularly to testing a data processor.
Since the testing of the integrated circuit is performed on-line or while the integrated circuit is functioning in a real-world application, the circuitry for implementing the MISR and associated control must be implemented within the integrated circuit. Due to the size of a MISR and therefore expense, the number of MISRs and the implementation size of a MISR may be limited. As a result the ability to test the integrated circuit is severely limited.
FIG. 2 illustrates a block diagram of data storage circuitry that functions dually as a general purpose register (GPR) and as a MISR bit cell;
FIG. 3 illustrates a block diagram of a configurable MISR in accordance with one embodiment of the present invention;
FIG. 4 illustrates in table form an example of a register file configuration in accordance with one form of the present invention;
FIG. 5 illustrates in table form another example of a register file configuration in accordance with another form of the present invention; and
FIG. 6 illustrates in diagram form an exemplary command or instruction to be used by the global control circuitry of the data processing system of FIG. 1.
DETAILED DESCRIPTION FIG. 1 illustrates a data processing system 10 having register files that are configurable for normal operation and for test operation. Thus the registers of the register files are reconfigurable. A multiple-bit global bus 12 functions to communicate data within the data processing system 10. A bus interface unit (BIU) 14 has an input and an output connected to the global bus 12. The data processing system 10 also includes one or more execution units 16, an instruction decoder 18, an instruction fetch unit 20, register files 22, global control 24, exception logic 26, a load/store unit 28 and a cache 30. A first input/output of the bus interface unit 14 is connected to a first input/output of the instruction fetch unit 20. A second input/output of the bus interface unit 14 is connected to a first input/output of the global control 24. A third input/output of the bus interface unit 14 is connected to a first input/output of the load/store unit 28. A fourth input/output of the bus interface unit 14 is connected to an output of cache 30. A second input/output of the instruction fetch unit 20 is connected to a second input/output of the global control 24. A third input/output of the global control 24 is connected to a second input/output of the one or more execution units 16. A third input/output of execution units 16 is connected to a first input/output of register files 22. A fourth input/output of the global control 24 is connected to an input/output of the instruction decoder 18. A fifth input/output of the global control 24 is connected to an input/output of the exception logic 26. Exception logic 26 also has an input for receiving an Interrupt Request signal. A sixth input/output of the global control 24 is connected to a first input/output of the cache 30. A seventh input/output of the global control 24 is connected to a second input/output of the load/store unit 28. An eighth input/output of the global control 24 is connected to a second input/output of register files 22. An output of the global control 24 provides a MISR Enable signal to an input of the register files 22 and functions as a select signal to select between a MISR test mode and a normal operation mode. A second input/output of the load/store unit 28 is connected to a third input/output of the register files 22. A fourth input/output of the load/store unit 28 is connected to a second input/output of the cache 30. It should be understood that other forms of data processing system 10 may not utilize cache 30 but rather use memory that is located outside of the data processing system 10. It should also be understood that the location of control circuitry within the data processing system 10 is implementation specific. For example, various control circuits are located within each of the functional units of the instruction fetch unit 20, the instruction decoder 18, the execution units 16 and the register files 22 for more limited control than the global control 24.
In operation, data processing system 10 is implemented as a pipelined data processing system. That means that the execution of data processing instructions functions in discrete time intervals in which a particular function in the execution occurs during each time interval. In one form, instruction execution advances in a pipeline in response to a system clock, wherein each cycle of the system clock advances the execution by one stage. In a first operation, an instruction is fetched in a first pipeline stage from the bus interface unit 14 by the instruction fetch unit 20. In a second pipeline stage, the fetched instruction is coupled to the instruction decoder 18 from the instruction fetch unit 20 and decoded. The resulting decoded instruction is then coupled to execution units 16 and instruction execution begins in a third pipeline stage. In some forms, the instruction execution occurs during two cycles of the system clock. In one form, the execution stage of the pipeline has two phases of instruction execution. Depending upon the functionality of the executed instruction, the result of the pipelined operation may be fed back to the input of the pipeline and used as a subsequent input. In a final stage of the pipeline a write back to memory, such as the cache 30, is performed. The various pipeline stages which are described herein are defined herein as �staging�. In other words, staging is the operation of data processing system in specific stages each having a predetermined function or functions. Staging is also the association of specific hardware circuitry with the functions of each stage in the ordered sequence which forms the data processing pipeline.
Registers files 22 are shared between the load/store unit 28 and the execution units 16. The load/store unit 28 operates in response to the global control 24 and provides data to and receives data from the bus interface unit 14. The load/store unit 28 also provides data to and receives data from the general purpose registers within the register files 22. Exception logic 26 functions to generate any of various types of data processing exceptions. An interrupt request may be generated and provided to the exception logic 26 in response to various events either within the illustrated data processing system 10 or from sources external to the data processing system 10. For example, instruction execution latency resulting from the generation of wait states may cause the generation of an exception as well as the occurrence of faults resulting from instruction execution errors. Various types of real-time interrupt requests may also be received by exception logic 26 via one or more interrupt request inputs.
The discussion of the operation of data processing system 10 to this point is conventional. Additionally, data processing system 10 has a real-time test capability that permits testing of various test points located at predetermined circuit nodes within the functional circuitry of data processing system. For example, the various test points may be located within any or all of the functional blocks illustrated in FIG. 1. The real-time testing of data processing system 10 is accomplished with one or more MISR circuits. However, the implementation of shift registers dedicated for the sole purpose of test would represent a significant amount of the area of the data processing system. To avoid the penalty of dedicating a large amount of area for the purpose of test, data processing system 10 uses register files 22 that are configurable to function as both general purpose registers and as registers for a test function such as a MISR.
A MISR functions to receive test data from various test locations within the system as the system is exercised. The MISR compresses the multiple test values by performing a plurality of predetermined logic operations that are determined by which test polynomial is selected. The compressed MISR result is typically referred to as a MISR signature. The value of the MISR signature and the structure of the MISR itself are polynomial specific and test point specific, and will vary from implementation to implementation. After exercising the system for a predetermined interval, the MISR result is compared with an expected MISR value for the implemented polynomial and a determination is made whether the data processing system is working correctly based on the comparison. Multiple MISR registers may be implemented to allow for a larger number of test points to be captured for signature generation. The advantage in increasing the number of MISRs is to allow for broader test coverage but comes at the penalty of additional size and cost of the system. Further explanation below is required to appreciate how the configurable registers within register files 22 provide the ability to dually use storage devices in data processing system 10 for normal operation and for test without negatively impacting the size of the system.
Illustrated in FIG. 2 is a block diagram of an exemplary storage device of a bit cell which functions as a general purpose register (GPR) bit and as a MISR bit. As a general purpose register, the register is included as part of a user's programming model for the data processing system. The general purpose registers are utilized for storing data values used as source values and result values during the execution of processor instructions, and constitute a portion of the programming model available to a user of the data processing system. Typical data processors implement a plurality of GPRs for use as source and destination values. Typical processing systems may implement sixteen, thirty-two or sixty-four GPRs. General purpose registers are well known.
Referring to FIG. 2, GPR MISR bit cell 50 has an exclusive OR gate 52 having a first input for receiving an Input value, a second input for receiving Test Data and a third input for receiving a signal labeled �MISR Feedback�. Alternatively the third input may be connected to a logic zero value and thus not influence the value of an output of exclusive OR gate 52. The output of exclusive OR gate 52 is connected to a first input of a multiplexor (Mux) 54. A second input of multiplexor 54 is connected to a Normal Write Input signal for receiving a digital value in the normal mode of operation to be written to or stored by the GPR MISR bit cell 50, such as the result of executing a processor instruction which designates the GPR as a destination register. A control input of multiplexor 54 receives the MISR Enable signal from global control 24. The MISR Enable signal selects the output of exclusive OR gate 52 when asserted. An output of multiplexor 54 is connected to a data (D) input of a flip-flop 56. A data (Q) output of flip-flop 56 provides an Output signal. Flip-flop 56 is clocked by clock signal (not shown) provided by global control 24 which controls the timing of when a value that is output by multiplexor 54 is stored. Thus it should be apparent that the GPR MISR bit cell 50 is configurable by the MISR Enable signal to function as either a MISR bit cell or as a general purpose register bit cell to capture and store data in a normal mode of operation. As a result a dual function is provided by the GPR MISR bit cell 50.
Illustrated in FIG. 3 is a block diagram implementation of a MISR 58. The MISR 58 is implemented with a plurality of serially connected bit cells 60-64, each of which is analogous to GPR MISR bit cell 50. A predetermined number of bit cells is used to implement a MISR wherein the predetermined number is typically a multiple of two. Each of bit cells 60-64 has an input, a Test Data input, a Normal Write input and a MISR Enable signal input. Bit cell 60 receives as feedback at its input the output of bit cell 64. The output of bit cell 64 is also connected to the third input of the exclusive OR gate analogous to exclusive OR gate 52 of predetermined bit cells 61, 63 and 64. Which bit cell or cells receives the MISR feedback is polynomial specific. It should be apparent that each of bit cells 60-64 receives test data from differing predetermined test points within the data processing system 10. The received test data is selected and provided to the exclusive OR gate, such as exclusive OR gate 52, of the bit cell, with the result stored in each respective bit cell in response to the MISR Enable signal. Additionally, each of bit cells 60-64 alternatively stores normal instruction execution result information which is written into storage when the MISR Enable signal in inactive and indicates a normal mode (i.e. non-test mode) of operation. Therefore, MISR capability is provided in a subset of the GPRs of the data processing system 10. The MISR function is controllable by software to switch between a test mode and a normal mode. When operating in the MISR mode of operation, the subset of GPRs which are implemented with GPR MISR bit cells as the storage elements act normally as source operands and are updated at selected points in time as MISRs to collect and accumulate information about various signal points in the data processing system 10. Therefore MISR signature generation may occur during a sequence of tests that utilize normal instruction execution to stimulate the data processing system. During execution of the test sequence of normal processor instructions, test values from the various test data points connected to the test data inputs of the GPR MISR bit cells are accumulated in the corresponding MISR. At the end of the test sequence, the GPR values are read out by normal data processing instruction execution as MISR signature values, and are compared to expected results to determine whether a failure has occurred during execution of the test sequence of instructions. Differing MISR modes can be implemented in which the GPRs can also capture merged destination data. In alternate embodiments, data merging of the normal write data into the exclusive OR gates may be implemented by providing a fourth input (not shown) to the exclusive OR gate 52 of some or all of the GPR MISR bit cells. This allows for further testing of the data processing system 10 to occur without additional test sequences, since the normal results of instruction execution can be compressed into the MISR signature in parallel with compression of the test data.
During execution of testing code when data processing system 10 is in the test mode, the subset of GPRs that is dedicated for MISR functionality is typically unavailable for use as general purpose registers. Therefore, the selection of which general purpose registers to implement the enhanced MISR functionality is made to ensure that no essential processor capability is lost. Therefore proper selection of a subset of general purpose registers will be discussed.
Illustrated in FIG. 4 is an exemplary register mapping of a portion of the register files 22 of FIG. 1. As an example, thirty-two contiguous registers labeled R0 through R31 are illustrated wherein each register is sixty-four bits wide. In the example, a portion 70 of registers R16-R31 is selected as the registers that will be configurable as MISRs. It is of course relevant that these registers continue to function normally as source operands to instructions that are executed. In one form, a portion 72 of registers R16 through R31 is provided which are not configurable between normal and test modes of operation. This provides the possibility that a portion of one register line may be configured to operate in the test mode of operation and a remaining portion of that register line is configured to always remain in a normal mode of operation. In one embodiment the selection of what subset of GPRs is made configurable is based on a software Application Binary Interface (ABI) which describes the low-level interface between an application program and the operating system, between an application and its libraries, or between component parts of the application. In many applications, the use of all the registers in the GPR registry is not required for instruction execution and a determination of any GPR capacity that is not essential to the software results in good candidates for becoming configurable registers. In the embodiment shown in FIG. 4, many processing instructions do not require a full sixty-four bits of information to be used during instruction processing. Thus, the upper thirty-two bits of the general purpose registers are not utilized and are available for configuration as MISRs. To ensure that those processing instructions which do require sixty-four bit operands are still available for use, only a portion of a subset of the GPRs are configurable, namely registers R16 through R31. General purpose registers R0 through R15 are not configurable, and function normally in the test mode of operation. Thus registers R0 through R15 are available for use by instructions requiring sixty-four bit general purpose values.
It should be noted also that the registers which are selected as being configurable may still be used in the test mode of operation as general purpose source registers. In other words, these registers may function normally as source operands to instructions. The values that are in the flip-flops of the bit cells 60-64 of the registers configured as MISRs during test mode provide a useful source of pseudo-random source values or test vectors for exercising logic within the data processing system. Since the MISRs are accumulating as execution proceeds, pseudo-random values are continuously generated. Therefore, during the test mode at least one register in the portion of the GPRs that are configured as one or more MISRs is used as a source register for a processor instruction that is executed by data processing system 10. In one form, that processor instruction performs an operation such as an arithmetic operation, a logic operation or an effective address calculation.
Illustrated in FIG. 5 is another example of a register mapping of the register files 22 of FIG. 1. In this example thirty-two registers, R0 through R31 are illustrated. A portion 74 or subset of the registers are designated by cross-hatching to be configurable to operate as both general purpose registers and as MISR registers. In the illustrated form portion 74 includes registers R8 through R23. In this form each register is thirty-two bits wide and all of the register width is made configurable. In one form, the selection of what subset of GPRs is made configurable is based on a software Application Binary Interface (ABI) which describes the low-level interface between an application program and the operating system, between an application and its libraries, or between component parts of the application. In many applications, the use of all the registers in the GPR registry is not required for instruction execution, and a determination of any GPR capacity that is not essential to the software results in good candidates for becoming configurable registers. In the embodiment shown in FIG. 5, the selection of registers to operate as MISR registers in the test mode of operations has been made based upon a convention for register usage by an ABI. In this convention, registers r8-r23 are not absolutely essential for proper operation of the data processor, provided that some limitations are placed on the ABI regarding register usage. It is desired to minimize the impact on the ABI in all cases, and the selected registers result in a minimized impact. In one embodiment, by ABI convention, general purpose registers R0 and R3-R7 are used as temporary or �volatile� registers. Register R1 is used as a stack pointer, register R2 is used as a pointer to a small data area, and registers R24-R31 are used as non-volatile registers to hold non-volatile data. In one form, registers R3-R7 are used by convention as argument passing registers to pass arguments and return results between software functions in compliance with an ABI function calling convention.
Such register usage conventions are well known and serve to promote interoperability of different compiled software functions. Proper selection of the GPRs to be used as MISR registers during the test mode is thus critical to minimize the impact on the calling convention and interoperability. It should be noted that the test mode relies on execution of normal software functions to provide the stimulus to the data processing system, and that the test data values which are accumulated into one or more MISR signature values are generated as a result of normal execution of normal, not special, processor instructions using the instructions available to the user outside of the test mode of operation, and for the most part using the same ABI conventions on general purpose register usage.
Illustrated in FIG. 6 is a command 80 having two fields which respectively function to select test points in data processing system 10 and to enable the test mode. The command 80 has a first field labeled �select� which controls which test points are coupled as the test data to the respective test data inputs of bit cells 60-64. The select information of command 80 is used by circuitry (not shown) such as a multiplexor that determines a specific predetermined test point within data processing system 10 for each test data input. Thus the determination of what points within the data processing system 10 to test is user programmable in real-time fashion. The second field of command 80 is labeled �MISR enable� and is the signal that the global control 24 provides to each GPR MISR bit cell to enable and disable the test mode of operation. Therefore the collection of test information at predetermined points in the data processing system 10 is within user control and is programmable.
By now it should be appreciated that there has been provided a method of operation and a data processing system that has configurable MISR capability for a portion of a general purpose register file. It should be understood that the portion may vary from a small subset of the general purpose register files to a substantial portion of the general purpose register files. The readily configurable MISR registers discussed herein satisfy a customer requirement that a data processing system be available for processing to meet system needs in safety applications and to ensure that critical applications are not interrupted. The configurable test capability disclosed herein provides a low cost and flexible method of adding signature test logic to a data processing system. Size is minimized by the time multiplexed use of a portion of the general purpose registers for this function.
In one form there is herein provided a method of providing a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for a data processing system. A test mode is entered. During the test mode, a portion of the plurality of GPRs is configured to operate as at least one multiple input shift register (MISR). During the test mode, each register in the portion of the plurality of GPRs generates a signature. The test mode is exited. After exiting the test mode, the portion of the plurality of GPRs is used as general purpose registers for normal program execution. In one form the portion of the plurality of GPRs is configured to operate as at least one MISR by implementing one or more bit cells of each register in the portion of the plurality of general purpose registers with at least one logic gate. During the test mode, the at least one logic gate receives a first input from another bit cell and the at least one logic gate provides an output to yet another bit cell. Test data is provided from test points located at predetermined circuit nodes within the data processing system to a second input of the at least one logic gate. In one form the portion of the plurality of GPRs corresponds to a selected subset of registers of the plurality of GPRs. In another form the selected subset of registers is selected based on a software Application Binary Interface (ABI). In yet another form the portion of the plurality of GPRs corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of GPRs. In another form remaining bit locations within each register of the selected subset of registers of the plurality of GPRs continue to operate as general purpose registers for normal program execution during the test mode. In yet another form the subset of bit locations corresponds to higher order bit locations within the each register of the selected subset of registers of the plurality of GPRs. In another form during test mode, at least one register in the portion of GPRs configured as the at least one MISR is used as a source register for a processor instruction executed by the data processing system. In another form the processor instruction performs an operation selected from a group consisting of an arithmetic operation, a logic operation, or an effective address calculation.
In another form there is provided a data processing system having functional circuitry which performs at least one data processing function. A register file is coupled to the functional circuitry and has a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system. A portion of the plurality of GPRs is reconfigurable as at least one test register during a test mode. Control circuitry provides a test enable indicator to the register file, wherein the portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from predetermined circuit nodes within the functional circuitry. In another form the portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from the predetermined circuit nodes within the functional circuitry and generates a signature used to test functionality of the functional circuitry. In another form the at least one test register is at least one multiple input shift register (MISR). In another form the register file further includes selecting circuitry coupled to each bit cell in each register of the portion of the plurality of GPRs. The selecting circuitry selects between providing a normal write input and providing a test input. In another form the selecting circuitry provides the normal write input when the test enable indicator indicates that test mode is not enabled and provides the test input when the test enable indicator indicates that test mode is enabled. In yet another form the portion of the plurality of GPRs corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of GPRs. In another form remaining bit locations within each register of the selected subset of registers of the plurality of GPRs continue to operate as general purpose registers for normal program execution during the test mode.
Also there is provided a data processing system having functional circuitry which performs at least one data processing function. A register file has a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system. A portion of the plurality of GPRs are reconfigurable as at least one multiple input shift register (MISR) during a test mode. Control circuitry provides a test enable indicator to the register file, wherein each register in the portion of the plurality of GPRs, in response to the test enable indicator indicating that the test mode is enabled, operates as a multiple input shift register (MISR) to generate a signature based on test data received from predetermined circuit nodes within the functional circuitry. In another form the register file has selecting circuitry for each bit cell in each register of the portion of the plurality of general purpose registers. The selecting circuitry selects between providing a normal write input and providing a test input based at least in part on the test data received from the predetermined circuit nodes within the functional circuitry. A logic gate is in each bit cell in each register of the portion of the plurality of general purpose registers. Each logic gate is coupled to receive at least a portion of the test data from the predetermined circuit nodes within the functional circuitry and coupled to provide the test input to the selecting circuitry. In another form the selecting circuitry provides the normal write input when the test enable indicator indicates that test mode is not enabled and provides the test input when the test enable indicator indicates that test mode is enabled. In another form the portion of the plurality of GPRs corresponds to a subset of bit locations within each register of a selected subset of registers of the plurality of GPRs.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. It should be understood that all circuitry described herein may be implemented either in silicon or another semiconductor material or alternatively by software code representation of silicon or another semiconductor material. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
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No. 11/355,681, filed Feb. 16, 2006.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS20090307770 *Aug 17, 2006Dec 10, 2009Peter William HarrisApparatus and method for performing integrity checks on sofware* Cited by examinerClassifications U.S. Classification714/724, 365/201, 714/732, 324/762.01International ClassificationG11C29/00, G01R31/28, G01R31/26Cooperative ClassificationG06F9/30141, G06F9/30189, G06F9/30112, G06F9/30134European ClassificationG06F9/30R6, G06F9/30X4, G06F9/30R4C, G06F9/30R5SLegal EventsDateCodeEventDescriptionNov 6, 2013ASAssignmentFree format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031591/0266Effective date: 20131101Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YORAug 20, 2013CCCertificate of correctionJun 18, 2013ASAssignmentFree format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030633/0424Effective date: 20130521Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YORMay 13, 2010ASAssignmentOwner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORKFree format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100518;REEL/FRAME:24397/1Effective date: 20100413Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100521;REEL/FRAME:24397/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:24397/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:24397/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORKMar 15, 2010ASAssignmentOwner name: CITIBANK, N.A.,NEW YORKFree format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100325;REEL/FRAME:24085/1Effective date: 20100219Owner name: CITIBANK, N.A.,NEW YORKFree format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100318;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100317;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100323;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100329;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100330;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100401;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100406;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100408;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100413;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100415;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100420;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100422;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100429;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100504;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100511;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100513;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100518;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:24085/1Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024085/0001Owner name: CITIBANK, N.A., NEW YORKFeb 2, 2007ASAssignmentOwner name: CITIBANK, N.A. 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MONTEREY OPEN TO VILLA FORCE; Consul Does Not Expect Any Opposition -- Garrison Leaves for the Border. CARRANZA CLAIMS VICTORIA And Denies Defeat at Saltillo -- Villa at Aquascalientes for Conference with Chiefs. - The New York Times
Archives|MONTEREY OPEN TO VILLA FORCE; Consul Does Not Expect Any Opposition -- Garrison Leaves for the Border. CARRANZA CLAIMS VICTORIA And Denies Defeat at Saltillo -- Villa at Aquascalientes for Conference with Chiefs.
https://nyti.ms/1QQWS2l
MONTEREY OPEN TO VILLA FORCE; Consul Does Not Expect Any Opposition -- Garrison Leaves for the Border. CARRANZA CLAIMS VICTORIA And Denies Defeat at Saltillo -- Villa at Aquascalientes for Conference with Chiefs.
JAN. 13, 1915
January 13, 1915, Page 4 The New York Times Archives
WASHINGTON, Jan. 12. -- Monterey has been evacuated by practically all of the Carranza troops, who have gone to Matamoras, on the border opposite Brownsville, according to Consular dispatches received today by the State Department. View Full Article in Timesmachine »
A version of this archives appears in print on January 13, 1915, on Page 4 of the New York edition with the headline: MONTEREY OPEN TO VILLA FORCE; Consul Does Not Expect Any Opposition -- Garrison Leaves for the Border. CARRANZA CLAIMS VICTORIA And Denies Defeat at Saltillo -- Villa at Aquascalientes for Conference with Chiefs. . Order Reprints| Today's Paper|Subscribe

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The real estate services company Cushman & Wakefield said in its first-quarter report on the statewide market that despite a general dearth of leasing activity, Newark -- along with the Hudson River waterfront and Princeton -- remains a ''pocket of reasonable strength.'' The overall vacancy rate rose slightly in the first quarter to 19.3 percent, Cushman reported. But in Newark, the rate was only 14.4, just above the 13.6 percent rate in Princeton and 12.9 percent on New Jersey's Gold Coast.''I tell you,'' said Steven M. Greenberg, president of the Heritage Management Company, which presided over the turnaround of a half-empty office tower at 550 Broad Street, now 90 percent leased, ''Newark is rising.''Edwin H. Cohen and David N. Stifelman, the Cushman & Wakefield brokers who represented Affiliated Computer Services in its quest to consolidate operations after years spent by E-ZPass in two cramped offices in Secaucus, said they looked at properties all around New Jersey, from Bergen County south to Trenton. One of Newark's unusual strengths came into play with the former Krementz jewelry plant, they noted: wiring.''A.C.S. is running the 24-hour call center for E-ZPass, in addition to its consumer office, for walk-ins,'' Mr. Stifelman said. ''They needed a tremendous amount of bandwidth, and a lot of power -- reliable power'' for their computer systems.THE McCarter Highway building, owned by the JEMB Realty Corporation of Manhattan, is a ''mission critical'' facility, said Christian Benedetto, a broker who is marketing third-floor space above the E-ZPass offices, which take up two floors. Mr. Benedetto, director of real estate services for National Redevelopment, is also a co-founder of the Newark Technology Group, set up three years ago to promote the city's technological capacities.''During the last power outage in Newark, when a power line was cut downtown as they were doing some construction, and the power was out for three hours, this building did not lose power,'' he said. ''There are 40,000 amps going into it -- 110 watts per square foot, whereas a standard office building has 6.5 watts per square foot. It has its own substation, with dual feeds -- one from Broad Street and one from McCarter Highway.''There is also a sort of a telecom highway of fiber-optic cable running underneath Broad Street, Mr. Stifelman said. ''If you take off the cover of a manhole, it's filled with fiber,'' he said. ''That's because Verizon has its main office in downtown Newark, covering a good portion of northern Jersey -- one of the most densely populated areas in the country.''
Mr. Benedetto noted that fiber-optic cables are buried along rail lines in Newark, as is usually the case. The E-ZPass building is situated just south of Lincoln Park in Newark, very near where the Amtrak and New Jersey Transit rail lines intersect, with the fiber lines running along its east side.Michael Huerta, a managing director of Affiliated Computer Services, said: ''I loved the building, and the site, as soon as we were made aware of it. It provides us with excellent access to some pretty sophisticated communications technology, and the infrastructure was already in place to enable us to connect with our main data center in Tarrytown, N.Y.
''We needed 12 T-1 lines for our use, an administrative phone system and support for our data backbone computer systems,all of which connect to toll plazas on three roadways -- the New Jersey Turnpike, the Garden State Parkway and the Atlantic City Highway.''JEMB Realty spent more than $3 million three years ago to put in the power substation, with plans of turning the building into a ''telecom hotel,'' or back-office computer center. But then the telecommunications market began to experience its own kind of outages -- mass layoffs, company closings -- ''and we changed direction,'' said a JEMB principal, Raymond Chalmé.''The great thing is we found a different kind of tenant, but one with the same needs,'' he said. ''The challenging thing was that A.C.S. had signed a contract with the state that set a very tight schedule for getting the new E-ZPass office up and running, something short of 60 days.''Mr. Chalmé's partner, Dan Blanco, said that he had arranged to have contractors ''ready to jump out of their chairs'' the moment the state approved final aspects of the plans -- and that they agreed to work through the Thanksgiving, Christmas and New Year's holidays. The E-ZPass center opened to the public on March 17.''One of the biggest selling points of this property was the available parking,'' Mr. Cohen said. The building has its own adjacent lot -- unusual for downtown Newark -- and leased rights to a number of other nearby lots.The main lot and building are encircled by barbed-wire fence, which representatives of some rival properties observed might send a negative signal about the safety of the neighborhood. But the owners said the barbed wire was there only because Krementz -- which now has only a small third-floor office -- had once required a high degree of security for the gems and precious metals it used to make jewelry. The owners noted that the building also has a huge vault at its core, which is now used by Affiliated as storage space.A Department of Transportation study of walk-in traffic at E-ZPass from Tuesday to Friday of the opening week showed 1,102 customers found their way through the doors. On Saturday, when the center is open 8 a.m. to 2 p.m. for those wanting to pay bills, purchase E-ZPass tags or exchange faulty transponders -- the windshield device that permits drivers to pass through toll booths -- 137 people showed up.''I think it's clear people are not afraid to visit Newark,'' said the commissioner, Mr. Lettiere. ''This is a perfect location for E-ZPass.'' Continue reading the main story