hwt/simulator/vcdHdlSimConfig.py
def vcdRegisterInterfaces(self, obj: Union[Interface, Unit],
                              parent: Optional[VcdVarWritingScope]):
        """
        Register signals from interfaces for Interface or Unit instances
        """
        if hasattr(obj, "_interfaces") and obj._interfaces:
            name = obj._name
            parent_ = self.vcdWriter if parent is None else parent

            subScope = parent_.varScope(name)
            self._obj2scope[obj] = subScope

            with subScope:
                # register all subinterfaces
                for chIntf in obj._interfaces:
                    self.vcdRegisterInterfaces(chIntf, subScope)

                if isinstance(obj, (Unit, SimModel)):
                    # register interfaces from all subunits
                    for u in obj._units:
                        self.vcdRegisterInterfaces(u, subScope)

            return subScope
        else:
            t = obj._dtype
            if isinstance(t, self.supported_type_classes):
                tName, width, formatter = vcdTypeInfoForHType(t)
                try:
                    parent.addVar(obj, getSignalName(obj),
                                  tName, width, formatter)
                except VarAlreadyRegistered:
                    pass
def vcdRegisterInterfaces(self, obj: Union[Interface, Unit],
                              parent: Optional[VcdVarWritingScope]):
        """
        Register signals from interfaces for Interface or Unit instances
        """
        if hasattr(obj, "_interfaces") and obj._interfaces:
            name = obj._name
            parent_ = self.vcdWriter if parent is None else parent

            subScope = parent_.varScope(name)
            self._obj2scope[obj] = subScope

            with subScope:
                # register all subinterfaces
                for chIntf in obj._interfaces:
                    self.vcdRegisterInterfaces(chIntf, subScope)

                if isinstance(obj, (Unit, SimModel)):
                    # register interfaces from all subunits
                    for u in obj._units:
                        self.vcdRegisterInterfaces(u, subScope)

            return subScope
        else:
            t = obj._dtype
            if isinstance(t, self.supported_type_classes):
                tName, width, formatter = vcdTypeInfoForHType(t)
                try:
                    parent.addVar(obj, getSignalName(obj),
                                  tName, width, formatter)
                except VarAlreadyRegistered:
                    pass
def vcdRegisterInterfaces ( self , obj : Union [ Interface , Unit ] , parent : Optional [ VcdVarWritingScope ] ) : if hasattr ( obj , "_interfaces" ) and obj . _interfaces : name = obj . _name parent_ = self . vcdWriter if parent is None else parent subScope = parent_ . varScope ( name ) self . _obj2scope [ obj ] = subScope with subScope : # register all subinterfaces for chIntf in obj . _interfaces : self . vcdRegisterInterfaces ( chIntf , subScope ) if isinstance ( obj , ( Unit , SimModel ) ) : # register interfaces from all subunits for u in obj . _units : self . vcdRegisterInterfaces ( u , subScope ) return subScope else : t = obj . _dtype if isinstance ( t , self . supported_type_classes ) : tName , width , formatter = vcdTypeInfoForHType ( t ) try : parent . addVar ( obj , getSignalName ( obj ) , tName , width , formatter ) except VarAlreadyRegistered : pass
Register signals from interfaces for Interface or Unit instances
Register signals from interfaces for Interface or Unit instances