hwt/serializer/verilog/serializer.py
def hardcodeRomIntoProcess(cls, rom):
        """
        Due to verilog restrictions it is not posible to use array constants
        and rom memories has to be hardcoded as process
        """
        processes = []
        signals = []
        for e in rom.endpoints:
            assert isinstance(e, Operator) and e.operator == AllOps.INDEX, e
            me, index = e.operands
            assert me is rom

            # construct output of the rom
            romValSig = rom.ctx.sig(rom.name, dtype=e.result._dtype)
            signals.append(romValSig)
            romValSig.hidden = False

            # construct process which will represent content of the rom
            cases = [(toHVal(i), [romValSig(v), ])
                     for i, v in enumerate(rom.defVal.val)]
            statements = [SwitchContainer(index, cases), ]

            for (_, (stm, )) in cases:
                stm.parentStm = statements[0] 

            p = HWProcess(rom.name, statements, {index, },
                          {index, }, {romValSig, })
            processes.append(p)

            # override usage of original index operator on rom
            # to use signal generated from this process
            def replaceOrigRomIndexExpr(x):
                if x is e.result:
                    return romValSig
                else:
                    return x
            for _e in e.result.endpoints:
                _e.operands = tuple(map(replaceOrigRomIndexExpr, _e.operands))
                e.result = romValSig

        return processes, signals
def hardcodeRomIntoProcess(cls, rom):
        """
        Due to verilog restrictions it is not posible to use array constants
        and rom memories has to be hardcoded as process
        """
        processes = []
        signals = []
        for e in rom.endpoints:
            assert isinstance(e, Operator) and e.operator == AllOps.INDEX, e
            me, index = e.operands
            assert me is rom

            # construct output of the rom
            romValSig = rom.ctx.sig(rom.name, dtype=e.result._dtype)
            signals.append(romValSig)
            romValSig.hidden = False

            # construct process which will represent content of the rom
            cases = [(toHVal(i), [romValSig(v), ])
                     for i, v in enumerate(rom.defVal.val)]
            statements = [SwitchContainer(index, cases), ]

            for (_, (stm, )) in cases:
                stm.parentStm = statements[0] 

            p = HWProcess(rom.name, statements, {index, },
                          {index, }, {romValSig, })
            processes.append(p)

            # override usage of original index operator on rom
            # to use signal generated from this process
            def replaceOrigRomIndexExpr(x):
                if x is e.result:
                    return romValSig
                else:
                    return x
            for _e in e.result.endpoints:
                _e.operands = tuple(map(replaceOrigRomIndexExpr, _e.operands))
                e.result = romValSig

        return processes, signals
def hardcodeRomIntoProcess ( cls , rom ) : processes = [ ] signals = [ ] for e in rom . endpoints : assert isinstance ( e , Operator ) and e . operator == AllOps . INDEX , e me , index = e . operands assert me is rom # construct output of the rom romValSig = rom . ctx . sig ( rom . name , dtype = e . result . _dtype ) signals . append ( romValSig ) romValSig . hidden = False # construct process which will represent content of the rom cases = [ ( toHVal ( i ) , [ romValSig ( v ) , ] ) for i , v in enumerate ( rom . defVal . val ) ] statements = [ SwitchContainer ( index , cases ) , ] for ( _ , ( stm , ) ) in cases : stm . parentStm = statements [ 0 ] p = HWProcess ( rom . name , statements , { index , } , { index , } , { romValSig , } ) processes . append ( p ) # override usage of original index operator on rom # to use signal generated from this process def replaceOrigRomIndexExpr ( x ) : if x is e . result : return romValSig else : return x for _e in e . result . endpoints : _e . operands = tuple ( map ( replaceOrigRomIndexExpr , _e . operands ) ) e . result = romValSig return processes , signals
Due to verilog restrictions it is not posible to use array constants
        and rom memories has to be hardcoded as process
Due to verilog restrictions it is not posible to use array constants and rom memories has to be hardcoded as process