texts: Can I use a dual high-side low-side gate driver as a dual low-side driver?

texts:
Some background: I am building a 350 VA DC to AC inverter, partly for my own curiosity, but mostly for a senior design project for my bachelor's.

What I have with me is monolithic dual high-and-low drivers with a 4A peak current driver, shown here. My planned first stage is going to be a push-pull type half bridge through the center tap of a transformer I hijacked out of an off-the shelf-UPS. I'll be doing this as mod-square wave, because the transformer is mains frequency rated, and I don't have time to get anything different. That output will then get rectified, stored, and h-bridged with my real experiment, which should be a low distortion sine wave output.

The push-pull mod-square arrangement doesn't need a high side driver, on account of not having one to speak of.

So, my question:

Given what I have available, can I use the high side output of the gate driver as a low-side output? I look at it, and it seems I would just have to omit the bootstrap capacitor and diode, connect Vb to Vcc, and connect Vs to GND, and then (I believe) it should work.

I have some time, but I have limited resources and I really just wanted to know before I go and etch a board. I also don't have a bunch of MOSFETs lying around to blow up while I learn. Also, using a single IC would save me some board space, and the chips have internally matched propagation delays.

I would appreciate any feedback on this application, or anything else the community would like to share.


texts: Behaviour of a capacitor+resistor (frequency domain)

texts:
why a capacitor behaves as an open circuit when \$\omega<\omega_p\$ and as a short circuit when \$\omega>\omega_p\$ (where \$\omega_p=1/RC\$ is a pole)? My question is generic.

Thank you for your time.


texts:
I'm trying to identify an IC named T072. It's used in several places inside a Rega Brio-R audio amplifier and it seems to be in the audio path. I can see it in the audio input paths but also int the record output audio path. It may be Texas Instruments based on that I see a logo that resembles the TI logo. Am I perhaps looking at a version of the TL072 OP from TI?

Unfortunately I don't have a picture of the circuit right now but I will try to  fix one.


texts:
How does a tank circuit work with a dc power supply? I understand that if you charge a capacitor that's in parallel with an inductor and then remove the power supply then the capacitor and inductor will exchange energy back and fourth and then slowly die out. But how does the oscillation begin with a constant DC power supply?

Can someone please examine to me how exactly this circuit works? Example, I think what's happening here is, the top plate of the capacitor has a positive charge and bottom negative, and when fully charged no current flows on the capacitor branch; with current flowing through the inductor L a electromagnetic field is building up, now with a field building up it would induce a current in L2 effectively turning on the transistor allowing the current from the inductor branch to flow through the transistor via collector-emmiter. Now with L fully charged the field is no longer changing and No current is induced in L2 so the transistor turns off. NOW, with the transistor off the current can still flow through L to the output line with the sine wave so L's field never changes and the capacitor never discharges because of the constant DC, now the only way I see it is to add a capacitor on the output line with the sine wave to block the DC and allowing the oscillations to occur. But in the diagram no capacitor has been added, so can someone explain if my explanation is right and Im missing something or give a thorough explanation like mine, of what's going on here.


texts:
I don't understand why the CAS latency of modern DDR4 memory is so high. I have no trouble understanding why the RAS latency is as high as it is -- given the small amount of charge stored in each bitcell, it is not hard to imagine that it takes a while for the signals to stabilize enough for the sense amplifiers to get a reliable reading when opening a row in a DRAM bank, and also that this is a rather analog process that isn't directly comparable to other memory technologies.
However, the way I understand the architecture of DRAM, once a row has been opened, the output from the sense amplifiers has effectively been latched into some sort of buffer made in ordinary CMOS logic, so in other words some kind of SRAM bank, the size of which is the size of the row, so some 2-8 kB in modern memories. I can think of no other example of an 8 kB SRAM memory (at least among ones made on similarly high-end process nodes) that takes so long to access.
For example, a common CAS latency value of DDR4 memory is 18 cycles, which at a rough 1.5 GHz memory clock rate (at DDR4 3000), means a real time value of about 12 ns. Compare that to, for instance, the L1 cache of a modern, fast CPU, which despite being significantly larger (often at 32 kB), being a CAM (which I'd assume is more complex to read out than a directly addressed memory), and even having multiple read and write ports, yet requires much less time to fetch a value, often at or even below 1 ns (and that time even includes such processes as virtual-to-physical address translation). I understand, of course, that the DDR4 memory is communicating over a bus that is significantly more cumbersome to drive than the internal data lines on a chip, but that doesn't seem to be relevant here, seeing as how the cycles of the CAS latency are being consumed inside of the memory chips themselves.
I certainly have zero experience designing high-speed ICs, so I'm sure there's much I could be missing or misunderstanding, but I just cannot think of any mechanism by which it would take so long to read and write to the open row buffer. It would be very satisfying if someone could explain why this is.
Why the is the CAS latency of modern DDR4 memory so high?


texts:
I am looking for a formula for R-2R current mode and voltage mode
is there some source where there is general formulas for these two?
Thanks.


texts: Different voltage rails output filter does share same core

texts:
I am reviewing circuit diagrams of ATX power supplies. I have noticed
this in almost all different designs of ATX power supplies. Different voltage power
rails output filter share a one core [ toroid ].

Is there is a specific reason for this or this is just to reduce the core size and
number of components?


texts: Transfer function of OP Amp circuit system?

texts:
I have this circuit here, and I'm fairly certain the function I have is correct but I just wanted to be sure. I am also a little thrown off from the resistor connected to the + of the op amp. The function I came up with is:
$$\frac{V_o}{V_i}=\frac{R_2C_2s}{(R_1C_1s+1)(R_2C_2s+1)}$$


texts:
My question is about the CD4015BE that i would really want to use in one of my projects, but i can't figure out how to make a carry out for the second register. In the datasheet they mention that it is possible, but i just can't seem to figure out how to do it. Some clues would be greatly appreciated.

Datasheet


texts:
My question is what is the difference between +12v and -12v. Can anyone explain it with a practical example approach.

can any one explain the real need of negative voltage(-9v). please try to explain in electron flow level, so as to get a clear idea. It's always confuses me. If question is repeated forgive Please. I want the real practical concept behind these supplies.


texts:
How can I calculate the current carrying capacity of a DC copper bus bar with respect to temperature?

Bus bar specifications:
Copper Busbar

Width=40mm
Thickness=6mm
Ambient Temp5 (C)=4


texts: How do I study the effect of body bias on threshold voltage with a plot of Ids vs Vgs for different values of Vbs using LTSpice tool?

texts: How can I get the plot for different values of VBS in a single plot so as to clearly show the threshold voltage variation?


texts:
Got a battery powered night lamp that's supposed to stay on for 10 minutes. But it only stays on for 10 seconds...
The pcb inside is not documented, and I have no idea how to change it.
Found this circuit online.
http://2.bp.blogspot.com/-SNrJNtauf1E/T5_bMrg8duI/AAAAAAAABOk/AK8hXbJP6bA/s1600/delay+timer+improved+circuit.png

How can I adapt it to work for 3v (the lamp uses two AAA batteries)?


texts:
I'm using this circuit design:

Link to original project page with schematic on EEVblog forum
I changed some values:

R1:220 ohms
R3:470 ohms
C1:470pF
M1: TIP41C.

When I turn the converter on and connect a 500mA load, the output voltage significantly drops from 5.6V to 4.6V, and there is a voltage drop across my inductor.
Is there any fault on my side? I used every other thing of same value except the components above.
Is my inductor saturating? I'm getting 0.07V drop across it, which is odd.
Any ideas what is going on?
(By the way, I'm stepping up 3.7V to 5V for LED strip. I like discrete.)


texts: What components do I need to connect a phone to my device via Bluetooth?

texts:
I have a phone I want to connect to a docking station I am making, via Bluetooth for as cheap as possible. As I understand the situation, all I need is something that can pick up a bluetooth signal from a smart phone, and relay it to a chip (in digital form preferably).

Could this purely be done by a bluetooth antenna? Or does this antenna need to be connected to other components to process the information it is receiving, in which case, it would be better off getting a module like the microchip RN-42?

Apologies if this is a naive question, have tried to do my research but I do not know enough electronic technical lingo to work it out myself.


texts:
I've been designing some active bandpass filters and, while in simulations it works great with ideal op amps, I'm not sure how to go about picking an op amp from a distributor.

Obviously there are an uncountable amount of options when it comes to choosing parts, and I can do my best to narrow down to what I need, but even then there's 1000s of options.

I'm not a super technical person so it's difficult for me to look at a datasheet and go "yep that's the one I need." In this case, I'm not trying to amplify the signal in the active bandpass filter but simply maintain it (as best I can) from any attenuation. I've been referring to this (very) simplified guide about active bandpass filters http://www.electronics-tutorials.ws/filter/filter_7.html.

I'm dealing with a 5V DC supply and will be breaking a signal with possible frequencies 20-20kHz into 5 filters (0-250, 250 - 500, 500 -2k, 2k-6k, 6k-20k). I'm not looking to boost the signals but rather preserve their original strength as much as possible through the filter. The filter doesn't need super sharp cutoffs as it won't be doing anything precise but powering a LM3914 Dot/Bar Display Driver (unless that is precise, what do I know).

The five filters are to be in parallel receiving the same signal input which will have an amplitude range of 300mV - 2V. Each output to the filter will drive its own LM3914, for a total of five LM3914s.

So what it boils down to, is what am I actually looking for in an op amp to create active filters? Are there any well known op-amp designs commonly used for filters?


texts: How to transmit UART from STM32 to PC without TTL to USB converter?

texts:
I have a STM32F429 Discovery but not have a TTL to USB converter. I wants transmit and receive data (String) with UART of computer and STM32. Have a way to implements this on the board, using HAL drivers? Or other way without a board with TTL to USB converter?
I searched for tutorials, but I didn't find a good and comprensible.


texts: Noise equivalent power of thermopile sensor?

texts:
I am working on the characterisation of thermopile sensor and stuck in determining the NEP of the sensor.
My thermopile sensor with AD8630 amplifier receives IR radiation coming from the blackbody at 500K. To calculate noise equivalent power I have calculated output voltage of the thermopile by simply taking the output of the sensor and power incident through power meter but I am not sure how to calculate the noise voltage ? should I take Johnson noise as the noise voltage ? if so then how can I calculate it ?
Please, someone give me an idea about how to deal with NEP in such situation.
Thank you and stay safe


texts:
I'm building an light communication device(pretty much lifi) using AM and am mostly done with every part except for demodulating the signal. The signal looks like with a 1.8432MHz carrier wave(serial communication at 115200Hz). The receiver consists of a photodiode, amplifiers, filters, and it requires an envelope detector or a circuit that outputs high when theres a AC signal present.

I've tried using a

A full and half bridge rectifier(with capacitor)

A lot of signal is suppressed with this can capacitor just shunts everything to ground.

Envelope detector (https://en.wikipedia.org/wiki/Envelope_detector#/media/File:Simple_envelope_detector.svg, basically peak detector):

It produces a lot of voltage spikes from capacitor discharging and does not really produce any recognizable demodulated wave

A diode and transistor

Transistor has quite a high breakdown voltage at 0.7V and the capacitor's response time is way too fast

A diode and capacitor

This circuit works for low signal frequencies but fails at higher signal frequencies

I'm also considering using a slow op-amp with response time faster than signal but slower than carrier wave, would it be reasonable? If so how should I build the circuit. Will there be any better options?

I have access to basic resistors, capacitors, some transistors and diodes, other components would have to be sourced.

Voltage graph after amplification and filtering:

Voltage graph with diode pointing away from ground:

Amplifier with filter:

Circuits tried:


texts: Correcting harmonics for power factor correction

texts: Is it recommended to use LINE REACTORS to mitigate harmonic issues on a power distribution system if there are power factor capacitors installed?


texts:
I see many custom designed FFC cable in laptops and tablets like the yellow and black cables on my UX305 laptop (shown below).

How can I design a similar FFC cable? Is it the same as PCB design layout?
How much it cost for  a single layer FFC with 1.5" length on a small run (10 to 20 pieces.)
What design rules should I consider moreover to normal PCB to get it work with a FPC connector.


texts: Is upsized reactor allowed for the comparitively less motor HP?

texts:
We have a LV-MCC in our commercial outlet having a 480 VAC, 15 HP VFD with line and load reactors in series with it. The VFD is sized for 22.0 A (normal duty), the motor has a horsepower rating of 10 HP (yes this  is comparitivey lesser horsepower than what it should be, but it is to be replaced in future with 15  HP motor) and the circuit breaker is having a trip rating of 60 A. However, the line and load reactor is rated for 25 Amps. With respect to the reactor selection catalogue (the manufacturer's guideline), it is recommended to use the 25 amps reactor (for both line as well load).The catalogue recommends the reactor rating based on the VFD Amps (of course different for normal and heavy duty) rating and not the motor HP. So, with respect to the guidelines mentioned,

Does upsized reactor will have any adverse effects on the behaviour of the system or affect the life of motor?
How is the reactor rating decided, is it dependent on VFD amps or the motor HP? (As far as I know, the VFD rating is selected using the FLA rating of the motor and it's service factor, and an upsized VFD wont cause any hindrance in the desired operation of the motor, except the increased cost of VFD.)
How can I calculate the reactor ampere rating for the specified motor HP or VFD ampere rating?


texts:
I'm designing a battery powered circuit where I would like to charge the battery via USB, and monitor the remaining battery capacity during operation.

I'm using the following IC's:

MCP73831 (charger)
BQ27441 (gauge)
AP7217 (LDO)

The LDO can be driven from the battery or USB. If the both battery and USB are connected, the MOSFET Q3 should disable the battery from the LDO and let the USB drive the LDO while also charging the battery. Everything works fine except one thing that I don't understand.

If I only connect a USB cable to the device, the yellow diode D11 is active, meaning that MCP73831 is charging the (disconnected) battery. Looking in the datasheet of MCP73831, description of battery detection:

"A 6 μA (typical) current is sourced by the VBAT pin to
determine if a battery is present or not. If the voltage at
VBAT rises to VREG + 100 mV (typical), the device
assumes that a battery is not present. If the voltage
stays below VREG + 100 mV (typical), the device
assumes that a battery is detected. In order to correctly
detect a battery insertion, the impedance seen by the
VBAT pin before the battery is connected must be
greater than 2 MΩ."

I have two questions. The first one is about the theory of the quote above. Why would V_BATT rise above VREG(4.2V) + 100mV when the circuit is sinking this small current and no battery is connected?

Secondly, why would V_BATT in my circuit NOT rise above this voltage and thus make the charger believe that a battery is (falsely) detected?

Thanks :)


texts:
Anyone used one of the FT2232H chips from FTDI?

Specifically, how do you figure out the permissible baud rates?

The data sheet is kind of vague, and I have to pick something in the 1-3 MBaud range but need to know what my options are.


texts:
I am trying to observe the effect of a negative voltage on the NMOS4 model in LTSpice. I have a DC sim running and a step parameter for the voltage. However the current curve (and threshold voltage) does not change. I have included a picture with the current and body voltage, and the ASC code. I have also tried including K1 and PHI parameters but the threshold voltage still doesn't change.

Here is the ASC file.
SHEET 1 1880 756
WIRE 1184 -192 960 -192
WIRE 1184 -112 1184 -192
WIRE 960 -96 960 -192
WIRE 1088 -48 960 -48
WIRE 912 -16 784 -16
WIRE 1088 -16 1088 -48
WIRE 784 32 784 -16
WIRE 1088 96 1088 64
WIRE 1088 96 1056 96
WIRE 784 128 784 112
WIRE 960 128 960 0
WIRE 960 128 784 128
WIRE 1056 128 1056 96
WIRE 1056 128 960 128
WIRE 1184 128 1184 -32
WIRE 1184 128 1056 128
WIRE 1056 176 1056 128
WIRE 1152 368 928 368
WIRE 1152 448 1152 368
WIRE 928 464 928 368
WIRE 1056 512 928 512
WIRE 880 544 752 544
WIRE 752 592 752 544
WIRE 1056 656 1056 512
WIRE 1056 656 1024 656
WIRE 752 688 752 672
WIRE 928 688 928 560
WIRE 928 688 752 688
WIRE 1024 688 1024 656
WIRE 1024 688 928 688
WIRE 1152 688 1152 528
WIRE 1152 688 1024 688
WIRE 1024 736 1024 688
FLAG 1056 176 0
FLAG 1024 736 0
SYMBOL nmos4 912 -96 R0
WINDOW 3 56 60 Left 2
WINDOW 123 56 88 Left 2
SYMATTR Value testn
SYMATTR Value2 l=0.25 w=0.375 ad=0.3u as=0.3u pd=1.875u ps=1.875u
SYMATTR InstName M1
SYMBOL voltage 784 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL voltage 1184 -128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 2
SYMBOL voltage 752 576 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value ""
SYMBOL voltage 1152 432 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -2.4
SYMBOL pmos4 880 464 R0
WINDOW 3 56 60 Left 2
WINDOW 123 56 88 Left 2
SYMATTR Value testp
SYMATTR Value2 l=0.25 w=1.125 ad=0.7u as=0.7u pd=2.375u ps=2.375u
SYMATTR InstName M2
SYMBOL voltage 1088 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value {V5}
TEXT -56 -32 Left 2 !.MODEL testn NMOS (kp=115u vt0=0.7 lambda=0.01)
TEXT 912 -312 Left 2 !.dc V1 0 2.4 10m
TEXT -72 616 Left 2 !.MODEL testp PMOS (kp=30u vt0=-0.7 lambda=0.01)
TEXT 1496 424 Left 2 !;dc V4  -2.4 0 10m V3 -2.4 0 0.4
TEXT 1464 -152 Left 2 !.step param V5  -5 0 1


texts: Micro Converter with ADC/DAC peripherals

texts: I bumped into an interesting device ADuC841. It seems to be a microcontroller with extensive ADC/DAC peripherals. Since I am not experienced and did not have to use combination of ADCs and DACs, going though the datasheet does not give me a good insight about the device. Did anyone use it before? I wish someone could provide some examples where the use of this device would be more efficient than using other uCs and ADCs. Although, this device costs about $20 a piece, but I would rather want to know the technical advantages.


texts: Unity Power Factor Correction from Waveforms

texts:
So I needed to find a value for a capacitor (Zx, where the resistive component is zero) to perform power factor correction (PF = 1) on the following circuit:

w = 1250

ZL = (98.1+157.5)+j(1250)(0.15)
Rt = 1k

I calculated that I need a capacitor with value C = 1.032E-7F, so I used a 0.1uF cap and measured voltage waveforms of the source and load with the NI MyDaq (garbage, but we have to use it for our lab class.) I realized that I need to be looking at the current waveform though. I obtained the following waveform:

This shows the voltage of the capacitor/load node is in phase with the source. However, I have no way of measuring current. I know that i = C(dv/dt) for the capacitor. So the current waveform would be 90 degrees out of phase with both voltage waveforms. Similarly, the inductor equation for current (Zl has an inductor of L = 0.15 H,) has an integral so it introduces a phase shift.

My question is as follows:

Is looking at the voltage waveform for the inductor and capacitor and deducing the fact that each respective current's phase offset will cancel with the other enough to say that we actually have achieved a unity power factor?


texts:
We have an AC voltage source connected to an ideal inductor that has no resistance.The inductor is wound around a ferromagnetic material.  The maximum value of the driving voltage source is big enough that it will drive the core into saturation during the first positive half cycle.

Will the induced emf be zero over the interval of saturation, and what will be the value of current over such an interval?

I think that the induced emf should be zero over the interval of saturation because the change in the B-field will be zero and consequently the time derivative of magnetic flux is zero.  But that leads me to a contradiction because the driving voltage is not zero during saturation then, how will the voltage across the inductor be zero ?


texts: Distortion Analysis for OpAmp integrator

texts:
Is there a reference for distortion analysis of an opamp interator:

where the amplifier has finite gain a1 and a third order distortion coefficient a3 such that the open loop voltage can be described as vo = a1 vx + a3 vx^3?

Suppose C is replaced by Rf, then the distortion is frequency independent and using Taylor series and coefficient comparison, the new coefficients can be found as:

vo = b1*vi + b3*vi^3 (closed loop)
vo = a1 vx + a3 vx^3 (open loop)
(vi-vx)/R = (vx-vo)/Rf ->
vx = vi Rf/(R+Rf) + vo R/(R+Rf)

b1 = a1 Rf/(Rf+(a1+1)R)
b3 = a3 Rf^3 (R+Rf)/(Rf+(a1+1)R)^4

Now I can do the same thing by replacing Rf with 1/sC and arrive at:

b1 = a1/(1 + sRC(1 + a1)) = H1(s)
b3 = a3(1 + sRC)/(1 + sRC(1 + a1))^4 = H3(s)

Suppose I enter a single tone at f1 = 1 MHz then I should get a third order distortion (filtered) at f2 = 3 MHz and evaluate the HD3 as

HD3 = 1/4 abs(H3(j*2*pi*1e6))/abs(H3(j*2*pi*3e6)) * vi^2

but the result is different from what I get with the circuit simulator. Hence I am afraid the situation is more complex here (even with just one tone) and I am looking for a reference where this has been worked out.


texts: Using any/all Ethernet wires for power transfer?

texts:
I was looking to get a small amount of power to be transmitted ~100ft, and noticed there is a standard way to move power over Ethernet cables.

We actually plan to splice the cables ourselves, and not use a standard Power over Ethernet, but wanted to confirm how much power I can dependably pass through a single pair? There will be no data transmission, no Ethernet devices. Only DC current.

Further, I wanted to know if it makes a difference which wires I use? I am not sure whether all 4 pairs (8 wires) are the same, or if only certain ones are built specially for power, while the others might be inappropriate for power, and only dependable for data?

Edit: Additional details: I have a transformer plugs into the 120V wall plug, and it says it outputs 5V 1.2A. So that is what I want the cable to support. I plan to cut the small wire coming out of the transformer and extend it using ethernet wires. If ethernet 1 pair is enough, I might do that. Or I might use 2 pairs just to keep the two transformers and end devices completely separate.


texts: Turns ratio of multi winding transformer

texts: Hi can anyone let me know what is the overall turns ratio of the transformer shown in image below as i was confused


texts:
The purpose of the application is to maintain a constant current at the load, even if the resistance changes.

I understand that the ADC is reporting the voltage and current values at the load to the micro controller. Also, that the load voltage is being measured by the differential amplifier (U4) and the current is being measured by the current-shunt monitor (U7), set up for low-side detection.
Please correct me if I'm wrong on any of this.

I believe the DAC is keeping the current constant by suppling a voltage to the positive terminal of op-amp (U6). Since the curr_out is a voltage value it also fed into the other terminal and I believe this difference is driving the gate of the transistor.

Yet, how does this keep the current constant at the load? Furthermore, why is there a zener diode between LOAD+ and LOAD-?

Also,is the 23V above the load, supplying the current while the transistor is working to keep is constant from the difference in DAC_OUT and Curr_out?

I just can't seem to rap my head around how this works?

A4V5 is 4.5V


texts:
Every time I read something about RAS e CAS there are mentions to the "DRAM" word.
The only difference that comes in mind is the presence of a latch/counter and registers in case of the DRAM. However I suppose that they can be both organized in a Row x Column fashion and use the same logic that is: select and read a row and extract a word (a set of columns) from that row.

So why are the RAS and CAS signal only used for a DRAM and not for a SRAM ?

How would a memory like this be implemented using SRAM ?

(This is a 32M x 8 DRAM chip)


texts: I am designing a small power amplifier similar to the circuit below, and I would like to have a volume control on the input. My understanding is that I can't just put a voltage divider on the input, since then the spectra of the filters on the input would change. I can't just have the pot change the gain of the amp continuously, since it has a minimum gain of 10. I figured I could just precede the input with a voltage divider and a unity-gain voltage follower, but I wasn't sure if there were some more elegant solutions or techniques available. Thanks!


texts: How to get rid of voltage drop of this timer circuit?

texts:
I'm getting ~ 12VAC pretty stable without load with this circuit

However when I try to convert this signal into 6VDC up to 500mA or 1A with AC to DC conversion and a regulator;

I get huge voltage drops on Timer circuit. AC voltage oscillates around 7 8 Volts, converted DC voltage going into regulator drops down to 1 V. So I don't expect to get anything from output of the regulator. Any thoughts or explanations would help me a lot since I just started my career and willing to learn more and more! Thanks!


texts: Using a DMM to measure output isolation/crosstalk

texts:
I'm making some PCB's that have some DC to DC converters on them with three 5 Volt converters, one 15 volt converter, and a converter with +/- 12 volts DC.

On the PCB the output pins are in a connector that are fairly close to each other. I want to make sure that there is isolation between all the supply outputs. The +/-12 supply shares the same common between them, but I"ll have to check to make sure that common isn't shorted to the +15volts for example.

I need to be able to test about 20 of these boards.

My idea is I'm already doing line/load regulation on these supplies so I have the DMM in VDC mode. After the line/load regulation test, I leave the positive lead of the DMM on the first supply, then I move the negative lead to each supply. I should measure the supply voltage output of the first supply, then zero VDC moving the negative lead to each supply.

Then I move on to the next supply leave the positive on that supply, and test all the negative pins making sure they are 0 VDC.

My question is, should I also do this for the positive pins for each supply?

Example: Now leave the Negative lead on the supply, and move the Positive lead to each supply making sure it is also 0VDC, or would this step be redundant?


texts:
I'm looking into building a custom gauge cluster for a project truck. The fuel level sending unit that I have will read 40 ohms when the fuel tank is empty, and 250 ohms when the fuel tank is full (it's just a potentiometer). Most aftermarket fuel gauges are designed to work with a sending unit that is 0 ohms when empty and 90 ohms when full. I am looking into designing a resistance converting/scaling circuit so that I can interface a standard aftermarket gauge to my factory fuel sending unit, but I am not sure where to start.

While researching, I came across the Negative Impedance Converter. Would it make sense to stack two "Negative Impedance Converter's" in series for my application?


texts: how does the circuit of a basic Variable speed electric drill work?

texts:
i am trying to 'automate' the control of an electric drill motor that im taking from a garden variety Variable Speed drill (from Harbor Freight)

it has a universal AC motor which I basically undertand and a DPDT switch to reverse direction and a triac citcuit to vary speed

Question 1 . i see 4 wires going to the 'field/Stator coil(s)'. Are there 2 seperate field/stator coils here? is this to provide low/high power.  I think in theory , you only need 1 coil with 2 wires and that coil is wired in series with the brushes... is that right?   how does this circuit work with 2 coils.

Question 2 . how does this variable speed circuit work.  is the wiring diagram correct (it doesnt show a variable resistor and it doesnt show what drives the control input of the traic? why are there two switches in the thing? does switch 2 close at high speed and thus shunt around the triac?

please see the attached 4 diagrams


texts:
I have somewhat successfully installed Cat5e cabling in my home, which works flawlessly for 10 and 100 Mbit/s, but I am experiencing severe packets loss at Gigabit speeds, on all of the eight cables. So obviously I must have done something wrong.

I've already verified that all connections have 1:1 mapping (all jacks are wired as T568A) and all pins are connected, using cheap testing equipment.

The obvious next step would be renting the expensive kind of testing device, but I wonder if there is either something obvious that I might have missed here, or that I could try with a modicum of skill and an oscilloscope.


texts: GPIO and clock configuration of STM32F427VG

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I am very new in STM32 projects and it is my first time writing a program with STM32. I used to program with AVR and now I should progress to STM32. I have a board with STM32F427VG on it without any external XTAL. I wrote the following code to make a simple LED blink:

#include "stm32f4xx_conf.h"
#include "stm32f4xx.h"
int main(void)
{
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);

    GPIO_InitTypeDef GPIO_InitDef; //Where GPIO_InitDef is variable to work with struct
    GPIO_InitDef.GPIO_Pin = GPIO_Pin_4 ;
    GPIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;
    GPIO_InitDef.GPIO_Speed = GPIO_Speed_50MHz;
    GPIO_Init(GPIOA, &GPIO_InitDef);
    GPIO_SetBits(GPIOA, GPIO_Pin_4);
    GPIO_ResetBits(GPIOA, GPIO_Pin_4);
    int i;

  while(1)
  {
    GPIO_SetBits(GPIOA, GPIO_Pin_4);
    for (i = 0; i < 500000; i++);
    GPIO_ResetBits(GPIOA, GPIO_Pin_4);
    for (i = 0; i < 500000; i++);

  }
}

I use Embitz to compile my code. In order to configure the internal clock I use the following configuration:

Then I press run and then generate. Then I copy the generated system_stm32f4xx file and replace with the default system_stm32f4xx file in the project.

Still, I can't see any change in the LED.

I know I am very new in STM32 projects, so most likely this question is very simple for anybody. Thanks if anybody helps me to find the problem.


texts: How to add power terminal pins in PCBNew in Kicad?

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I am trying my hands-on with Kicad recently. I have created an LED astable multi-vibrator circuit in the Eeschema as follows.

Then I have created a PCB out of it as below.

I wanted to add the two power supply pins on the PCB. So, I used two SolderWirePad_single_0-8mmDrills.

But then I needed to connect these two drill points (+, GND) to the actual tracks of the circuit.

I did this before successfully for the POS(+) terminal encircled in PINK colour.

But now I cannot add a track for the (GND) terminal encircled in RED  colour (seems like I am missing something).

Whenever I am adding a track starting either from one of the emitters of the BC548 or from the GND drill pin, the track is not added after the double clicking on the ending terminal. (Please note: I am able to draw the track, but, it seems something is not validating, may be, the connection.)

How to get the power supply tracks when there is no connection in the schematic?
Is there any better way to handle this?

Thanks in advance.


texts: Circuit topology name and function for PNP transistor in light barrier circuit

texts:
I have seen this rather simple circuit for end position detection of a DC motor drive mechanism. An infrared LED (V402) and a phototransistor (V401) are used as a light barrier.

Can someone give me a hint concerning the circuit topology name and function of the additional BC856A (V403) PNP transistor in this circuit? (Is it a current amplifier?)

Isn't this circuit design very susceptible to ambient light and also temperature variation?

Edit1: Here is the simulation result of this circuit. It seems to have a current to voltage gain of 20V/mA.


texts: Micro controller reset due to noise, PCB design for noise immunity

texts:
After making this PCB, I learnt the importance of ground plane. Besides ground plane, there is considerable amount of theory behind PCB designing which can provide immunity against ESD, surge, EMI, RFI etc.

After reading some articles and following the suggestions on my previous post, I am trying to make another PCB.

I haven't routed whole board yet because I am not very sure about the robustness of this layout against EMI, RFI, ESD etc. Since this takes experience, I need suggestions from you.

Here is what I am planning to do next:

1) Route most of the PCB on top layer so that I can provide a huge GND pour on the bottom layer in DC zone. (No GND pour in ac zone)

2) Route the remaining board, making sure that decoupling capacitors are as close to micro-controller as possible.

3) Use smd caps and resistors so that I can provide a bigger and continuous ground plane.

4) Keep current loops smaller so as to reduce internal EMI development.

5) Provide ferrite bead at incoming ac power lines to suppress sparks.

Besides this, what other improvements do you suggest for increased stability of this circuit? Any constructive suggestions from your side will be very appreciable.


texts: using ADC on the current output of a sensor

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My project uses a LEM LAH 50-P current sensor. Current will vary between +/- 22 Amps. The project uses a Texas Instruments TMS320F28027 MCU which operates at 3.3 V. The output of the sensor is a current equal the sensed current / 2000; the output will vary between +/- 0.011 A.

I'm trying to implement the resistor network by following this post which describes a summing amplifier. The post describes the input as a voltage source with all resistors of the same value. Also a comment to the post notes that the attenuation resistors can be incorporated into the circuit thereby saving on parts. Would the following design work? How to design for V1, R1, and R2?

simulate this circuit – Schematic created using CircuitLab


texts: Persistent memory on msp430 without FRAM

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For persistence in FRAM-enabled msp430 there are convenient "noinit" and "persistent" variables...

For flash-based MSP430G you need to use flash memory. There is a demo for it.

How to make it simpler? Is there more easy to use persistence example which provides abstraction of flash erase, lock, some "calibration constants" etc., hopefully also providing portability between different msp430g2*. (Also how to tell the compiler to put a variable to some specific flash segment?) I.e. to simulate "noinit, persistent" on FRAM-less controllers.


texts: What do capacitor markings in dash-dot style mean?

texts:
I have got a few capacitors in my sortiment which have got dash-dot markings above and below the value code, like this:

What do these dash-dot codes mean? Do they reflect voltage rating or temperature dependency, or do they just denote a production date/lot?


texts:
I'm trying to learn Altium and would like to know if someone can point me in the right direction here or if it's even possible to do this.

So I've created a 20 pin symbol on a .SchLib for an IC and then placed it on a schematic .SchDoc so I can build my circuit, nice and easy no issues here. I then unlock the pins and re-arrange them as I see fit for better readability, so far so good.

Then I noticed I wanted to make the rectangle surrounding the pins bigger, but can't figure how to edit the symbol's graphic within the .SchDoc schematic (or create a new instance with my preferences without disturbing the original) unless I go and edit it right on the .SchLib it was originally created. But if I go and edit the symbol on the .SchLib and then update the .SchDoc the pin arrangement I had done is gone.

I looked to see if maybe there is a way to lock the update so that the pins arrangement or something of that sort. In orcad capture I just update the symbol right on the schematic and it creates a new cached version without disturbing the original.


texts: Covering asynchronous reset behaviour in SystemVerilog Assertions

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I have been assigned to write SystemVerilog cover-directives in a verification plan for a block
One of them is to cover a functional check for an asynchronous reset mid-packet. There are three steps to this as follows:

Check if a signal, tvalid is asserted (registered w.r.t posedge of the clock)
Check if asynchronous reset is deasserted (active low)
Check if the signal, tvalid is de-asserted due to the reset

I have come up with the following sequence to cover this
sequence seq_reset_n_check;
    @(posedge clk) tvalid ##1 @(negedge reset_n) 1'b1 ##1 @(posedge clk) !t_valid[*3];
endsequence

cov_seq1 : cover sequence (
    seq_reset_n_check
);

I tried testing this locally but I cannot seem to cover the behaviour I want. Any help will be appreciated!
Edit:
This is how it would like in SystemVerilog code.
initial begin
    do begin
        @(posedge clk); @(negedge reset_n);
    end while (!valid);
    repeat (3) begin
        @(posedge clk);
        assert (valid == '0);
    end
end


texts: Why is power gain a meaningful quantity at all?

texts:
I'm quite confused at a very basic concept: power gain.
An amplifier can be said to have a power gain of x decibels. The gain of an amp in decibels is never voltage or current, it is always power. But let's say I was given some black box amplifier with some power gain. Since I'm only given the power gain, I don't really know the output voltage of the amplifier. I can feed the amp with some known input voltage, and given the input impedance of the amp I can calculate the input power and therefore the output power. But aren't we usually more interested in how much output voltage we are getting from the amp?
For example, if I wanted to use the amp to amplify some weak audio signal to feed it to some speakers. The amplitude of the speaker vibration is not really a function of how much power is dissipated in the speaker (let's assume a simple dynamic coil speaker), but rather how much current is flowing through it (right?).
I find it quite difficult to express my confusion as a question but I hope somebody understands.


texts: Battery life calculation - depending voltage levels

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I wonder calculation of the battery life, depends of its voltage level. Basic calculation of battery life is given below:

Battery Life = Battery Capacity in mAh / Load Current in mAh

However in this formula we are not using any voltage levels. I know that formula is very basic formula, there has to be a constant (0.7 or 0.85), although we can't use any voltage level in this formulas. How we can read the datasheets to making exact calculation? For an example if I use 3.7 V battery, what is the lasting voltage? What if my limit is 2.7 V in my system, I mean that system will passive under 2.7 V, how will be the calculation? What if I use the limit as 2.4 V? In the basic calculation formula we couldn't use voltage level.


texts: Choosing Correct Switching Power IC for 5v 2A Output from 2S Battery

texts:
I am designing a Power Circuitry for a Application that needs to feed
1x Beaglebone Black (5v),
1x Device with 600mA (5v),
and
2x XBeePro Modules (3.3v)

via a 2S (7.4v 1Ah LiPo) Pack.

The Plan of action was to use 1x 5v@3A Switching Regulator to give power to the BeagleBone,  the Other device and an LM1117 which will give 3.3v to the XBees. Is this approach Correct?

While choosing a DC DC Buck Rectifier, of how much importance does the switching frequency play?

Can i use a MAX16909 for my Application?

Is there any other Switching Regulator for Battery Supplies that i can use? The power source will be a 2S Lipo Battery rated for 1Ah. The MAX16909 takes input from 3.5V to 36V. Should i look for an IC that takes input from 5v-12v for efficiency?


texts: How to interface TMDS signal with optical tranceivers at low cost?

texts:
Not like this which is about protocol, this is about physical.
The HDMI2.0 (18Gbps) fiber optic HDMI cables on market seems to be "cheap", like<$100.
Although optic fibers are very cheap now, but considering those cables contain 4 optic channels which require 4 transmitters and 4 receivers each at least with a rate of 4.5Gbps, and for comparison 10Gbps optical NIC is $100 with only one 10G transmitter and receiver.
Does those cables just connect the TMDS lines directly (or only with some general off the shelf cheap level shifter like ICs) to the optical tranceivers (or even just some off the shelf cheap ICs and a optical diode?) to get such low cost? If so, maybe a HDMI2.1 48Gbps transmitter/receiver can be DIYed (paired with off the shelf optic cables) which is not on market yet.
What is the recommended way to convert TMDS (two sub question:18Gbps and 48Gbps which may be a very different design) signal to optical signals with low cost?
Updated
Phase synchronization between channels is another problem, HDMI is a synchronized bus, the electric-optic and optic-electric converters should have fixed phase shift (and noise) that is compliant with HDMI requirement.


texts:
While reading articles and application notes regarding DACs and their output spectrum, I stumbled across aliasing of higher harmonics to the first Nyquist band. For example, when generating a single test tone with a DAC, harmonics of the fundemental frequency appear due to DAC nonlinearity, and if their frequency is higher than the Nyquist frequency (half of the sample rate), they fold down (alias) to the first Nyquist band.

I know what is aliasing and how it affects the spectrum when sampling with an ADC, but I can't figure out how and why this happens when reconstructing the waveforms with a DAC.

This is an example taken from Tektronix High-Speed DACs application note (https://download.tek.com/document/76W_30631_0_HR_Letter.pdf)

Could someone expain this to me or at least point me to where I could read more about this?

Thanks


texts:
in a project that I am developing, I have a plastic cube with metal contacts, like this:

The cube is 2cm x 2cm x 2cm.
The metal contacts are nails with ~2.5mm diameter.

The center metal contacts (5 in a + shape) are designed to be a code (5 bits), and each plastic cube will have a different code. The 6th pin is a reference pin, so that the user can place the cube in all rotations.
The cube has magnets on the corners so it stays in place on the pcb board.

I want to be able to detect the metal contacts with a PCB, but I don't know the best way to do it. Currently I am thinking on a design like this (sorry for the low quality):

In the image it shows 6 pads but there will be 9 in a 3x3 arrangement
The center 5 are the code-pins, and the outer 4 are so that the reference pin is detected, and through software the pins are rotated accordingly.

I would then detect the metal contacts because they would short the pad.
I have seen this design in portable consoles, but using silicone membranes to make the contact.
Would this design work at all? If not, what is a good solution? Also, can anyone tell me how this type of "connector" is called? I can't find anything online. Thanks!


texts:
Recently, I have been working on a battery charger design based on a flyback DC-DC converter and I am curious about one thing: the flyback converter can work in CCM (continuous conduction mode) and DCM (discontinous conduction mode), but most battery charger systems use a flyback set up for DCM and I know the DCM flyback converter can use the valley ZVS.
Is this the reason for ensuring that the flyback converter works in DCM (the valley ZVS)? Is there anything else that could motivate this?


texts:
I am working on PIC18f controllers with USB peripherals and i would like to take advice from those who have worked in similar field.
How do you deal with things like:

1.Some times My pic enumerates well showing Device Recognized and some times it pops up like Unknown device.
What should be the real cause and how can i fix it?

Im confused about where to look for leaks in this problem.

  The firmware for the USB communication is taken from this:
  http://18f4550.com/updated_USB_demo_board/updated_USB_demo_board.html

I suspect this is not a h/w problem as i'm using a crystal oscillator of 16mhz.
I would like to have your insights to debug this project.

Yours faithfully

Arookie


texts: Confusion with RPM calculation of a DC fan from its datasheet

texts:
I want to calculate pulse periods from a tacho output of a DC fan. I want to read pulses by a MCU and convert them to RPM and display in LCD.

But I'm confused with the following description of RPM conversion from the manual:

It seems they mean I should read two consecutive periods and obtain T0.

So N = |60/T0| rpm (?)

My confusions are:

1-) Why would I need two sum periods but not use a single one? Aren't they almost the same for a constant fan speed?(Because in coding it will be more difficult to implement to calculate two consecutive periods)

2-) Why are there 1/4 in both sides of equation? And is N = 60/T0 where T0 is the sum of two consecutive pulse periods?


texts: BLDC Y-shaped motor with Hall sensors generating different combination of back EMF on windings with different direction?

texts:
I have a BLDC Y-shaped motor.  I connected the Hall sensors and winding to a logic analyzer to see the combination of back EMF on thr windings. My intention is to eventually create a commutation table to spin the motor with sensors.
With the logic analyzer, I manually spin the motor in, for example, clockwise direction, and see the output on analyzer as the following:

So based on the back EMF and Hall sensor combination, let's say I decide to assign these three windings to be U, V, W as shown in the above picture
Then, I spin it in reverse direction, in this case counter-clockwise, and then I see the following:

As shown, the combination does not match.
I was expecting to see when at the same state of Hall sensors (which means the positions are the same), both directions should cause the windings to have the same back EMF, either HIGH or LOW.
Did I misunderstand something? How can I see different combinations of windings<->Hall sensors just because of spinning in different direction?


texts: What can go wrong when producing an ASIC from an FPGA-verified verilog design?

texts:
Given a Verilog design fully validated on an FPGA prototyping system, and someone who has never done an ASIC before, what are the chances that a service like CMP will ship fully usable chips on the first try? As far as I can tell, they provide the cell library and the tools, and do a DRC, so in theory it seems like just taking the RTL and compiling the design with their cell libraries should result in a usable chip.

What kind of things can go wrong when moving an FPGA-validated design onto a basic process like CMP's 0.35μm CMOS process?

If the design works on FPGA but not on the chip, is it debuggable without very specialized services like decapsulation and microprobing?


texts:
I've built my own version of 8-bit computer based on various examples in the Internet. Once built I started to face some issue with unpredictable memory changes when it was not supposed to. After I'd spent couple of days debugging I found out that the problem was caused by a chip implementing combination logic. An output of the chip was switching from 1 to 0 unpredictably with no particular rule. Ensuing digging helped me to realize that the problem could be caused by the schematics of one of the inputs. (See the picture).
Once I removed the LED,I let the schema work for a couple of hours and it worked with no issues.
I wanted the input of the HCT10N to be either 1 or 0 based on the switch position and LED to indicate the mode of the schema.

Question: Does it mean that actually I can't pull down the IC input through LED? Looks like I can't 'cause LED drops up to 2V and CMOS logic can treat it as a logical 1.
Thanks a lot!


texts: Half H Bridge for Arduino Motor with Braking

texts:
I'm fairly new and still learning so please forgive me if this isn't the most technically correct wording or diagram.

I built a circuit to work with Arduino using PWM and a simple MOSFET. My motor is 7.4 amp stall current and about 1-2 amps running. It's running off a 12.4v Lipo pack.

However, I now need to support braking. I don't need to support reverse and so many of the drivers out there are h-bridges, and I gather I only need a half h-bridge.

On paper, a half h-bridge appears to be just two MOSFET transistors. I can control speed with PWM on one, or set it to low and short the motor with the 2nd MOSFET for braking.

However, my circuit doesn't work, and I'm not sure why. I read some things and I'm thinking maybe it's related to voltage difference on the gate. In my old circuit, the MOSFET was used on the negative line for the motor, but that won't work with a half h-bridge.


texts:
I have been building a synchronized I2C slave receiver with Verilog.

The I2C slave receiver did not encounter any issues when I simulated it with Modelsim.  However, it does not function properly when it has been programmed into a (Cyclone V) FPGA.

Below is the waveform from Modelsim simulation:

With the Signal-Tap analyzer on the Quatras program, I have
observed two issues on the synchronized counter of the I2C slave. I do not know the root causes of the two issues, please give advice:

Bug #1: Counter number unstable.

Bug #2: Unable to detect input signal(SCK) rising edge.

Here's the Verilog code I used for the counter to detect the SCK rising edge, I have altered the counter to a switch statement as an attempt to fix counter number unstable, but it does not work:

always @(posedge clk)
begin
    if  (SCL_buf == 0 && SCL == 1) // posedge SCL
        begin
            // Read the Value
            if(WR_Active == 1)
            begin
                // Count Up until Byte Write is completed
                if(Bit_Count < 8)
                begin
                    Bit_Count_wr = 7 - Bit_Count;
                    Byte_in[Bit_Count_wr] = SDA;
                    //Bit_Count <= Bit_Count + 1;
                    case(Bit_Count)
                        4'b0000 : Bit_Count <= 4'b0001;
                        4'b0001 : Bit_Count <= 4'b0010;
                        4'b0010 : Bit_Count <= 4'b0011;
                        4'b0011 : Bit_Count <= 4'b0100;
                        4'b0100 : Bit_Count <= 4'b0101;
                        4'b0101 : Bit_Count <= 4'b0110;
                        4'b0110 : Bit_Count <= 4'b0111;
                        4'b0111 : Bit_Count <= 4'b1000;
                    endcase
                end
                // Acknowledge + Address Check/ Write Byte Process
                else
                begin
                    Bit_Count = 0;
                    //........
                    end
                end
            end
        end
        SCL_buf <= SCL;
    end


texts: Can I drastically undervolt/underpower a relay?

texts: For instance, if I have a 24VDC/10A relay would running significantly less current (say 12VDC/2A) through it cause it to not operate properly?


texts: Confusion about Diagnosing Problems with a Commutated (Brushed) Motor

texts:
Recently I have been "brushing up" my knowledge of commutated (brushed not electronically commutated) motors. I came across this short video describing tests that can be done to diagnose wound rotor armature problems, and it has throughly confused me.

In the video there are 2 tests that are conducted. The 1st is checking the resistance between commuter bars that are 180 degrees apart, if there is a consistent low resistance between them the test is passed. The 2nd test involves checking resistance between adjacent commutator bars, again if there is a consistent low resistance between them the test is passed. I understand that the windings on the rotor are terminated on the bars of the commutator and therefore it makes sense for some pairs to read low resistance, but it seems odd to me that both the adjacent and opposite bars would be connected. If you don't have any windings connected to the commutator you would find that all of the individual bars would be electrically isolated from each other, right?

This short video outlines how such a commutated motor functions, and leads me to the conclusion that it makes more sense for commutator bars that are offset 180 degrees to be connected by the rotor windings. On the other hand I came across this post where the diagram shows adjacent commutator bars are being connected by the windings, essentially creating a series circuit connecting every bar of the commutator through the windings. In this configuration it would make sense that both the 180 degree opposing bars would read low resistance when tested as described above, as would any pair of bars. But why wind a rotor in this manner, what am I missing here about how these types of motor armatures are configured?


texts: Initialize variable used in always_ff block

texts:
I have a bunch of (System) Verilog code that uses initialization statements.  This is code for an Altera FPGA.  I test the code using automated testbenches in the version of modelsim that ships with quartus, and it all works fine.  However, I have been trying to move some of our test benches to the cadence simulator, and it is complaining.  A simple example of code that fails is this:

reg [15:0] counter = 0;

always_ff @(posedge clk) begin
    counter = counter + 1'b1;
    display("counter: %4X", counter);
end

This give an error in the cadence simulator that it is not allowed for counter to have multiple drivers because it is used in an always_ff block.

Is this error correct?  Two tools say that code is OK, and one fails.  The rules I have found for always_ff state that "a variable assigned in an always_ff, always_comb, or always_latch may not be assigned in by any other process".  This makes sense, but it seems strange that the initial value would be considered a process, and in any case would make those language features mutually incompatible.

So is there a correct way to use initializers along side system verilog new style always_* processes?  Does this behavior depend on the version of the system verilog standard such that I might be able to tell my tools which one to use?  Or are my choices to use explicit reset lines only, or stick to old style always blocks?


texts: I am connecting a Dual CD/MP3 Receiver in my boat if I connect the red to positive, do I connect the ground wire to the negative side

texts: I am installing a radio in a fiberglass boat. The instructions call for red o positive and black to ground. Can I use the negative post as the ground


texts: In electronics engineering which is the better unit to work with radians or degrees?What are the advantages those 2 unit provides?


texts: Is the a circuit building software that can accept a music file as the input?

texts:
I am trying to manipulate the output of an audio file. I have been using such things as high and low pass filters and I would love to use a simulation software such as PSpice to simulate before building.

I would need the audio input to be split into the right, left and mono channels to be used as input signals to my circuit.

Is there any software out there than can do such a thing?


texts: When an open-drain output asserts low, where does the line capacitance discharge?

texts:
I was looking at the auto-retry functionality of the TI part TPS2553 (datasheet http://www.ti.com/lit/ds/symlink/tps2553.pdf) and came across something I didn't understand and thought it a good opportunity to ask a general question.

I am going to refer to the picture below to ask this question using it as an example but really I am unsure about this in any situation where you have a line pulled up with a resistor and connected to an open drain output with some similar capacitance.

Referring to the picture below, when the part senses an overcurrent condition, the FAULT pin pulls low. My question is, when this happens where does Cretry discharge to? The only place I could see it discharging is directly into the FAULT pin. However there is no resistance between Cretry and that pin and the FAULT pin specifes a 10mA max current from the datasheet. So wont there be a big current spike when it discharges since there is nothing to limit the current, and this would damage the pin as it's outside the recommended sink current for the pin (datasheet actually specifies absolute max of 25mA sink current for FAULT)? Am I wrong in my understanding about how/where the cap discharges, the fact that the current spike exists assuming I am right about the previous point, or am I misunderstanding the significance of said discharging current spike if I am right about previous 2 points?

Again I am not just asking about this specific case but using this as an example to ask this question. I wonder too about I2C lines. When the I2C driver pulls the line low, where does the charge that was on that line discharge to?


texts: 74AHCT244 did not output the required signal. What could be the problem?

texts:
I am using an STM32 to control my TLC5940, which uses different voltage levels. The circuit layout is in schematic shown above.

I wrote a small program to toggle my Blank pin. At the controller side (BLANK_3V3) I measure a toggle signal from LOW to HIGH. But at the TLC5940 side (BLANK_4V0) my signal is always LOW. What can be the cause?

I have changed the supply voltage of the 74AHCT244 to 5V as according to the datasheet, but no change has occurred. I would be really thankful to hear from you.


texts:
Can someone explain what the Ta line on this zener diode temperature derating graph means please.

The diode is an MCC SMBJ5338B 5.1V 5W zener. I understand the lead temperature (TL) line means derating linearly above 75°C but the ambient temperature (Ta) line suggests to me that the power dissipation is limited to a maximum of about 1.5W no matter what the ambient temperature is. How can the diode then be rated at 5W?

A note from the datasheet says: "Ambient Temperature at 15°C = TA at Mounting Plane. Derate Linearly Above 15°C to Zero Power at 150°C"

I would take this to mean that the power rating is 5W up to 15°C and then derated to 0W at 150°C but this isn't what the graph shows. Any ideas? I'm sure I'm missing something obvious.

Datasheet: SMBJ5338B datasheet


texts: Regenerative Power on DC bus between DC motor and voltage supplier

texts:
Currently, I am looking for a back-EMF solution for brushless DC motor drive. My input voltage for motor driver is 48V (which starts at 50V level and starts to decline until 35V as a feature of fuel cell). However, as I try to accelerate DC motor back and forth during motion, I observe a regenerative power on the input of the motor driver. (after 56V the motor driver disables itself)

Do you know if there is any strategy to compensate this back-EMF on DC bus?
Is there any suitable product which I can use for this purpose?

Here is what I saw on the screen of oscilloscope (I just supplied the motor driver with 28V)

Supplied with 48V. The driver shut downed itself


texts:
I designed a 24V PWM dimmer. Basically, it drives a 24V-LED-strip with low-side switching using a MOSFET driven by a 1-kHz-PWM having 1-100% duty-cycle.

There are no problems when the circuit is supplied with a lab-type linear power supply or 2 series-connected car batteries.

But, when we use a switching power supply (I'm sure it provides enough power), the strip flickers at around 20Hz. Interestingly, no flickering at 100% duty-cycle.

I've no chance to measure the output of the supply, because the circuit is out of my country! So I'm just trying to figure out what could be the problem.

What can cause this? If the supply has a ripple, shouldn't it show itself on 100% duty-cycle? What should/can I do?


texts: Self Inductance in Steady State equivalent model of Brushed DC machine

texts:
The First pic shows the model of DC motor under dynamic conditions.

The above second image shows the steady-state model of the DC motor.

The image below shows the Simplified DC Motor by using a single coil.
I studied and understood the Working of DC motor and I believe the current inside the coil alternates depending upon the speed of rotating. And for this purpose, the Brushes and commutator are used.

If so the current in the coils of DC motor is Actually AC(Alternating Current) for the motor to rotate. Isn't? If so there exist an Inductance(Self Inductance) for the Coil of DC motor.
Whether or not it is operating in Steady-State the inductance should be always used in the model for the reason that current in the coil alternates? But it is neglected in the second model. Why??


texts: Why would a part be available as 4.99k and 5k?

texts:
I was looking at chip resistors, and came across the MORNTA1001AT5, which comes in many resistance values.  The resistor tolerance is 0.1%, so what is the logic of having the part available in both 4.99k and 5.0k versions?  Generally, if you needed accuracy like that, you'd use smaller parts as they are easier to match, so I have no idea why there would be a 4.99k and 5k version.   I'm just trying to determine if I'm missing something fundamental.

Edit:  Could I get an example of where a 0.1% 4.99k would be used over a 5k at 0.1%?


texts:
I have a 2-line telephone that shows when a line is in-use (i.e. if an extension is picked-up, the indicator will light up on the phone).  The two lines are being supplied via 1 RJ-11 cable (1 line on each pair).  Both lines are supplied via the wiring throughout the house but here's the issue:
- The lines DO NOT show as IN-USE when both phone lines are connected to the telephone

When 1 line is connected to the phone, the indicator lights up when an extension is picked up.  I've tried both lines individually and the indicator seems to work fine.  The issue only seems to happen when both lines are connected.  I suspect the voltage is not dropping (indicating an off-hook) but does anyone have any suggestions on where to begin troubleshooting?  Thanks.


texts:
I have an issue with this process where if I include a reset statement, I get an inferred latch. However, if I do not include the reset statement, I do not get an inferred latch on duty_cycle_triangle.

    SIGNAL duty_cycle_triangle : INTEGER := 0;
    SIGNAL count_up : STD_LOGIC;
    SIGNAL tick_zero : STD_LOGIC;

    triangle_count: PROCESS(clk, reset signal, tick_zero)
        BEGIN
            IF (reset = '1') THEN
                duty_cycle_triangle <= 0;
            ELSIF (RISING_EDGE(clk)) THEN
                IF (tick_zero = '1') THEN
                    IF (count_up = '1') THEN
                        duty_cycle_triangle <= duty_cycle_triangle + 2;
                    ELSE
                        duty_cycle_triangle <= duty_cycle_triangle - 2;
                    END IF;
                END IF;
            END IF;
    END PROCESS;

I am trying to design an FSM that will output a triangle wave using a PWM and an FSM shown below:

        FSM_comb: PROCESS(currentState, duty_cycle_triangle)
        BEGIN
            CASE currentState IS
                WHEN triangle_up =>
                    PWM_enable <= '1';
                    count_up <= '1';
                    IF (duty_cycle_triangle > 99) THEN
                        nextState <= triangle_down;
                    ELSE
                        nextState <= triangle_up;
                    END IF;
                WHEN triangle_down =>
                    PWM_enable <= '1';
                    count_up <= '0';
                    IF (duty_cycle_triangle < 1) THEN
                        nextState <= triangle_up;
                    ELSE
                        nextState <= triangle_down;
                    END IF;
            END CASE;
    END PROCESS;

    FSM_seq: PROCESS(clk, reset)
        BEGIN
            IF (reset = '1') THEN
                currentState <= triangle_up;
            ELSIF (RISING_EDGE(clk)) THEN
                currentState <= nextState;
            END IF;
    END PROCESS FSM_seq;

Basically, after every "tick" I want the duty cycle of the triangle wave to increase by 2. After the duty cycle reaches 100, I want the duty cycle to decrease by 2 until the duty cycle reaches 0. Once the duty cycle reaches 0, I want the duty cycle to start increasing from 0 again until it reaches 100 and it starts over.

Does anyone see any problems with my code or can anyone point me in the right direction to correcting any issues?


texts: AVR - Timer0 is not firing if INT5 is enabled in EIMSK

texts:
I'm using an ATMEGA2560.

Compiler: avr-gcc (AVR_8_bit_GNU_Toolchain_3.4.5_1522) 4.8.1

I have setup TIMER0 for periodic tasks:

// Initialize Timer0
TCCR0A = (1<<WGM01); //CTC - mode 2
TCCR0B = (1<<CS01); //Prescale by 8
OCR0A  = (F_CPU / F_INTERRUPTS_SMALL / 8 - 1);// //~15kHz by default
TIMSK0 = (1<<OCIE0A);

This way I can have an ISR of (TIMER0_COMPA_vect):

ISR(TIMER0_COMPA_vect) {...}

All of the above works fine until I enable the INT5 external interrupt:

// From datasheet Table 15-3:
// "The low level of INTn generates an interrupt request"
DDRE &= ~(1<<PE5);
EICRB &= ~(1<<ISC50);
EICRB &= ~(1<<ISC51);
EIMSK |= (1<<INT5);

When I enable INT5, the Timer0 calls the ISR(TIMER0_COMPA_vect) only when PE5 is high.

If PE5 is low, Timer0 stops and when PE5 goes high again, Timer0 continues.

Why do these modules are correlating like this? They need to be independent, no?


texts: Do all the VDDIO pins need power in on a chip?

texts:
Question: I have a chip, AMTEL AT32UC3A4256S, with multiple VDDIO pins on. Do they all need a 3.3V power input or just one?

The power schematic from AMTEL shows a single decoupled VDDIO pin in their schematic -
BUT the pin out has many VDDIO pins.

Background: I am involved in a project as a systems engineer and another team is developing a custom PCB for an AMTEL AT32UC3A4256S. I decided that this would be a good chance to try and learn more about electronics and am doing some homework on the chip. It's a pretty complex chip to start out learning from but everything I find will be relevant to the project.


texts: Hi i bought a PN532 breakout board, I did install my cable FTDI, i did install NFC, nfc-list recognized my PN532, i did start the nfc-poll, its in listening mode, i've got my mifare card tag that came together and I did try to read, but it didn't read. So where could be the problem? I did solder the pin-heads to the FTDI cable, I connected it to my USB (linux ubuntu 10.04), i downloaded the last stable libnfc, compiled with the options ./configure --with-drivers=pn532_uart --enable-serial-autoprobe, as i wrote, the nfc-list recognized but now i cannot read a card with nfc-pool (but nfc-pool recognized as well my reader, it is in listening).Anything else to debug?


texts: mplab error: Executable code and data must be defined in an appropriate section

texts:
I'm  beginner to Mplab and microController programing.i'm following a pic book .basically my program is a led turn on and off program .I'm using mplabx-v2.10 .this is not my complete code.however the error comes from line

BSF STATUS, 5

my code

STATUS EQU 03H
TRISA EQU 85H
PORTA EQU 05H

    BSF STATUS, 5

    END

the error is

Error[152]   C:\USERS\MADHAWAX\MPLABXPROJECTS\P-STAR1.X\NEWASMTEMPLATE1.ASM 6 : Executable code and data must be defined in an appropriate section

a snapshot of error


texts: Form differential equation pair from discrete time system block diagram

texts:
I have a discrete time system block diagram.
And my question is what is the output y(k)

I managed to get what is V(k)
$$V(k)=\frac{1}{2}*V(k-1)  +U(k)        $$
But now i can't form y(k) because these adders mess me up.
I tried to do it and i got $$y(k)=-\frac{1}{2}*V(k)  +V(k-1)        $$


texts: Can an LED achieve full brightness in 40 µs?

texts:
How fast can an LED achieve it's full brightness at it's rated voltage and current?

I need to do multiplexing of LEDs to make a matrix display and I've calculated that each LED can only stay on for 40µs. I don't know if that is enough time for the LED light to be seen however.


texts: Is it possible to create an IIR filter in an FPGA that's clocked at the sample frequency?

texts:
This question is about implementing a IIR filter in a FPGA with DSP slices, with very specific criteria.

Lets say you're making a filter with no forward taps and only 1 reverse tap, with this equation:

$$y[n] = y[n-1] \cdot b1 + x[n]$$

(see image)

Take the DSP48A1 slice from Xilinx as an example - most hard IP DSP slices are similar.

Lets say you have analog data incoming at 1 sample per clock. I would like to design an IIR filter that runs synchronously at the sample clock.

The problem is that in order to run the DSP slice at the maximum rate, you can't multiply AND add on the same cycle. You have to have a pipeline register between these components.

So, if you have 1 new sample every clock, you will need to produce 1 output per clock. However, you need the previous output 2 clocks before you can produce a new one in this design.

The obvious solution is to either process the data at double clock rate, or to disable the pipeline register so that you can multiply and add in the same cycle.

Unfortunately, if say you're sampling at the max clock rate of the fully pipelined DSP slice, neither of those solutions are possible. Is  there any other way to build this?

(Bonus points if you can design a IIR filter that operates at half of the sample rate, using any number of DSP slices)

The goal would be to run a compensation filter for a 1 GSPS ADC in a Xilinx Artix FPGA. Their DSP slices can run just over 500 MHz when fully pipelined. If there is a solution for 1 sample per clock, I would like to try and scale the solution for 2 samples per clock. This is all very easy with an FIR filter.


texts: Verifying Impedance of Capacitors, Inductors, Resistors

texts: I would like some tips on how to build a circuit that will let me verify the impedances of these basic components. I had tried just measuring the output voltage from the component, but that didn't seem to work. I have an Analog Discover 2, it's a small oscilloscope/function generator. It can only measure voltage. Also the function generator can go up to 10 MHz, at that frequency will I see in inductive of capacitive effects in a typical carbon core resistor?


texts: Microchip PIC18F CAN message reception problem

texts:
I am attempting CAN communication between two nodes and can not get the receiver to transfer a message from the MAB to a readable buffer.  The nodes are identical, physically and in configuration.  I am transmitting at 40kbps.  The receiver will send the acknowledge bit and I have confirmed that a valid message is being sent with a Saleae Logic connected to PC. Also, when connected to MPLABX with PICKit3 for debugging I am able to see that neither the TXERRCNT of the trasmiter nor the RXERRCNT of the receiver are logging any errors.  I have RXB0CON, RXM1 set which means the receiver should be transferring all messages, including those with errors, to RXB0 ignoring filters and masks.  I have tried the same setting with RXB1CON and nothing is being transferred to that register either.  I am strictly using Assembly, no canned routines.  I have also tried starting with a "bootup message" of SID set to all 0's and 0 DLC prior to sending a normal message but it does not make any difference.

Hardware is PIC18F25K80 connected to MCP2561.  Bus is properly terminated with 120 ohm resistors at each node and meter shows 60 ohms on bus when nodes are not powered so no shorted or open terminators.

Thanks in advance to anyone that may offer suggestions.


texts: Thermal resistance of anodized aluminium interface

texts: I'm considering extruded aluminium enclosures for a power amplifier, but need to do something with as much as 255W of heat. Currently I have a sufficient heat sink, attached directly to the transistors. If I attached the transistors to the anodized aluminium enclosure, and the heat sink to that (all with appropriate thermal grease, of course), what thermal performance can I expect? Can I estimate the additional thermal resistance due to the interface between the parts?


texts: Why can we bias mosfet with current source

texts:
I know that we can get desired DC current by supplying certain VGS asccording to the equation I=(1/2)*K(VGS-VT)^2.
But the scheme shown in the picture does it in a reversed way. It is establishing a VGS according to I.
Can this really happen? Doesn't Mosfet only transfer signal in one way (from gate to drain current)? How can it be the other around?


texts: Relation ship between Track width, Impedance, Dielectric and copper thickness

texts:
I like to know the relationship between different factors like track width, impedance, dielectric and copper thickness.

After quite a reading I got to know that as the track width of a cline is decreased, there is a decrease in the impedance, Trace width is indirectly proportional to impedance. For every 0.025mm change of track width, there is a 5-6 ohm change in impedance.

I want to derive the relationship like above between the other.


texts: Why can't an object have "absolute" zero potential

texts:
I've read a lot of questions about this on this site and others, and every answer seems to believe that there can't be an object with zero potential/voltage, unless you take it at infinity, which seems pointless, or arbitrarily define it as zero.

From my understanding, potential difference is proportional to q/r, so I can see why, if you just look at r, it's difficult to have zero potential.

But what if we look at q? Surely, if an object has a net charge of zero, then you must be able to say it has zero potential.


texts: Power converters Modelling - NPC versus no NPC

texts:
I am trying to simulate a three-phase inverter in Matlab/Simulink.

So far I figured out that in the Simulink library there are two types of inverters. The first one is illustrated in the figure below and its called "Universal Bridge"

The second type of converter is called "Three-level neutral point clamped (NPC) power converter" and you can see it below.

The main difference between the two topologies is that in the NPC converter there is one more output at the DC side. I have read that we can use this output to create one more voltage level. Also, the design methodology and the control techniques are pretty much the same.

So, I would like to ask if there are any more differences and why should I select the one topology over the other.


texts: Creating Cadence Virtuoso Layout in Rectangular MOS Power device

texts:
I am trying to create a Power MOSFET with W/L = 9.2mm/1.6u
This value is as per the design specification obtained by simulation using schematic value.
I am new to Cadence Virtuoso and would appreciate any suggestions or pointers to making rectangular Power MOSFET of W/L mentioned above.


texts: VHDL - assigning array signal in a loop generates side effects

texts:
I do not understand why the following vhdl code does not simulate as I think it should.

test_pipe_1(0) is assigned at process pr1, but the simulation (both Aldec and GHDL) shows test_pipe_1(0) being 'U' all the time.

OTH, test_pipe_2(0) works differently in Aldec vs GHDL.
In Aldec, the signal is assigned as expected ('Z' @ 0 sec, '0' @ 500 ns, '1' @ 1 us, etc).

In GHDL, the wierd behaviour is seen ('Z' @ 0 sec, 'U' @ 500 ns). There is no 'U' driver for test_pipe_2(0) signal.

My feeling is that this is language definition feature, but cannot understand what, and why.

Any ideas?

library ieee;
use ieee.std_logic_1164.all;

entity vhdl_loop_assignment is
end;

architecture testing of vhdl_loop_assignment is
    signal test_d0: std_logic;
    signal test_pipe_1: std_logic_vector(9 downto 0);
    signal test_pipe_2: std_logic_vector(9 downto 0) := (others => 'Z');
    signal clk: std_logic;
begin
    test_1: process(clk)
    begin
        if rising_edge(clk) then
            l: for n in 0 to 8 loop
                test_pipe_1(n+1) <= test_pipe_1(n);
            end loop;
            -- test_pipe_1(0) <= 'Z'; -- If this is uncommented, starts working as expected.
        end if;
    end process;

    test_2: process(clk'delayed(300 ns))
    begin
        if rising_edge(clk'delayed(300 ns)) then
            l: for n in 0 to 8 loop
                test_pipe_2(n+1) <= test_pipe_2(n);
            end loop;
        end if;
    end process;

    pr1: process(clk)
    begin
        if rising_edge(clk) then
            if test_d0 /= '0' then
                test_d0 <= '0';
                test_pipe_1(0) <= '0';
                test_pipe_2(0) <= '0';
            else
                test_d0 <= '1';
                test_pipe_1(0) <= '1';
                test_pipe_2(0) <= '1';
            end if;
        end if;
    end process;

    pr2: process
    begin
        clk <= '0';
        wait for 500 ns;
        clk <= '1';
        wait for 500 ns;
    end process;
end;


texts: Design and simulation of snubber and hysteresis current control

texts:
I want to do an hysteresis current control with this circuit:

that have three operation modes:

in order to make the output current to follow a triangle wave as reference.

I made a simple C code to use it with the S-function block in Matlab/Simulink (which basically says: if output current is greater than triangular reference turn Sa and Sb OFF, otherwise (less than reference) turn Sa and Sb ON.
However, I'm obtaining this output current:

As you can see, current is ugly and made me ask this question because I'm having trouble about selecting the correct values for capacitors and inductors.

Any suggestion or comment would be truly appreciated.
Thanks!


texts: Buck converter freewheeling diode short circuit damaging the FET

texts:
I have a classic buck converter configuration (http://en.wikipedia.org/wiki/Buck_converter) with IXFK120N65X2 power mosfet used as switch and VS-8ETL06PbF used as freewheeling diode. The input voltage is 300VDC, PWM frequency 50kHz, power mosfet driven by ADUM3123 isolated gate driver, DC/DC supply for the high side is MEJ1S0512SC. Max. continuous current is limited to 10A.
It is a prototype and the only I have.

a) When the mosfet is fully switched on (PWM duty = 100%) the converter operates fine for hours - here it seems to be fine.

b) When the buck converter operates in discontinuous mode (i.e. bigger PWM duty and small load OR smaller PWM duty and bigger load) the converter operates fine for hours and all measured waveforms correspond to our SPICE simulations - here it seems to be fine as well.

c) But when the buck converter operates in continuous mode the diode burns within just seconds and in most cases the power mosfet burns as well, causing short circuit of the buck converter and overload protection of our input voltage source to become active. When inspecting the damaged parts after this event, the diode is then fully conductive with zero resistance in both directions and the mosfet sometimes as well (zero resistance between drain and source).

I've experienced 5 those "crashes" before I could isolate the event to occur only in the continuous mode. I think the cause here is a fairly long reverse recovery time of this diode, causing repetitive short circuits during each reverse recovery cycle which finally destroy the diode after few seconds. But I am not sure. Maybe also this diode is not suitable for this purpose. Because the operating time ad c) was always very short I was not able to measure anything. Now I don't want to destroy more diodes and FETs. I already ordered a SiC diode alternative (which has a slightly higher forward voltage however) and will try it again then.

Question: Did you experience such behavior and/or are my assumptions correct?

Thank you

EDIT: Load of the converter is only resistive (a heater).


texts: Are source and drain terminals of Access Transistors in 6T SRAM interchangeable?

texts: My textbook understanding is that the source terminals (S) of the access transistors in a 6T SRAM cell are to be connected to the bit lines (BL/BLB) while the drain terminals (D) to the storage nodes (Q/QB). Now while simulating an SRAM cell in HSPICE, exchanging the Source and Drain terminal connections doesn't seem to change the output. In fact, I thought about this only after I saw some SRAM netlists available on the internet where they had connected S to Q/QB and D to BL/BLB! I get that MOSFET is a symmetrical structure and S/D can be interchanged in a standalone device, but is it true while designing a circuit?


texts: Connecting 0.25 watt 8 ohm speaker to 3.5mm mini jack output from laptop/portable player

texts:
Can I safely connect a 0.25W 8 Ohm speaker to 3.5mm mini jack output from laptop/portable player?
What is the general calculation (thought) when doing similar stuff, like connecting a 2 watt 4 ohm speaker to a XY device for example.


texts:
I'm looking for some bright LEDs (in the range of 30-50 lumens, which I think means 2-3 W) for use in a piece of scientific equipment. Can anyone recommend an LED manufacturer that has not just powerful LEDs, but also particularly complete datasheets? I'm especially interested in a lumens/current curve.

If it helps, I'm mostly interested in LEDs with wavelengths below 560 nm, i.e. green, blue, violet, and UV. If I could get all the LEDs from one manufacturer, that would be good. I'd prefer surface-mount LEDs, but it's not a strict requirement.


texts: A battery is not connected to anything. Is there a voltage between its plus and minus poles?

texts:
Here's one mental picture of a battery:
The electro-chemical reactions inside the battery happen only when there's a closed circuit.
When you place a voltmeter across the poles, then you create a closed circuit (with very low current) - the electro-chemical reactions start, and you now have a voltage between the poles. The placement of the voltmeter changes the thing you are trying to measure. Without the voltmeter, there's no voltage between the poles, because there's no closed circuit.
But the above seems completely inconsistent with how people speak of open-circuit voltage, as existing independent of actually measuring it.
My reasoning must be wrong somewhere. But where?
(I know this is a very simple question, but I'm genuinely confused by it.)
Here's an example of the typical use of open-circuit voltage (see 24:00), from an MIT lecture.
Edit: replaced voltage-drop with voltage.


texts: How to find out how many sensor you can add to a I2C or SPI protocol?

texts:
I am having problems to find out exactly how to connect sensors to make a project.

The main issue is that I cannot find a device that can drive enough analog sensor, so I need to use either SPI or I2C.

Now, I have noticed that some sensor basically has the limitation about how many of them you can connect on the same protocol, since they use a fixed address (forgive me if this is incorrect as explanation, but that's what I grasped, looking at the sparse documentation online).

Now, is there an easy way to know which sensor are able to "change" this memory address, so you can use many of them via SPI or I2C? Thanks

EDIT: As sensor I am considering these; for the sampling rate I am not sure how to calculate it; I am a SW engineer, not a hardware engineer. The application is real time collection of data related to position and rotation of an object with the equipment on. The speed of the object measured is not faster than any movement that a human can generate.

ADXL335 and 345 (the latter has SPI and I2C, the former only analog)
http://www.analog.com/static/imported-files/data_sheets/ADXL345.pdf
http://www.analog.com/static/imported-files/data_sheets/ADXL335.pdf

PArallax MMA7455 Accelerometer
http://www.parallax.com/sites/default/files/downloads/28526-MMA7455-3-Axis-Accelerometer-Documentation-v1.1.pdf

Bosch BMA180 Accelerometer
http://zh.bosch-sensortec.com/content/language4/downloads/BST-BMA180-FL000-03.pdf

L3G4200D Gyroscope
http://www.pololu.com/file/0J491/L3G4200D.pdf

Invesense MPU6050 Gyroscope
http://invensense.com/mems/gyro/documents/PS-MPU-6000A-00v3.4.pdf


texts: Good day to all. I'm doing a self study about the circuit shown above. I kind of don't understand which structure biases the differential pair(red). The explanation I read from the book that it is the structure in green that biases it, but the lecture I'm following says it it's the structure in blue that biases the diff pair. Which one is true? Please bear with me my command of english language is not that good. Thank you.


texts: Need smaller pullups on i2c lines, but design is low power, what is best?

texts: The pullups on my i2c lines are 4.7k. People are afraid of draining the battery by fixing this waveform with smaller pullups, like 2.2k. It doesn't seem much power is wasted considering the short duration of the bus being low (2-4 byte transfers) and the 400k bus speed. I am concerned about reliability with the waveform this distorted. What is the effect of the curving leading edge? It would seem to delay sampling of sda on the rising edge of scl.


texts: Generating sawtooth signal out of square/triangular signal

texts:
I want to create a sawtooth signal generator. I know, how to build op-amp comparator to create a square wave. I also know, how i can get triangular signal by integrating comparator output with op-amp integrator.

What i don't know nor find is how do i get sawtooth signal out of square/triangular wave. Could someone explain this a bit and es

Thank you.


texts:
I need to send data from one PIC to another PIC by using RS485. As a protocol I use UART. However, I cannot be sure about RS485 transceiver and its circuit. I will be able to supply 5 V and according to this I have found one of the most used option is LT1785 chip. I have these following questions related to this chip:

Can this chip (LT1785) also convert RS485 signal to UART or it can only convert UART to RS485?
There is no hardware diagram in the datasheet so I have take a look at the internet and some people use 120 ohm resistor between rx and tx pins some people do not. Do I need to put that resistor?
In some schematics some people shorted the RE (receiver output enable) and DE (driver output enable) pins. What is the purpose for it? Do I also need to short them?
There is a circuit image for UART to RS485 convension. Do I need to change the circuit if I need to use LT1785 for RS485 to UART convension or can I use the circuit in image without changing it?
Is there a need for a resistor or a capacitor between Vdd pin to Vdd and a Ground pin to Ground.

PS: I am new to these topics so please excuse if the questions are too simple.


texts: Equivalent resistance in BJT small-signal : Rpi in parallel with Beta*Ib

texts:
I'm currently reading Vorperian's book on Fast Analytical Circuits techniques. On page 129 he states :

I'm not sure I understand correctly the statement I highlighted in yellow.
Is it some kind of use of the Norton<->Thevenin conversion?
If anybody could make me understand what he means mathematically and/or schematically.
I know the resistance reflection rule in a BJT, but I'm not sure I understand it in terms of "parallel combination between \$i_b \beta\$ and \$r_{\pi}\$".
It doesn't seem the resulting equivalent circuit has \$r_e\$ in series with \$R_E\$ given eq. 4.59.
Any help will be appreciated. Thanks!


texts: negative voltage of a differential amplifier

texts: Can somebody explain what is this negative voltage -VEE in the circuit? I thought two parallel circuits are connected to the power supply vcc, but how this VEE came? Can somebody explain me this using simplified battery connection?


texts: Losses in NE555 oscillator and Sallen-Key filter

texts:
I use a Sallen-Key bandpass filter in a project at university to isolate the 1kHz sinusoidal part of a square signal produced by a NE555 oscillator.
Here is my circuit:

When I simulate it on PSpice, I get this:

But when I check the voltage with an oscilloscope on the real circuit, this is what I get (5V per square):

How can I explain the big differences in amplitude of the signal between simulation and reality ? Is that only losses in the NE555 and non-ideality of the opamp in the filter ?


texts: Analog Potentiometer Output to USB Serial

texts:
I‘m working on a project which has several switches and potentiometers that will be used to control parameters in software via (e.g.) MIDI and would like to know how to get the pots set up without using an Arduino.

The path I started down was to use a (following the MIDI example) 7-bit Flash ADC IC to convert to a digital signal, but am unsure how I could convert this to serial to be sent over USB. Is there some microcontroller which could be programmed to send out MIDI information based on the values received from the ADC?

I‘d like to cut out the Arduino to save space, be able to make a more customised device, and would also like to learn more about how this works. If there‘s a different path (such as using a different type of ADC other than Flash) I should look towards, please point me in the right direction.


texts: Can I use a car battery for running DC motors?

texts:
I'm planning to run 2 DC motors in parallel for a project.

Each of my motors has rated power of 250 W and a rated current draw of 14 amps at 24V (so 28 amps from 2 motors).

After researching around, it seems that a used car battery is a good solution (versatile and cheap). I would need to use 2 in series. However, are they okay to use for such high continuous currents for long periods of time (50-60 minutes in my case)?

Any help would be appreciated. Thank you.


texts: Which kind of motor is best recommended for a curtain opener?

texts:
The general idea is to build a curtain opener, using some kind of motor connected to my arduino. Which will cause the pulling-functionality...

So the following options are :

1. DC motor

I feel like this is the least preferable one, since of it's low torque

2. Servo motor

If I "hack" the servo & cut off the potentiometer. I should be able to make it go in to two directions, in 360 degrees and still keep the power of the torque, I think?

3. Stepper motor

This is probably the most recommend one for the functionality I'm trying to achieve but, stepper motors are quite big, maybe a bit too big and quite pricy from what I've seen.

So, to sum it up. I could use a DC-motor, but I don't think it will be able to pull the curtain rope with enough power. I could also use a stepper motor, but it looks too big and heavy for the environment I'm using it in. So, would a "hacked" servo, be an OK solution?

Maybe I'm not seeing other possible problems here that might play a role...

Thanks!


texts:
I'm using this Regulator namely TLV1117-50IDCYR for a project that I'm working on. Aparently everything is working fine with this chip but sometimes I feel it's heating too much and I'm not putting all the load there.

I'm making a regulation from 12V to 5V for a 300mA output current and it will have a 2,1W of power dissipation.
I've checked the datasheet on the page 5 and it says the Junction-to-ambient thermal resistance is 104.3 ºC/w and the Junction-to-case (top) thermal resistance is 53.7 ºC/W.

My doubt is: which parameter should I consider for my case? If it is the second one I am not seeing any problem.

Can you help me on this?
Many thank's!


texts: I am a plant eco-physiologist working with leaf venation networks. I want to calculate the resistance of a vein segment in units of Ohms, using the formula Resistance = (resistivity * segment length)/ cross sectional area. I have the vein length in m, the vein cross-sectional area in cm2 and I calculated the vein resistivity using the Sack and Frole 2006 formula (DOI: 10.1890/05-0710) which gives the resistivity in units of MPa mmol-1 s m. How could I convert this resistivity in MPa mmol-1 s m to units of Ohm m (Ohms per meter)?


texts: Can I connect multiple electret microphones for better gain?

texts:
Is it possible to connect multiple electret microphones in order to increase sensitivity (gain) of the microphone(s)? If yes, how do I connect them?

Update:
Obviously one solution is to increase the number of amplifiers, but I am curious if multiple microphones can be serial connected - so this is more like a theoretical question (unless it is possible to do it - then it becomes a practical question)   :)


texts: Why is the PNP transistor used in this circuit?

texts:
Why are there PNP transistors here?

from: https://www.youtube.com/watch?v=5_uYE4EWSKY&t=884s&ab_channel=SparkFunElectronics
This shows a charge pump circuit that will be controlled via the digital pins of a microcontroller.
Why does it use 3 transistors each? Wouldn't 2 NPN's each give the same output?
like this:

More specifically, can I replace the PNP transistor with an NPN transistor(as shown in the above schematic)?
(I am an amateur in electronics, so please forgive me if this is a dumb question -_-; )


texts: Running a 220v dust collector with 24v switches

texts: I have a 5hp 220V 30A dust collector that I want to turn on and off with 24v switches attached to my blast gates. Can I simply use a 220v to 24v transformer?


texts: Asynchronous Bitbang mode vs Synchronous Bitbang mode

texts:
I am still newbie in the field of electronic, and I have to write program to flash LED light as well as receive light data via photodiode. I am currently using FT2232H mini module. I have trouble understanding what an Asynchronous Bitbang mode is and how is it different from Synchronous Bitbang mode. I tried to send repeating 101010 on send an Asynchronous Bitbang mode, but the receiver sometime read as 11011011 and sometime as 00100100 (notice double 1 or double 0). On the other hand, I tried Synchronous mode, but all I got is random bits. What would be the right approach to this situation? What mode should I use for receiving a predefined data rate (e.g. sender sent at constant 30kbit/s)

reference:http://www.ftdichip.com/Support/Documents/AppNotes/AN_232R-01_Bit_Bang_Mode_Available_For_FT232R_and_Ft245R.pdf


texts: Placement/routing of decoupling cap straddling oscillator guard ring on dsPIC

texts:
Changes in my design are forcing me to replace my 44-pin dsPIC33FFJ16MC304 with a 64-pin (same package size, finer pin pitch) dsPIC33FJ64MC506. In the datasheets for both chips, Microchip recommends a guard ring connected to ground around the oscillator circuit and a trace length of no more than 500 mils on the OSC lines.

The board is a 4-layer stackup (signal, ground, power, signal). I'm concerned about EMI because the board will be located near a compressor and two fans.

Pins 28-31 of the 44-pin package are +3.3V, DGND, OSC1, and OSC2. I currently have the oscillator circuit laid out like so:

C10 is a 0.1 uF decoupling cap, C20 and C21 are the 18pF load caps for the 8MHz crystal Y1. I put the via to the ground plane at the end of the guard trace because Altium was treating it as an incomplete trace.

The decoupling capacitor placement is not optimal per Decoupling caps, PCB layout, but ignore that for a moment. On the new 64-pin chip, the pin arrangement changes to +3.3V, OSC1, OSC2, DGND.

It seems to me that the obvious location for the decoupling cap in this case is underneath the chip, but I'm restricted to placing components on the top layer only. That being said, I'm guessing I have to have C10 straddling C20 and C21 so that the power/ground lines go around the oscillator circuit. I don't like how long that will make the traces to the decoupling cap. For optimal EMC,

I intend to redraw the guard ring as a polygon pour to eliminate the extra terminating via. Where should I connect the guard ring to the ground plane, the single via in Olin's answer to Decoupling caps, PCB layout?
The guard ring connects to the ground pin on the PIC that the decoupling capacitor would normally be connected to. Do I connect the ground pin of the decoupling cap to the guard ring?
What if I avoid the longer decoupling cap trace length issue by using two caps (one for the power pin, one for the ground pin) like in How to connect decoupling capacitor when VCC/GND pins aren't close? Would this work better? My concern with this approach is how to connect the extra capacitor pins to the reference planes.
Do I increase the length of the OSC lines to better fan out the surrounding traces? It's currently about 320 mils from the MCU pins to the load capacitors, so I do have a little headroom there if needed.

EDIT: Here's the new chip pinout, no guard ring yet. Current OSC trace length is 416 mils. C29 in the picture is supposed to be decoupling the 3.3V and DGND pins on either side of the OSC pins. The decoupling cap is now a 0603 instead of a 0805 as well.