code:
/*	$OpenBSD: sab82532reg.h,v 1.2 2002/04/08 17:49:42 jason Exp $	*/

/*-
 * Copyright (c) 2001 Jason L. Wright (jason@thought.net)
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Jason L. Wright
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * Effort sponsored in part by the Defense Advanced Research Projects
 * Agency (DARPA) and Air Force Research Laboratory, Air Force
 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
 *
 * $FreeBSD: release/9.0.0/sys/dev/ic/sab82532.h 139749 2005-01-06 01:43:34Z imp $
 */

#ifndef _DEV_IC_SAB82532_H_
#define	_DEV_IC_SAB82532_H_

/*
 * Register definitions for SAB82532 based on "Enhanced Serial Communication
 * Controller ESCC2 Version 3.2 User's Manual 07.96" from:
 * http://www.infineon.com
 */

#define	SAB_NCHAN	2	/* number of channels */
#define	SAB_CHANLEN	0x40	/* length of channel register set */

#define	SAB_CHAN_A	0x00	/* channel A register offset */
#define	SAB_CHAN_B	0x40	/* channel B register offset */

#define	SAB_RFIFO	0x00	/* r: rx fifo */
#define	SAB_XFIFO	0x00	/* w: tx fifo */
#define	SAB_STAR	0x20	/* r: status register */
#define	SAB_CMDR	0x20	/* w: command register */
#define	SAB_MODE	0x22	/* rw: mode register */
#define	SAB_TIMR	0x23	/* rw: timer register */
#define	SAB_XON		0x24	/* rw: xon character */
#define	SAB_XOFF	0x25	/* rw: xoff character */
#define	SAB_TCR		0x26	/* rw: termination character */
#define	SAB_DAFO	0x27	/* rw: data format */
#define	SAB_RFC		0x28	/* rw: rfifo control register */
#define	SAB_RBCL	0x2a	/* r: rx byte count low */
#define	SAB_TBCL	0x2a	/* w: tx byte count low */
#define	SAB_RBCH	0x2b	/* r: rx byte count high */
#define	SAB_XBCH	0x2b	/* w: tx byte count high */
#define	SAB_CCR0	0x2c	/* rw: channel configuration register 0 */
#define	SAB_CCR1	0x2d	/* rw: channel configuration register 1 */
#define	SAB_CCR2	0x2e	/* rw: channel configuration register 2 */
#define	SAB_CCR3	0x2f	/* rw: channel configuration register 3 */
#define	SAB_TSAX	0x30	/* w: time-slot assignment register tx */
#define	SAB_TSAR	0x31	/* w: time-slot assignment register rx */
#define	SAB_XCCR	0x32	/* w: tx channel capacity register */
#define	SAB_RCCR	0x33	/* w: receive channel capacity register */
#define	SAB_VSTR	0x34	/* r: version status */
#define	SAB_BGR		0x34	/* w: baud rate generator */
#define	SAB_TIC		0x35	/* w: transmit immediate character */
#define	SAB_MXN		0x36	/* w: mask xon character */
#define	SAB_MXF		0x37	/* w: mask xoff character */
#define	SAB_GIS		0x38	/* r: global interrupt status */
#define	SAB_IVA		0x38	/* w: interrupt vector address */
#define	SAB_IPC		0x39	/* rw: interrupt port configuration */
#define	SAB_ISR0	0x3a	/* r: interrupt status 0 */
#define	SAB_IMR0	0x3a	/* w: interrupt mask 0 */
#define	SAB_ISR1	0x3b	/* r: interrupt status 1 */
#define	SAB_IMR1	0x3b	/* w: interrupt mask 1 */
#define	SAB_PVR		0x3c	/* rw: port value register */
#define	SAB_PIS		0x3d	/* r: port interrupt status */
#define	SAB_PIM		0x3d	/* w: port interrupt mask */
#define	SAB_PCR		0x3e	/* w: port configuration register */
#define	SAB_CCR4	0x3f	/* rw: channel configuration register 4 */

/* SAB_STAR: status register */
#define	SAB_STAR_XDOV	0x80	/* transmit data overflow */
#define	SAB_STAR_XFW	0x40	/* transmit fifo write enable */
#define	SAB_STAR_RFNE	0x20	/* rfifo not empty */
#define	SAB_STAR_FCS	0x10	/* flow control status */
#define	SAB_STAR_TEC	0x08	/* tx immediate char is executing */
#define	SAB_STAR_CEC	0x04	/* command is executing */
#define	SAB_STAR_CTS	0x02	/* cts status: 0:inactive/high,1:active/low */

/* SAB_CMDR: command register */
#define	SAB_CMDR_RMC	0x80	/* receive message complete */
#define	SAB_CMDR_RRES	0x40	/* receiver reset */
#define	SAB_CMDR_RFRD	0x20	/* receive fifo read enable */
#define	SAB_CMDR_STI	0x10	/* start timer */
#define	SAB_CMDR_XF	0x08	/* transmit frame */
#define	SAB_CMDR_XRES	0x01	/* transmit reset */

/* SAB_MODE: mode register */
#define	SAB_MODE_FRTS	0x40	/* flow control using rts */
#define	SAB_MODE_FCTS	0x20	/* flow control using cts */
#define	SAB_MODE_FLON	0x10	/* flow control on */
#define	SAB_MODE_RAC	0x08	/* receiver active */
#define	SAB_MODE_RTS	0x04	/* request to send */
#define	SAB_MODE_TRS	0x02	/* timer resolution */
#define	SAB_MODE_TLP	0x01	/* test loop */

/* SAB_TIMR: timer register */
#define	SAB_TIMR_CNT	0xe0	/* count mask */
#define	SAB_TIMR_VAL	0x1f	/* value mask */

/* SAB_DAFO: data format */
#define	SAB_DAFO_XBRK	0x40	/* transmit break */
#define	SAB_DAFO_STOP	0x20	/* stop bit: 0:1 bit, 1:2 bits */
#define	SAB_DAFO_PAR1	0x10	/* parity 1, see below */
#define	SAB_DAFO_PAR0	0x08	/* parity 0, see below */
#define	SAB_DAFO_PARE	0x04	/* parity enable */
#define	SAB_DAFO_CHL1	0x02	/* character length 1, see below */
#define	SAB_DAFO_CHL0	0x01	/* character length 0, see below */

#define	SAB_DAFO_CHL_CSIZE	(SAB_DAFO_CHL1|SAB_DAFO_CHL0)
#define	SAB_DAFO_CHL_CS5	(SAB_DAFO_CHL1|SAB_DAFO_CHL0)
#define	SAB_DAFO_CHL_CS6	(SAB_DAFO_CHL1)
#define	SAB_DAFO_CHL_CS7	(SAB_DAFO_CHL0)
#define	SAB_DAFO_CHL_CS8	(0)

#define	SAB_DAFO_PARMASK	(SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE)
#define	SAB_DAFO_PAR_MARK	(SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE)
#define	SAB_DAFO_PAR_EVEN	(SAB_DAFO_PAR1|SAB_DAFO_PARE)
#define	SAB_DAFO_PAR_ODD	(SAB_DAFO_PAR0|SAB_DAFO_PARE)
#define	SAB_DAFO_PAR_SPACE	(SAB_DAFO_PARE)
#define	SAB_DAFO_PAR_NONE	(0)

/* SAB_RFC: rfifo control register */
#define	SAB_RFC_DPS	0x40	/* disable parity storage */
#define	SAB_RFC_DXS	0x20	/* disable storage of xon/xoff characters */
#define	SAB_RFC_RFDF	0x10	/* rfifo data format: 0 data,1 data+stat */
#define	SAB_RFC_RFTH1	0x08	/* rfifo threshold level 1, see below */
#define	SAB_RFC_RFTH0	0x04	/* rfifo threshold level 0, see below */
#define	SAB_RFC_TCDE	0x01	/* termination character detection enable */

#define	SAB_RFC_RFTH_MASK	(SAB_RFC_RFTH1|SAB_RFC_RFTH0)
#define	SAB_RFC_RFTH_32CHAR	(SAB_RFC_RFTH1|SAB_RFC_RFTH0)
#define	SAB_RFC_RFTH_16CHAR	(SAB_RFC_RFTH1)
#define	SAB_RFC_RFTH_4CHAR	(SAB_RFC_RFTH0)
#define	SAB_RFC_RFTH_1CHAR	(0)

/* SAB_RBCH: received byte count high */
#define	SAB_RBCH_DMA	0x80	/* read back of XBCH DMA bit */
#define	SAB_RBCH_CAS	0x20	/* read back of XBCH CAS bit */
#define	SAB_RBCH_CNT	0x0f	/* ms 4 bits of rx byte count (not used) */

/* SAB_XBCH: transmit byte count high */
#define	SAB_XBCH_DMA	0x80	/* dma mode: 1:dma, 0:interrupt */
#define	SAB_XBCH_CAS	0x20	/* carrier detect auto-start */
#define	SAB_XBCH_XC	0x10	/* transmit continuously */
#define	SAB_XBCH_CNT	0x0f	/* ms 4 bits of tx byte count */

/* SAB_CCR0: channel configuration register 0 */
#define	SAB_CCR0_PU	0x80	/* 0:power-down, 1:power-up */
#define	SAB_CCR0_MCE	0x40	/* master clock enable */
#define	SAB_CCR0_SC2	0x10	/* serial port config 2, see below */
#define	SAB_CCR0_SC1	0x08	/* serial port config 1, see below */
#define	SAB_CCR0_SC0	0x04	/* serial port config 0, see below */
#define	SAB_CCR0_SM1	0x02	/* serial mode 1, see below */
#define	SAB_CCR0_SM0	0x01	/* serial mode 0, see below */

#define	SAB_CCR0_SC_MASK	(SAB_CCR0_SC2|SAB_CCR0_SC1|SAB_CCR0_SC0)
#define	SAB_CCR0_SC_NRZ		(0)
#define	SAB_CCR0_SC_NRZI	(SAB_CCR0_SC1)
#define	SAB_CCR0_SC_FM0		(SAB_CCR0_SC2)
#define	SAB_CCR0_SC_FM1		(SAB_CCR0_SC2|SAB_CCR0_SC0)
#define	SAB_CCR0_SC_MANCHESTER	(SAB_CCR0_SC2|SAB_CCR0_SC1)

#define	SAB_CCR0_SM_MASK	(SAB_CCR0_SM1|SAB_CCR0_SM0)
#define	SAB_CCR0_SM_DLC		(0)
#define	SAB_CCR0_SM_DLCLOOP	(SAB_CCR0_SM0)
#define	SAB_CCR0_SM_BISYNC	(SAB_CCR0_SM1)
#define	SAB_CCR0_SM_ASYNC	(SAB_CCR0_SM1|SAB_CCR0_SM0)

/* SAB_CCR1: channel configuration register 1 */
#define	SAB_CCR1_ODS	0x10	/* Output driver select:1:pushpull,0:odrain */
#define	SAB_CCR1_BCR	0x08	/* bit clock rate: 1:async, 0:isochronous */
#define	SAB_CCR1_CM2	0x04	/* clock mode 2, see below */
#define	SAB_CCR1_CM1	0x02	/* clock mode 1, see below */
#define	SAB_CCR1_CM0	0x01	/* clock mode 0, see below */

#define	SAB_CCR1_CM_MASK	(SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0)
#define	SAB_CCR1_CM_7		(SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0)

/* SAB_CCR2: channel configuration register 2, depends on clock mode above */
/* clock mode 0a, 1, 4, 5 */
#define	SAB_CCR2_SOC1	0x80	/* special output 1, below */
#define	SAB_CCR2_SOC0	0x40	/* special output 0, below */
#define	SAB_CCR2_SOC_MASK	(SAB_CCR2_SOC1|SAB_CCR2_SOC0)
#define	SAB_CCR2_SOC_RTSHIGH	(SAB_CCR2_SOC1)
#define	SAB_CCR2_SOC_RTSNORM	(0)
#define	SAB_CCR2_SOC_RTSRX	(SAB_CCR2_SOC1|SAB_CCR2_SOC0)
/* clock mode 0b, 2, 3, 6, 7 */
#define	SAB_CCR2_BR9	0x80	/* baud rate bit 9 */
#define	SAB_CCR2_BR8	0x40	/* baud rate bit 8 */
#define	SAB_CCR2_BDF	0x20	/* baud rate division factor: 0:1: 1:BRG */
#define	SAB_CCR2_SSEL	0x10	/* clock source select */
/* clock mode 5 */
#define	SAB_CCR2_XCS0	0x20	/* tx clock shift, bit 0 */
#define	SAB_CCR2_RCS0	0x10	/* rx clock shift, bit 0 */
/* clock mode 0b, 2, 3, 4, 5, 6, 7 */
#define	SAB_CCR2_TOE	0x08	/* tx clock output enable */
/* clock mode 0a, 0b, 1, 2, 3, 4, 5, 6, 7 */
#define	SAB_CCR2_RWX	0x04	/* read/write exchange (dma mode only) */
#define	SAB_CCR2_DIV	0x01	/* data inversion (nrz) */

/* SAB_CCR3: channel configuration register 3 (v2 or greater) */
#define	SAB_CCR3_PSD	0x01	/* dpll phase shift disable (nrz/nrzi) */

/* SAB_TSAX: time-slot assignment register transmit (clock mode 5 only) */
#define	SAB_TSAX_TSNX	0xfc	/* time-slot number transmit */
#define	SAB_TSAX_XCS2	0x02	/* transmit clock shift bit 2 */
#define	SAB_TSAX_XCS1	0x01	/* transmit clock shift bit 1 */

/* SAB_TSAR: time-slot assignment register receive (clock mode 5 only) */
#define	SAB_TSAR_TSNR	0xfc	/* time-slot number receive */
#define	SAB_TSAR_RCS2	0x02	/* receive clock shift bit 2 */
#define	SAB_TSAR_RCS1	0x01	/* receive clock shift bit 1 */

/* SAB_VSTR: version status register */
#define	SAB_VSTR_CD	0x80	/* carrier detect status */
#define	SAB_VSTR_DPLA	0x40	/* dpll asynchronous */
#define	SAB_VSTR_VMASK	0x0f	/* chip version mask: */
#define	SAB_VSTR_V_1	0x00	/*   version 1 */
#define	SAB_VSTR_V_2	0x01	/*   version 2 */
#define	SAB_VSTR_V_32	0x02	/*   version 3.2 */

/* SAB_GIS: global interrupt status register */
#define	SAB_GIS_PI	0x80	/* universal port interrupt */
#define	SAB_GIS_ISA1	0x08	/* interrupt status a1 */
#define	SAB_GIS_ISA0	0x04	/* interrupt status a0 */
#define	SAB_GIS_ISB1	0x02	/* interrupt status b1 */
#define	SAB_GIS_ISB0	0x01	/* interrupt status b0 */

/* SAB_IVA: interrupt vector address */
#define	SAB_IVA_MASK	0xf8	/* interrupt vector address mask */

/* SAB_IPC: interrupt port configuration */
#define	SAB_IPC_VIS	0x80	/* masked interrupt bits visible */
#define	SAB_IPC_SLAMASK	0x18	/* slave address mask */
#define	SAB_IPC_CASM	0x04	/* cascading mode */
#define	SAB_IPC_ICMASK	0x03	/* port config mask: */
#define	SAB_IPC_ICOD	0x00	/*   open drain output */
#define	SAB_IPC_ICPL	0x01	/*   push/pull active low output */
#define	SAB_IPC_ICPH	0x03	/*   push/pull active high output */

/* SAB_ISR0: interrupt status 0 */
#define	SAB_ISR0_TCD	0x80	/* termination character detected */
#define	SAB_ISR0_TIME	0x40	/* time-out limit exceeded */
#define	SAB_ISR0_PERR	0x20	/* parity error */
#define	SAB_ISR0_FERR	0x10	/* framing error */
#define	SAB_ISR0_PLLA	0x08	/* dpll asynchronous */
#define	SAB_ISR0_CDSC	0x04	/* carrier detect status change */
#define	SAB_ISR0_RFO	0x02	/* rfifo overflow */
#define	SAB_ISR0_RPF	0x01	/* receive pool full */

/* SAB_ISR1: interrupt status 1 */
#define	SAB_ISR1_BRK	0x80	/* break detected */
#define	SAB_ISR1_BRKT	0x40	/* break terminated */
#define	SAB_ISR1_ALLS	0x20	/* all sent */
#define	SAB_ISR1_XOFF	0x10	/* xoff detected */
#define	SAB_ISR1_TIN	0x08	/* timer interrupt */
#define	SAB_ISR1_CSC	0x04	/* clear to send status change */
#define	SAB_ISR1_XON	0x02	/* xon detected */
#define	SAB_ISR1_XPR	0x01	/* transmit pool ready */

/* SAB_IMR0: interrupt mask 0 */
#define	SAB_IMR0_TCD	0x80	/* termination character detected */
#define	SAB_IMR0_TIME	0x40	/* time-out limit exceeded */
#define	SAB_IMR0_PERR	0x20	/* parity error */
#define	SAB_IMR0_FERR	0x10	/* framing error */
#define	SAB_IMR0_PLLA	0x08	/* dpll asynchronous */
#define	SAB_IMR0_CDSC	0x04	/* carrier detect status change */
#define	SAB_IMR0_RFO	0x02	/* rfifo overflow */
#define	SAB_IMR0_RPF	0x01	/* receive pool full */

/* SAB_ISR1: interrupt mask 1 */
#define	SAB_IMR1_BRK	0x80	/* break detected */
#define	SAB_IMR1_BRKT	0x40	/* break terminated */
#define	SAB_IMR1_ALLS	0x20	/* all sent */
#define	SAB_IMR1_XDU	0x10	/* xoff detected */
#define	SAB_IMR1_TIN	0x08	/* timer interrupt */
#define	SAB_IMR1_CSC	0x04	/* clear to send status change */
#define	SAB_IMR1_XMR	0x02	/* xon detected */
#define	SAB_IMR1_XPR	0x01	/* transmit pool ready */

/* SAB_PVR: port value register */
#define	SAB_PVR_DSR_A	0x01	/* port A DSR */
#define	SAB_PVR_DTR_A	0x02	/* port A DTR */
#define	SAB_PVR_DTR_B	0x04	/* port B DTR */
#define	SAB_PVR_DSR_B	0x08	/* port B DSR */
#define	SAB_PVR_MAGIC	0x10	/* dunno... */

/* SAB_CCR4: channel configuration register 4 */
#define	SAB_CCR4_MCK4	0x80	/* master clock divide by 4 */
#define	SAB_CCR4_EBRG	0x40	/* enhanced baud rate generator mode */
#define	SAB_CCR4_TST1	0x20	/* test pin */
#define	SAB_CCR4_ICD	0x10	/* invert polarity of carrier detect */

/* Receive status byte */
#define	SAB_RSTAT_PE	0x80	/* parity error */
#define	SAB_RSTAT_FE	0x40	/* framing error */
#define	SAB_RSTAT_PAR	0x01	/* parity bit */

#endif /* _DEV_IC_SAB82532_H_ */


code:
/*
 * Copyright 2004 by Peter Grehan. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: release/9.0.0/sys/dev/ic/via6522reg.h 153030 2005-12-02 22:36:14Z grehan $
 */

#ifndef _VIA6522REG_H_
#define _VIA6522REG_H_

/* Registers */
#define REG_OIRB	0	/* Input/output register B */
#define REG_OIRA	1	/* Input/output register A */
#define REG_DDRB	2	/* Data direction register B */
#define REG_DDRA	3	/* Data direction register A */
#define REG_T1CL	4	/* T1 low-order latch/low-order counter */
#define REG_T1CH	5	/* T1 high-order counter */
#define REG_T1LL	6	/* T1 low-order latches */
#define REG_T1LH	7	/* T1 high-order latches */
#define REG_T2CL	8	/* T2 low-order latch/low-order counter */
#define REG_T2CH	9	/* T2 high-order counter */
#define REG_SR		10	/* Shift register */
#define REG_ACR		11	/* Auxiliary control register */
#define REG_PCR		12	/* Peripheral control register */
#define REG_IFR		13	/* Interrupt flag register */
#define REG_IER		14	/* Interrupt-enable register */
#define REG_OIRA_NH	15	/* Input/output register A: no handshake */

/* Auxiliary control register (11) */
#define ACR_SR_NONE	0x0	/* Disabled */
#define ACR_SR_DIR	0x4	/* Bit for shift-register direction 1=out */
#define ACR_SRI_T2	0x1	/* Shift in under control of T2 */
#define ACR_SRI_PHI2	0x2	/*   "    "   "     "      " PHI2 */
#define ACR_SRI_EXTCLK	0x3	/*   "    "   "     "      " external clk */
#define ACR_SRO		0x4	/* Shift out free running at T2 rate */
#define ACR_SRO_T2	0x5	/* Shift out under control of T2 */
#define ACR_SRO_PHI2	0x6	/*   "    "   "     "      "  PHI2 */
#define ACR_SRO_EXTCLK	0x7	/*   "    "   "     "      "  external clk */

#define ACR_T1_SHIFT	5	/* bits 7-5 */
#define ACR_SR_SHIFT	2	/* bits 4-2 */

/* Peripheral control register (12) */
#define PCR_INTCNTL	0x01	/* interrupt active edge: +ve=1, -ve=0 */

#define PCR_CNTL_MASK	0x3	/* 3 bits */
#define PCR_CNTL_NEDGE	0x0	/* Input - negative active edge */
#define PCR_CNTL_INEDGE 0x1	/* Interrupt - negative active edge */
#define PCR_CNTL_PEDGE	0x2	/* Input - positive active edge */
#define PCR_CNTL_IPEDGE 0x3	/* Interrupt - positive active edge */
#define PCR_CNTL_HSHAKE 0x4	/* Handshake output */
#define PCR_CNTL_PULSE	0x5	/* Pulse output */
#define PCR_CNTL_LOW	0x6	/* Low output */
#define PCR_CNTL_HIGH	0x7	/* High output */

#define PCR_CB2_SHIFT	5	/* bits 7-5 */
#define PCR_CB1_SHIFT	4	/* bit 4 */
#define PCR_CA2_SHIFT	1	/* bits 3-1 */
#define PCR_CA1_SHIFT	0	/* bit 0 */

/* Interrupt flag register (13) */
#define IFR_CA2		0x01
#define IFR_CA1		0x02
#define IFR_SR		0x04
#define IFR_CB2		0x08
#define IFR_CB1		0x10
#define IFR_T2		0x20
#define IFR_T1		0x40
#define IFR_IRQB       	0x80	/* status of IRQB output pin */

/* Interrupt enable register (14) */
#define IER_CA2		IFR_CA2
#define IER_CA1		IFR_CA1
#define IER_SR		IFR_SR
#define IER_CB2		IFR_CB2
#define IER_CB1		IFR_CB1
#define IER_T2		IFR_T2
#define IER_T1		IFR_T1
#define IER_IRQB	IFR_IRQB

#endif /* _VIA6522REG_H_ */

repo_name: veiledmerc/mira

license: mit


code:
/* $FreeBSD: release/9.0.0/sys/dev/ic/wd33c93reg.h 139749 2005-01-06 01:43:34Z imp $ */
/*	$NecBSD: wd33c93reg.h,v 1.21.24.1 2001/06/13 05:52:05 honda Exp $	*/
/*	$NetBSD$	*/
/*-
 * [NetBSD for NEC PC-98 series]
 *  Copyright (c) 1996, 1997, 1998
 *	NetBSD/pc98 porting staff. All rights reserved.
 *  Copyright (c) 1996, 1997, 1998
 *	Naofumi Honda. All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef	_WD33C93REG_H_
#define	_WD33C93REG_H_

/* wd33c93 register */
#define	wd3s_oid		0x00
#define	IDR_FS_16_20		0x80
#define	IDR_FS_12_15		0x40
#define	IDR_FS_8_10		0x00
#define	IDR_RAF			0x20
#define	IDR_EHP			0x10
#define	IDR_EAF			0x08
#define	IDR_IDM			0x07

#define	wd3s_ctrl		0x01
#define	CR_DMA			0x80
#define	CR_DMAD			0x40
#define	CR_HLT_HOST_PARITY	0x10
#define	CR_DIS_INT		0x08
#define	CR_IDIS_INT		0x04
#define	CR_HLT_ATN		0x02
#define	CR_HLT_BUS_PARITY	0x01
#define	CR_DEFAULT		(CR_DIS_INT | CR_IDIS_INT)
#define	CR_DEFAULT_HP		(CR_DEFAULT | CR_HLT_BUS_PARITY)

#define	wd3s_tout		0x02
#define	wd3s_cdb		0x03
#define	wd3s_lun		0x0f
#define	wd3s_cph		0x10
#define	wd3s_synch		0x11
#define	wd3s_cnt		0x12
#define	wd3s_did		0x15
#define	DIDR_SCC		0x80
#define	DIDR_DPD		0x40

#define	wd3s_sid		0x16
#define	SIDR_RESEL		0x80
#define	SIDR_SEL		0x40
#define	SIDR_VALID		0x08
#define	SIDR_IDM		0x07

#define	wd3s_stat		0x17

#define	BSR_CM			0xf0
#define	BSR_CMDCPL		0x10
#define	BSR_CMDABT		0x20
#define	BSR_CMDERR		0x40
#define	BSR_CMDREQ		0x80

#define	BSR_SM			0x0f
#define	BSR_PM			0x07
#define	BSR_PHVALID		0x08
#define	BSR_IOR			0x01
#define	BSR_DATAOUT		0x00
#define	BSR_DATAIN		0x01
#define	BSR_CMDOUT		0x02
#define	BSR_STATIN		0x03
#define	BSR_UNSPINFO0		0x04
#define	BSR_UNSPINFO1		0x05
#define	BSR_MSGOUT		0x06
#define	BSR_MSGIN		0x07

#define	BSR_RESET		0x00
#define	BSR_AFM_RESET		0x01
#define	BSR_SELECTED		0x11
#define	BSR_SATFIN		0x16
#define	BSR_ACKREQ		0x20
#define	BSR_SATSDP		0x21
#define	BSR_RESEL		0x80
#define	BSR_AFM_RESEL		0x81
#define	BSR_DISC		0x85

#define	wd3s_cmd		0x18
#define	wd3s_data		0x19
#define	wd3s_qtag		0x1a

#define	wd3s_mbank		0x30
#define	MBR_RST			0x02
#define	MBR_IEN			0x04

#define	wd3s_mwin		0x31
#define	wd3s_auxc		0x33
#define	AUXCR_HIDM		0x07
#define	AUXCR_INTM		0x38
#define	AUXCR_RRST		0x80

/* status port */
#define	STR_INT			0x80
#define	STR_LCI			0x40
#define	STR_BSY			0x20
#define	STR_CIP			0x10
#define	STR_PE			0x02
#define	STR_DBR			0x01
#define	STR_BUSY		0xf0

/* cmd port */
#define	CMDP_DMES		0x01
#define	CMDP_DMER		0x02
#define	CMDP_TCMS		0x04
#define	CMDP_TCMR		0x08
#define	CMDP_TCIR		0x10

/* wd33c93 chip cmds */
#define	WD3S_SBT		0x80
#define	WD3S_RESET		0x00
#define	WD3S_ABORT		0x01
#define	WD3S_ASSERT_ATN		0x02
#define	WD3S_NEGATE_ACK		0x03
#define	WD3S_DISCONNECT		0x04
#define	WD3S_RESELECT		0x05
#define	WD3S_SELECT_ATN		0x06
#define	WD3S_SELECT_NO_ATN	0x07
#define	WD3S_SELECT_ATN_TFR	0x08
#define	WD3S_SELECT_NO_ATN_TFR	0x09
#define	WD3S_RESELECT_RCV_DATA	0x0a
#define	WD3S_RESELECT_SEND_DATA	0x0b
#define	WD3S_WAIT_SELECT_RCV	0x0c
#define	WD3S_CMD_COMPSEQ	0x0d
#define	WD3S_SEND_DISC_MSG	0x0e
#define	WD3S_SET_IDI		0x0f
#define	WD3S_RCV_CMD		0x10
#define	WD3S_RCV_DATA		0x11
#define	WD3S_RCV_MSG_OUT	0x12
#define	WD3S_RCV_UNSP_INFO_OUT	0x13
#define	WD3S_SEND_STATUS	0x14
#define	WD3S_SEND_DATA		0x15
#define	WD3S_SEND_MSG_IN	0x16
#define	WD3S_SEND_UNSP_INFO_IN	0x17
#define	WD3S_TRANSLATE_ADDRESS	0x18
#define	WD3S_TFR_INFO		0x20

#endif	/* !_WD33C93REG_H_ */


code:
/*-
 * Copyright (c) 2003 Marcel Moolenaar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * $FreeBSD: release/9.0.0/sys/dev/ic/z8530.h 155967 2006-02-24 02:03:35Z marcel $
 */

#ifndef _DEV_IC_Z8530_H_
#define	_DEV_IC_Z8530_H_

/*
 * Channel B control:	0
 * Channel B data:	1
 * Channel A control:	2
 * Channel A data:	3
 */

/* The following apply when using a device-scoped bus handle */
#define	CHAN_A		2
#define	CHAN_B		0

#define	REG_CTRL	0
#define	REG_DATA	1

/* Write registers. */
#define	WR_CR		0	/* Command Register. */
#define	WR_IDT		1	/* Interrupt and Data Transfer Mode. */
#define	WR_IV		2	/* Interrupt Vector (shared). */
#define	WR_RPC		3	/* Receive Parameters and Control. */
#define	WR_MPM		4	/* Miscellaneous Parameters and Modes. */
#define	WR_TPC		5	/* Transmit Parameters and Control. */
#define	WR_SCAF		6	/* Sync Character or (SDLC) Address Field. */
#define	WR_SCF		7	/* Sync Character or (SDCL) Flag. */
#define	WR_EFC		7	/* Extended Feature and FIFO Control. */
#define	WR_TB		8	/* Transmit Buffer. */
#define	WR_MIC		9	/* Master Interrupt Control (shared). */
#define	WR_MCB1		10	/* Miscellaneous Control Bits (part 1 :-). */
#define	WR_CMC		11	/* Clock Mode Control. */
#define	WR_TCL		12	/* BRG Time Constant Low. */
#define	WR_TCH		13	/* BRG Time Constant High. */
#define	WR_MCB2		14	/* Miscellaneous Control Bits (part 2 :-). */
#define	WR_IC		15	/* Interrupt Control. */

/* Read registers. */
#define	RR_BES		0	/* Buffer and External Status. */
#define	RR_SRC		1	/* Special Receive Condition. */
#define	RR_IV		2	/* Interrupt Vector. */
#define	RR_IP		3	/* Interrupt Pending (ch A only). */
#define	RR_MPM		4	/* Miscellaneous Parameters and Modes. */
#define	RR_TPC		5	/* Transmit Parameters and Control. */
#define	RR_BCL		6	/* Byte Count Low. */
#define	RR_BCH		7	/* Byte Count High. */
#define	RR_RB		8	/* Receive Buffer. */
#define	RR_RPC		9	/* Receive Parameters and Control. */
#define	RR_MSB		10	/* Miscellaneous Status Bits. */
#define	RR_MCB1		11	/* Miscellaneous Control Bits (part 1). */
#define	RR_TCL		12	/* BRG Time Constant Low. */
#define	RR_TCH		13	/* BRG Time Constant High. */
#define	RR_EFC		14	/* Extended Feature and FIFO Control. */
#define	RR_IC		15	/* Interrupt Control. */

/* Buffer and External Status (RR0). */
#define	BES_BRK		0x80	/* Break (Abort). */
#define	BES_TXU		0x40	/* Tx Underrun (EOM). */
#define	BES_CTS		0x20	/* CTS. */
#define	BES_SYNC	0x10	/* Sync. */
#define	BES_DCD		0x08	/* DCD. */
#define	BES_TXE		0x04	/* Tx Empty. */
#define	BES_ZC		0x02	/* Zero Count. */
#define	BES_RXA		0x01	/* Rx Available. */

/* Clock Mode Control (WR11). */
#define	CMC_XTAL	0x80	/* -RTxC connects to quartz crystal. */
#define	CMC_RC_DPLL	0x60	/* Rx Clock from DPLL. */
#define	CMC_RC_BRG	0x40	/* Rx Clock from BRG. */
#define	CMC_RC_TRXC	0x20	/* Rx Clock from -TRxC. */
#define	CMC_RC_RTXC	0x00	/* Rx Clock from -RTxC. */
#define	CMC_TC_DPLL	0x18	/* Tx Clock from DPLL */
#define	CMC_TC_BRG	0x10	/* Tx Clock from BRG */
#define	CMC_TC_TRXC	0x08	/* Tx Clock from -TRxC. */
#define	CMC_TC_RTXC	0x00	/* Tx Clock from -RTxC. */
#define	CMC_TRXC_OUT	0x04	/* -TRxC is output. */
#define	CMC_TRXC_DPLL	0x03	/* -TRxC from DPLL */
#define	CMC_TRXC_BRG	0x02	/* -TRxC from BRG */
#define	CMC_TRXC_XMIT	0x01	/* -TRxC from Tx clock. */
#define	CMC_TRXC_XTAL	0x00	/* -TRxC from XTAL. */

/* Command Register (WR0). */
#define	CR_RSTTXU	0xc0	/* Reset Tx. Underrun/EOM. */
#define	CR_RSTTXCRC	0x80	/* Reset Tx. CRC. */
#define	CR_RSTRXCRC	0x40	/* Reset Rx. CRC. */
#define	CR_RSTIUS	0x38	/* Reset Int. Under Service. */
#define	CR_RSTERR	0x30	/* Error Reset. */
#define	CR_RSTTXI	0x28	/* Reset Tx. Int. */
#define	CR_ENARXI	0x20	/* Enable Rx. Int. */
#define	CR_ABORT	0x18	/* Send Abort. */
#define	CR_RSTXSI	0x10	/* Reset Ext/Status Int. */

/* Extended Feature and FIFO Control (WR7 prime). */
#define	EFC_ERE		0x40	/* Extended Read Enable. */
#define	EFC_FE		0x20	/* Transmit FIFO Empty. */
#define	EFC_RQT		0x10	/* Request Timing. */
#define	EFC_FHF		0x08	/* Receive FIFO Half Full. */
#define	EFC_RTS		0x04	/* Auto RTS Deactivation. */
#define	EFC_EOM		0x02	/* Auto EOM Reset. */
#define	EFC_FLAG	0x01	/* Auto SDLC Flag on Tx. */

/* Interrupt Control (WR15). */
#define	IC_BRK		0x80	/* Break (Abort) IE. */
#define	IC_TXU		0x40	/* Tx Underrun IE. */
#define	IC_CTS		0x20	/* CTS IE. */
#define	IC_SYNC		0x10	/* Sync IE. */
#define	IC_DCD		0x08	/* DCD IE. */
#define	IC_FIFO		0x04	/* SDLC FIFO Enable. */
#define	IC_ZC		0x02	/* Zero Count IE. */
#define	IC_EF		0x01	/* Extended Feature Enable. */

/* Interrupt and Data Transfer Mode (WR1). */
#define	IDT_WRE		0x80	/* Wait/DMA Request Enable. */
#define	IDT_REQ		0x40	/* DMA Request. */
#define	IDT_WRR		0x20	/* Wait/DMA Reuest on Receive. */
#define	IDT_RISC	0x18	/* Rx Int. on Special Condition Only. */
#define	IDT_RIA		0x10	/* Rx Int. on All Characters. */
#define	IDT_RIF		0x08	/* Rx Int. on First Character. */
#define	IDT_PSC		0x04	/* Parity is Special Condition. */
#define	IDT_TIE		0x02	/* Tx Int. Enable. */
#define	IDT_XIE		0x01	/* Ext. Int. Enable. */

/* Interrupt Pending (RR3). */
#define	IP_RIA		0x20	/* Rx. Int. ch. A. */
#define	IP_TIA		0x10	/* Tx. Int. ch. A. */
#define	IP_SIA		0x08	/* Ext/Status Int. ch. A. */
#define	IP_RIB		0x04	/* Rx. Int. ch. B. */
#define	IP_TIB		0x02	/* Tx. Int. ch. B. */
#define	IP_SIB		0x01	/* Ext/Status Int. ch. B. */

/* Interrupt Vector Status Low (RR2). */
#define	IV_SCA		0x0e	/* Special Condition ch. A. */
#define	IV_RAA		0x0c	/* Receive Available ch. A. */
#define	IV_XSA		0x0a	/* External/Status Change ch. A. */
#define	IV_TEA		0x08	/* Transmitter Empty ch. A. */
#define	IV_SCB		0x06	/* Special Condition ch. B. */
#define	IV_RAB		0x04	/* Receive Available ch. B. */
#define	IV_XSB		0x02	/* External/Status Change ch. B. */
#define	IV_TEB		0x00	/* Transmitter Empty ch. B. */

/* Miscellaneous Control Bits part 1 (WR10). */
#define	MCB1_CRC1	0x80	/* CRC presets to 1. */
#define	MCB1_FM0	0x60	/* FM0 Encoding. */
#define	MCB1_FM1	0x40	/* FM1 Encoding. */
#define	MCB1_NRZI	0x20	/* NRZI Encoding. */
#define	MCB1_NRZ	0x00	/* NRZ Encoding. */
#define	MCB1_AOP	0x10	/* Active On Poll. */
#define	MCB1_MI		0x08	/* Mark Idle. */
#define	MCB1_AOU	0x04	/* Abort On Underrun. */
#define	MCB1_LM		0x02	/* Loop Mode. */
#define	MCB1_SIX	0x01	/* 6 or 12 bit SYNC. */

/* Miscellaneous Control Bits part 2 (WR14). */
#define	MCB2_NRZI	0xe0	/* DPLL - NRZI mode. */
#define	MCB2_FM		0xc0	/* DPLL - FM mode. */
#define	MCB2_RTXC	0xa0	/* DPLL - Clock from -RTxC. */
#define	MCB2_BRG	0x80	/* DPLL - Clock from BRG. */
#define	MCB2_OFF	0x60	/* DPLL - Disable. */
#define	MCB2_RMC	0x40	/* DPLL - Reset Missing Clock. */
#define	MCB2_ESM	0x20	/* DPLL - Enter Search Mode. */
#define	MCB2_LL		0x10	/* Local Loopback. */
#define	MCB2_AE		0x08	/* Auto Echo. */
#define	MCB2_REQ	0x04	/* Request Function. */
#define	MCB2_PCLK	0x02	/* BRG source is PCLK. */
#define	MCB2_BRGE	0x01	/* BRG enable. */

/* Master Interrupt Control (WR9). */
#define	MIC_FHR		0xc0	/* Force Hardware Reset. */
#define	MIC_CRA		0x80	/* Channel Reset A. */
#define	MIC_CRB		0x40	/* Channel Reset B. */
#define	MIC_SIE		0x20	/* Software INTACK Enable. */
#define	MIC_SH		0x10	/* Status High. */
#define	MIC_MIE		0x08	/* Master Interrupt Enable. */
#define	MIC_DLC		0x04	/* Disable Lower Chain. */
#define	MIC_NV		0x02	/* No Vector. */
#define	MIC_VIS		0x01	/* Vector Includes Status. */

/* Transmit/Receive Miscellaneous Parameters and Modes (WR4). */
#define	MPM_CM64	0xc0	/* X64 Clock Mode. */
#define	MPM_CM32	0x80	/* X32 Clock Mode. */
#define	MPM_CM16	0x40	/* X16 Clock Mode. */
#define	MPM_CM1		0x00	/* X1 Clock Mode. */
#define	MPM_EXT		0x30	/* External Sync Mode. */
#define	MPM_SDLC 	0x20	/* SDLC mode. */
#define	MPM_BI		0x10	/* 16-bit Sync (bi-sync). */
#define	MPM_MONO	0x00	/* 8-bit Sync (mono-sync). */
#define	MPM_SB2 	0x0c	/* Async mode: 2 stopbits. */
#define	MPM_SB15 	0x08	/* Async mode: 1.5 stopbits. */
#define	MPM_SB1 	0x04	/* Async mode: 1 stopbit. */
#define	MPM_SYNC	0x00	/* Sync Mode Enable. */
#define	MPM_EVEN 	0x02	/* Async mode: even parity. */
#define	MPM_PE		0x01	/* Async mode: parity enable. */

/* Receive Parameters and Control (WR3). */
#define	RPC_RB8		0xc0	/* 8 databits. */
#define	RPC_RB6		0x80	/* 6 databits. */
#define	RPC_RB7		0x40	/* 7 databits. */
#define	RPC_RB5		0x00	/* 5 databits. */
#define	RPC_AE		0x20	/* Auto Enable. */
#define	RPC_EHM		0x10	/* Enter Hunt Mode. */
#define	RPC_CRC		0x08	/* CRC Enable. */
#define	RPC_ASM		0x04	/* Address Search Mode. */
#define	RPC_LI		0x02	/* SYNC Character Load Inhibit */
#define	RPC_RXE		0x01	/* Receiver Enable */

/* Special Receive Condition (RR1). */
#define	SRC_EOF		0x80	/* End Of Frame. */
#define	SRC_FE		0x40	/* Framing Error. */
#define	SRC_OVR		0x20	/* Rx. Overrun. */
#define	SRC_PE		0x10	/* Parity Error. */
#define	SRC_RC0		0x08	/* Residue Code 0. */
#define	SRC_RC1		0x04	/* Residue Code 1. */
#define	SRC_RC2		0x02	/* Residue Code 2. */
#define	SRC_AS		0x01	/* All Sent. */

/* Transmit Parameter and Control (WR5). */
#define	TPC_DTR		0x80	/* DTR. */
#define	TPC_TB8		0x60	/* 8 databits. */
#define	TPC_TB6		0x40	/* 6 databits. */
#define	TPC_TB7		0x20	/* 7 databits. */
#define	TPC_TB5		0x00	/* 5 or fewer databits. */
#define	TPC_BRK		0x10	/* Send break. */
#define	TPC_TXE		0x08	/* Transmitter Enable. */
#define	TPC_CRC16	0x04	/* CRC16. */
#define	TPC_RTS		0x02	/* RTS. */
#define	TPC_CRC		0x01	/* CRC Enable. */

#endif /* _DEV_IC_Z8530_H_ */


code:
/*-
 * Copyright (c) 2005 Poul-Henning Kamp
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * This file defines the ABI between the userland gpib library and the
 * kernel.  This file should not be used anywhere else.
 *
 * $FreeBSD: release/9.0.0/sys/dev/ieee488/ibfoo_int.h 141768 2005-02-12 21:07:09Z phk $
 */

#include <sys/ioccom.h>

typedef void ibsrq_t(void);
enum ibfoo_id {
	__ID_INVALID = 0,
	__ID_IBASK,
	__ID_IBBNA,
	__ID_IBCAC,
	__ID_IBCLR,
	__ID_IBCMD,
	__ID_IBCMDA,
	__ID_IBCONFIG,
	__ID_IBDEV,
	__ID_IBDIAG,
	__ID_IBDMA,
	__ID_IBEOS,
	__ID_IBEOT,
	__ID_IBEVENT,
	__ID_IBFIND,
	__ID_IBGTS,
	__ID_IBIST,
	__ID_IBLINES,
	__ID_IBLLO,
	__ID_IBLN,
	__ID_IBLOC,
	__ID_IBONL,
	__ID_IBPAD,
	__ID_IBPCT,
	__ID_IBPOKE,
	__ID_IBPPC,
	__ID_IBRD,
	__ID_IBRDA,
	__ID_IBRDF,
	__ID_IBRDKEY,
	__ID_IBRPP,
	__ID_IBRSC,
	__ID_IBRSP,
	__ID_IBRSV,
	__ID_IBSAD,
	__ID_IBSGNL,
	__ID_IBSIC,
	__ID_IBSRE,
	__ID_IBSRQ,
	__ID_IBSTOP,
	__ID_IBTMO,
	__ID_IBTRAP,
	__ID_IBTRG,
	__ID_IBWAIT,
	__ID_IBWRT,
	__ID_IBWRTA,
	__ID_IBWRTF,
	__ID_IBWRTKEY,
	__ID_IBXTRC
};

#define __F_HANDLE              (1 << 0)
#define __F_SPR                 (1 << 1)
#define __F_BUFFER              (1 << 2)
#define __F_RETVAL              (1 << 3)
#define __F_BDNAME              (1 << 4)
#define __F_MASK                (1 << 5)
#define __F_PADVAL              (1 << 6)
#define __F_SADVAL              (1 << 7)
#define __F_CNT                 (1 << 8)
#define __F_TMO                 (1 << 9)
#define __F_EOS                 (1 << 10)
#define __F_PPR                 (1 << 11)
#define __F_EOT                 (1 << 12)
#define __F_V                   (1 << 13)
#define __F_VALUE               (1 << 14)
#define __F_SAD                 (1 << 15)
#define __F_BOARDID             (1 << 16)
#define __F_OPTION              (1 << 17)
#define __F_FLNAME              (1 << 18)
#define __F_FUNC                (1 << 19)
#define __F_LINES               (1 << 20)
#define __F_PAD                 (1 << 21)
#define __F_MODE                (1 << 22)
#define __F_LISTENFLAG          (1 << 23)
#define __F_EVENT               (1 << 24)

struct ibarg {
	enum ibfoo_id       __ident;
	unsigned int        __field;
	int		    __retval;
	int		    __ibsta;
	int		    __iberr;
	int		    __ibcnt;
	int                 handle;
	char *              spr;
	void *              buffer;
	int *               retval;
	char *              bdname;
	int                 mask;
	int                 padval;
	int                 sadval;
	long                cnt;
	int                 tmo;
	int                 eos;
	char *              ppr;
	int                 eot;
	int                 v;
	int                 value;
	int                 sad;
	int                 boardID;
	int                 option;
	char *              flname;
	ibsrq_t *           func;
	short *             lines;
	int                 pad;
	int                 mode;
	short *             listenflag;
	short *             event;
};

#define GPIB_IBFOO	_IOWR(4, 0, struct ibarg)


code:
/*-
 * Copyright (c) 2010 Joerg Wunsch
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: release/9.0.0/sys/dev/ieee488/tnt4882.h 203360 2010-02-01 21:21:10Z joerg $
 */

enum tnt4882reg {
	dir = 0x00,
	cdor = 0x00,
	isr1 = 0x02,
	imr1 = 0x02,
	isr2 = 0x04,
	imr2 = 0x04,
	accwr = 0x05,
	spsr = 0x06,
	spmr = 0x06,
	intr = 0x07,
	adsr = 0x08,
	admr = 0x08,
	cnt2 = 0x09,
	cptr = 0x0a,
	auxmr = 0x0a,
	tauxcr = 0x0a,	/* 9914 mode register */
	cnt3 = 0x0b,
	adr0 = 0x0c,
	adr = 0x0c,
	hssel = 0x0d,
	adr1 = 0x0e,
	eosr = 0x0e,
	sts1 = 0x10,
	cfg = 0x10,
	dsr = 0x11,
	sh_cnt = 0x11,
	imr3 = 0x12,
	hier = 0x13,
	cnt0 = 0x14,
	misc = 0x15,
	cnt1 = 0x16,
	csr = 0x17,
	keyreg = 0x17,
	fifob = 0x18,
	fifoa = 0x19,
	isr3 = 0x1a,
	ccr = 0x1a,
	sasr = 0x1b,
	dcr = 0x1b,
	sts2 = 0x1c,
	cmdr = 0x1c,
	isr0 = 0x1d,
	imr0 = 0x1d,
	timer = 0x1e,
	bsr = 0x1f,
	bcr = 0x1f
};


code:
/*-
 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: release/9.0.0/sys/dev/ieee488/ugpib.h 141777 2005-02-12 23:52:44Z phk $
 *
 */

#ifndef _DEV_IEEE488_UGPIB_H_
#define _DEV_IEEE488_UGPIB_H_

/* ibfoo() return values */
#define EDVR	0		/* System error				*/
#define ECIC	1		/* Not Active Controller		*/
#define ENOL	2		/* Nobody listening			*/
#define EADR	3		/* Controller not addressed		*/
#define EARG	4		/* Invalid argument			*/
#define ESAC	5		/* Not System Controller		*/
#define EABO	6		/* I/O Aborted/Time out			*/
#define ENEB	7		/* No such controller			*/
#define EOIP	10		/* Async I/O in progress		*/
#define ECAP	11		/* No such capability			*/
#define EFSO	12		/* File system error			*/
#define EBUS	14		/* Command byte xfer error		*/
#define ESTB	15		/* Serial poll status byte lost		*/
#define ESRQ	16		/* SRQ line stuck			*/
#define ETAB	20		/* Table problem			*/

/* ibsta bits */
#define ERR	(1<<15)		/* Error				*/
#define TIMO	(1<<14)		/* Timeout				*/
#define END	(1<<13)		/* EOI/EOS				*/
#define SRQI	(1<<12)		/* SRQ					*/
#define RQS	(1<<11)		/* Device requests service		*/
#define SPOLL	(1<<10)		/* Serial Poll				*/
#define EVENT	(1<<9)		/* Event occured			*/
#define CMPL	(1<<8)		/* I/O complete				*/
#define LOK	(1<<7)		/* Lockout				*/
#define REM	(1<<6)		/* Remote				*/
#define CIC	(1<<5)		/* CIC					*/
#define ATN	(1<<4)		/* ATN					*/
#define TACS	(1<<3)		/* Talker				*/
#define LACS	(1<<2)		/* Listener				*/
#define DTAS	(1<<1)		/* Device trigger status		*/
#define DCAS	(1<<0)		/* Device clear state			*/

/* Timeouts */
#define TNONE	0
#define T10us	1
#define T30us	2
#define T100us	3
#define T300us	4
#define T1ms	5
#define T3ms	6
#define T10ms	7
#define T30ms	8
#define T100ms	9
#define T300ms	10
#define T1s	11
#define T3s	12
#define T10s	13
#define T30s	14
#define T100s	15
#define T300s	16
#define T1000s	17

/* EOS bits */
#define REOS	(1 << 10)
#define XEOS	(1 << 11)
#define BIN	(1 << 12)

/* Bus commands */
#define GTL	0x01		/* Go To Local				*/
#define SDC	0x04		/* Selected Device Clear		*/
#define GET	0x08		/* Group Execute Trigger		*/
#define LAD	0x20		/* Listen address			*/
#define UNL	0x3F		/* Unlisten				*/
#define TAD	0x40		/* Talk address				*/
#define UNT	0x5F		/* Untalk				*/

#ifndef _KERNEL

extern int ibcnt, iberr, ibsta;

int ibask(int handle, int option, int *retval);
int ibbna(int handle, char *bdname);
int ibcac(int handle, int v);
int ibclr(int handle);
int ibcmd(int handle, void *buffer, long cnt);
int ibcmda(int handle, void *buffer, long cnt);
int ibconfig(int handle, int option, int value);
int ibdev(int boardID, int pad, int sad, int tmo, int eot, int eos);
int ibdiag(int handle, void *buffer, long cnt);
int ibdma(int handle, int v);
int ibeos(int handle, int eos);
int ibeot(int handle, int eot);
int ibevent(int handle, short *event);
int ibfind(char *bdname);
int ibgts(int handle, int v);
int ibist(int handle, int v);
int iblines(int handle, short *lines);
int ibllo(int handle);
int ibln(int handle, int padval, int sadval, short *listenflag);
int ibloc(int handle);
int ibonl(int handle, int v);
int ibpad(int handle, int pad);
int ibpct(int handle);
int ibpoke(int handle, int option, int value);
int ibppc(int handle, int v);
int ibrd(int handle, void *buffer, long cnt);
int ibrda(int handle, void *buffer, long cnt);
int ibrdf(int handle, char *flname);
int ibrdkey(int handle, void *buffer, int cnt);
int ibrpp(int handle, char *ppr);
int ibrsc(int handle, int v);
int ibrsp(int handle, char *spr);
int ibrsv(int handle, int v);
int ibsad(int handle, int sad);
int ibsgnl(int handle, int v);
int ibsic(int handle);
int ibsre(int handle, int v);
int ibsrq(void (*func)(void));
int ibstop(int handle);
int ibtmo(int handle, int tmo);
int ibtrap(int  mask, int mode);
int ibtrg(int handle);
int ibwait(int handle, int mask);
int ibwrt(int handle, const void *buffer, long cnt);
int ibwrta(int handle, const void *buffer, long cnt);
int ibwrtf(int handle, const char *flname);
int ibwrtkey(int handle, const void *buffer, int cnt);
int ibxtrc(int handle, void *buffer, long cnt);
#endif /* _KERNEL */
#endif /* _DEV_IEEE488_UGPIB_H_ */


code:
/*-
 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
 * Copyright (c) 2010 Joerg Wunsch <joerg@FreeBSD.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: release/9.0.0/sys/dev/ieee488/upd7210.h 203360 2010-02-01 21:21:10Z joerg $
 *
 * Locating an actual �PD7210 data book has proven quite impossible for me.
 * There are a fair number of newer chips which are supersets of the �PD7210
 * but they are particular eager to comprehensively mark what the extensions
 * are and what is in the base set.  Some even give the registers and their
 * bits new names.
 *
 * The following information is based on a description of the �PD7210 found
 * in an old manual for a VME board which used the chip.
 */

#ifndef _DEV_IEEE488_UPD7210_H_
#define _DEV_IEEE488_UPD7210_H_
#ifdef _KERNEL

struct upd7210;
struct ibfoo;

/* upd7210 interface definitions for HW drivers */

typedef int upd7210_irq_t(struct upd7210 *, int);

struct upd7210 {
	struct resource		*reg_res[8];
	struct resource		*irq_clear_res;
	u_int			reg_offset[8];
	int			dmachan;
	int			unit;
	int			use_fifo;

	/* private stuff */
	struct mtx		mutex;
	uint8_t			rreg[8];
	uint8_t			wreg[8 + 8];

	upd7210_irq_t		*irq;

	int			busy;
	u_char			*buf;
	size_t			bufsize;
	u_int			buf_wp;
	u_int			buf_rp;
	struct cdev		*cdev;

	struct ibfoo		*ibfoo;
};

#ifdef UPD7210_HW_DRIVER
void upd7210intr(void *);
void upd7210attach(struct upd7210 *);
void upd7210detach(struct upd7210 *);
#endif

#ifdef UPD7210_SW_DRIVER

/* upd7210 hardware definitions. */

/* Write registers */
enum upd7210_wreg {
	CDOR	= 0,			/* Command/Data Out Register	*/
	IMR1	= 1,			/* Interrupt Mask Register 1	*/
	IMR2	= 2,			/* Interrupt Mask Register 2	*/
	SPMR	= 3,			/* Serial Poll Mode Register	*/
	ADMR	= 4,			/* ADdress Mode Register	*/
	AUXMR	= 5,			/* AUXilliary Mode Register	*/
	ICR	= 5,			/* Internal Counter Register	*/
	PPR	= 5,			/* Parallel Poll Register	*/
	AUXRA	= 5,			/* AUXilliary Register A	*/
	AUXRB	= 5,			/* AUXilliary Register B	*/
	AUXRE	= 5,			/* AUXilliary Register E	*/
	ADR	= 6,			/* ADdress Register		*/
	EOSR	= 7,			/* End-Of-String Register	*/
};

/* Read registers */
enum upd7210_rreg {
	DIR	= 0,			/* Data In Register		*/
	ISR1	= 1,			/* Interrupt Status Register 1	*/
	ISR2	= 2,			/* Interrupt Status Register 2	*/
	SPSR	= 3,			/* Serial Poll Status Register	*/
	ADSR	= 4,			/* ADdress Status Register	*/
	CPTR	= 5,			/* Command Pass Though Register	*/
	ADR0	= 6,			/* ADdress Register 0		*/
	ADR1	= 7,			/* ADdress Register 1		*/
};

/* Bits for ISR1 and IMR1 */
#define IXR1_DI		(1 << 0)	/* Data In			*/
#define IXR1_DO		(1 << 1)	/* Data Out			*/
#define IXR1_ERR	(1 << 2)	/* Error			*/
#define IXR1_DEC	(1 << 3)	/* Device Clear			*/
#define IXR1_ENDRX	(1 << 4)	/* End Received			*/
#define IXR1_DET	(1 << 5)	/* Device Execute Trigger	*/
#define IXR1_APT	(1 << 6)	/* Address Pass-Through		*/
#define IXR1_CPT	(1 << 7)	/* Command Pass-Through		*/

/* Bits for ISR2 and IMR2 */
#define IXR2_ADSC	(1 << 0)	/* Addressed Status Change	*/
#define IXR2_REMC	(1 << 1)	/* Remote Change		*/
#define IXR2_LOKC	(1 << 2)	/* Lockout Change		*/
#define IXR2_CO		(1 << 3)	/* Command Out			*/
#define ISR2_REM	(1 << 4)	/* Remove			*/
#define IMR2_DMAI	(1 << 4)	/* DMA In Enable		*/
#define ISR2_LOK	(1 << 5)	/* Lockout			*/
#define IMR2_DMAO	(1 << 5)	/* DMA Out Enable		*/
#define IXR2_SRQI	(1 << 6)	/* Service Request Input	*/
#define ISR2_INT	(1 << 7)	/* Interrupt			*/

#define SPSR_PEND	(1 << 6)	/* Pending			*/
#define SPMR_RSV	(1 << 6)	/* Request SerVice		*/

#define ADSR_MJMN	(1 << 0)	/* MaJor MiNor			*/
#define ADSR_TA		(1 << 1)	/* Talker Active		*/
#define ADSR_LA		(1 << 2)	/* Listener Active		*/
#define ADSR_TPAS	(1 << 3)	/* Talker Primary Addr. State	*/
#define ADSR_LPAS	(1 << 4)	/* Listener Primary Addr. State	*/
#define ADSR_SPMS	(1 << 5)	/* Serial Poll Mode State	*/
#define ADSR_ATN	(1 << 6)	/* Attention			*/
#define ADSR_CIC	(1 << 7)	/* Controller In Charge		*/

#define ADMR_ADM0	(1 << 0)	/* Address Mode 0		*/
#define ADMR_ADM1	(1 << 1)	/* Address Mode 1		*/
#define ADMR_TRM0	(1 << 4)	/* Transmit/Receive Mode 0	*/
#define ADMR_TRM1	(1 << 5)	/* Transmit/Receive Mode 1	*/
#define ADMR_LON	(1 << 6)	/* Listen Only			*/
#define ADMR_TON	(1 << 7)	/* Talk Only			*/

/* Constant part of overloaded write registers */
#define	C_ICR		0x20
#define	C_PPR		0x60
#define	C_AUXA		0x80
#define	C_AUXB		0xa0
#define	C_AUXE		0xc0

#define AUXMR_PON	0x00		/* Immediate Execute pon	*/
#define AUXMR_CPP	0x01		/* Clear Parallel Poll		*/
#define AUXMR_CRST	0x02		/* Chip Reset			*/
#define AUXMR_RFD	0x03		/* Finish Handshake		*/
#define AUXMR_TRIG	0x04		/* Trigger			*/
#define AUXMR_RTL	0x05		/* Return to local		*/
#define AUXMR_SEOI	0x06		/* Send EOI			*/
#define AUXMR_NVSA	0x07		/* Non-Valid Secondary cmd/addr	*/
					/* 0x08 undefined/unknown	*/
#define AUXMR_SPP	0x09		/* Set Parallel Poll		*/
					/* 0x0a undefined/unknown	*/
					/* 0x0b undefined/unknown	*/
					/* 0x0c undefined/unknown	*/
					/* 0x0d undefined/unknown	*/
					/* 0x0e undefined/unknown	*/
#define AUXMR_VSA	0x0f		/* Valid Secondary cmd/addr	*/
#define AUXMR_GTS	0x10		/* Go to Standby		*/
#define AUXMR_TCA	0x11		/* Take Control Async (pulsed)	*/
#define AUXMR_TCS	0x12		/* Take Control Synchronously	*/
#define AUXMR_LISTEN	0x13		/* Listen			*/
#define AUXMR_DSC	0x14		/* Disable System Control	*/
					/* 0x15 undefined/unknown	*/
#define AUXMR_SIFC	0x16		/* Set IFC			*/
#define AUXMR_CREN	0x17		/* Clear REN			*/
					/* 0x18 undefined/unknown	*/
					/* 0x19 undefined/unknown	*/
#define AUXMR_TCSE	0x1a		/* Take Control Sync on End	*/
#define AUXMR_LCM	0x1b		/* Listen Continuously Mode	*/
#define AUXMR_LUNL	0x1c		/* Local Unlisten		*/
#define AUXMR_EPP	0x1d		/* Execute Parallel Poll	*/
#define AUXMR_CIFC	0x1e		/* Clear IFC			*/
#define AUXMR_SREN	0x1f		/* Set REN			*/

#define PPR_U		(1 << 4)	/* Unconfigure			*/
#define PPR_S		(1 << 3)	/* Status Polarity		*/

#define AUXA_HLDA	(1 << 0)	/* Holdoff on All		*/
#define AUXA_HLDE	(1 << 1)	/* Holdoff on END		*/
#define AUXA_REOS	(1 << 2)	/* End on EOS received		*/
#define AUXA_XEOS	(1 << 3)	/* Transmit END with EOS	*/
#define AUXA_BIN	(1 << 4)	/* Binary			*/

#define AUXB_CPTE	(1 << 0)	/* Cmd Pass Through Enable	*/
#define AUXB_SPEOI	(1 << 1)	/* Send Serial Poll EOI		*/
#define AUXB_TRI	(1 << 2)	/* Three-State Timing		*/
#define AUXB_INV	(1 << 3)	/* Invert			*/
#define AUXB_ISS	(1 << 4)	/* Individual Status Select	*/

#define AUXE_DHDT	(1 << 0)	/* DAC Holdoff on DTAS		*/
#define AUXE_DHDC	(1 << 1)	/* DAC Holdoff on DCAS		*/

#define ADR0_DL0	(1 << 5)	/* Disable Listener 0		*/
#define ADR0_DT0	(1 << 6)	/* Disable Talker 0		*/

#define ADR_DL		(1 << 5)	/* Disable Listener		*/
#define ADR_DT		(1 << 6)	/* Disable Talker		*/
#define ADR_ARS		(1 << 7)	/* Address Register Select	*/

#define ADR1_DL1	(1 << 5)	/* Disable Listener 1		*/
#define ADR1_DT1	(1 << 6)	/* Disable Talker 1		*/
#define ADR1_EOI	(1 << 7)	/* End or Identify		*/

/* Stuff from software drivers */
extern struct cdevsw gpib_ib_cdevsw;

/* Stuff from upd7210.c */
void upd7210_print_isr(u_int isr1, u_int isr2);
u_int upd7210_rd(struct upd7210 *u, enum upd7210_rreg reg);
void upd7210_wr(struct upd7210 *u, enum upd7210_wreg reg, u_int val);
int upd7210_take_ctrl_async(struct upd7210 *u);
int upd7210_goto_standby(struct upd7210 *u);

#endif /* UPD7210_SW_DRIVER */

#endif /* _KERNEL */
#endif /* _DEV_IEEE488_UPD7210_H_ */


code:
/*-
 * Copyright (c) 1998 Nicolas Souchu
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: release/9.0.0/sys/dev/iicbus/iic.h 210998 2010-08-07 08:31:32Z joel $
 *
 */
#ifndef __IIC_H
#define __IIC_H

#include <sys/ioccom.h>

/* Designed to be compatible with linux's struct i2c_msg */
struct iic_msg
{
	uint16_t	slave;
	uint16_t	flags;
#define	IIC_M_WR	0	/* Fake flag for write */
#define	IIC_M_RD	0x0001	/* read vs write */
#define	IIC_M_NOSTOP	0x0002	/* do not send a I2C stop after message */
#define	IIC_M_NOSTART	0x0004	/* do not send a I2C start before message */
	uint16_t	len;	/* msg length */
	uint8_t *	buf;
};

struct iiccmd {
	u_char slave;
	int count;
	int last;
	char *buf;
};

struct iic_rdwr_data {
	struct iic_msg *msgs;
	uint32_t nmsgs;
};

#define I2CSTART	_IOW('i', 1, struct iiccmd)	/* start condition */
#define I2CSTOP		_IO('i', 2)			/* stop condition */
#define I2CRSTCARD	_IOW('i', 3, struct iiccmd)	/* reset the card */
#define I2CWRITE	_IOW('i', 4, struct iiccmd)	/* send data */
#define I2CREAD		_IOW('i', 5, struct iiccmd)	/* receive data */
#define I2CRDWR		_IOW('i', 6, struct iic_rdwr_data)	/* General read/write interface */
#define I2CRPTSTART	_IOW('i', 7, struct iiccmd)	/* repeated start */

#endif


code:
/*-
 * Copyright (c) 1998 Nicolas Souchu
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: release/9.0.0/sys/dev/iicbus/iicbus.h 181304 2008-08-04 21:03:06Z jhb $
 *
 */
#ifndef __IICBUS_H
#define __IICBUS_H

#include <sys/_lock.h>
#include <sys/_mutex.h>

#define IICBUS_IVAR(d) (struct iicbus_ivar *) device_get_ivars(d)
#define IICBUS_SOFTC(d) (struct iicbus_softc *) device_get_softc(d)

struct iicbus_softc
{
	device_t dev;		/* Myself */
	device_t owner;		/* iicbus owner device structure */
	u_char started;		/* address of the 'started' slave
				 * 0 if no start condition succeeded */
	struct mtx lock;
};

struct iicbus_ivar
{
	uint32_t	addr;
};

enum {
	IICBUS_IVAR_ADDR		/* Address or base address */
};

#define IICBUS_ACCESSOR(A, B, T)					\
	__BUS_ACCESSOR(iicbus, A, IICBUS, B, T)

IICBUS_ACCESSOR(addr,		ADDR,		uint32_t)

#define	IICBUS_LOCK(sc)			mtx_lock(&(sc)->lock)
#define	IICBUS_UNLOCK(sc)      		mtx_unlock(&(sc)->lock)
#define	IICBUS_ASSERT_LOCKED(sc)       	mtx_assert(&(sc)->lock, MA_OWNED)

extern int iicbus_generic_intr(device_t dev, int event, char *buf);

extern driver_t iicbus_driver;
extern devclass_t iicbus_devclass;

#endif


code:
/*-
 * Copyright (c) 1998, 2001 Nicolas Souchu
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: release/9.0.0/sys/dev/iicbus/iiconf.h 164901 2006-12-05 06:19:36Z imp $
 */
#ifndef __IICONF_H
#define __IICONF_H

#include <sys/queue.h>
#include <dev/iicbus/iic.h>

#define IICPRI (PZERO+8)		/* XXX sleep/wakeup queue priority */

#define LSB 0x1

/*
 * How tsleep() is called in iic_request_bus().
 */
#define IIC_DONTWAIT	0
#define IIC_NOINTR	0
#define IIC_WAIT	0x1
#define IIC_INTR	0x2

/*
 * i2c modes
 */
#define IIC_MASTER	0x1
#define IIC_SLAVE	0x2
#define IIC_POLLED	0x4

/*
 * i2c speed
 */
#define IIC_UNKNOWN	0x0
#define IIC_SLOW	0x1
#define IIC_FAST	0x2
#define IIC_FASTEST	0x3

#define IIC_LAST_READ	0x1

/*
 * callback index
 */
#define IIC_REQUEST_BUS	0x1
#define IIC_RELEASE_BUS	0x2

/*
 * interrupt events
 */
#define INTR_GENERAL	0x1	/* general call received */
#define INTR_START	0x2	/* the I2C interface is addressed */
#define INTR_STOP	0x3	/* stop condition received */
#define INTR_RECEIVE	0x4	/* character received */
#define INTR_TRANSMIT	0x5	/* character to transmit */
#define INTR_ERROR	0x6	/* error */
#define INTR_NOACK	0x7	/* no ack from master receiver */

/*
 * adapter layer errors
 */
#define IIC_NOERR	0x0	/* no error occured */
#define IIC_EBUSERR	0x1	/* bus error */
#define IIC_ENOACK	0x2	/* ack not received until timeout */
#define IIC_ETIMEOUT	0x3	/* timeout */
#define IIC_EBUSBSY	0x4	/* bus busy */
#define IIC_ESTATUS	0x5	/* status error */
#define IIC_EUNDERFLOW	0x6	/* slave ready for more data */
#define IIC_EOVERFLOW	0x7	/* too much data */
#define IIC_ENOTSUPP	0x8	/* request not supported */
#define IIC_ENOADDR	0x9	/* no address assigned to the interface */

extern int iicbus_request_bus(device_t, device_t, int);
extern int iicbus_release_bus(device_t, device_t);
extern device_t iicbus_alloc_bus(device_t);

extern void iicbus_intr(device_t, int, char *);

extern int iicbus_null_repeated_start(device_t, u_char);
extern int iicbus_null_callback(device_t, int, caddr_t);

#define iicbus_reset(bus,speed,addr,oldaddr) \
	(IICBUS_RESET(device_get_parent(bus), speed, addr, oldaddr))

/* basic I2C operations */
extern int iicbus_started(device_t);
extern int iicbus_start(device_t, u_char, int);
extern int iicbus_stop(device_t);
extern int iicbus_repeated_start(device_t, u_char, int);
extern int iicbus_write(device_t, const char *, int, int *, int);
extern int iicbus_read(device_t, char *, int, int *, int, int);

/* single byte read/write functions, start/stop not managed */
extern int iicbus_write_byte(device_t, char, int);
extern int iicbus_read_byte(device_t, char *, int);

/* Read/write operations with start/stop conditions managed */
extern int iicbus_block_write(device_t, u_char, char *, int, int *);
extern int iicbus_block_read(device_t, u_char, char *, int, int *);

/* vectors of iic operations to pass to bridge */
int iicbus_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs);
int iicbus_transfer_gen(device_t bus, struct iic_msg *msgs, uint32_t nmsgs);

#define IICBUS_MODVER	1
#define IICBUS_MINVER	1
#define IICBUS_MAXVER	1
#define IICBUS_PREFVER	IICBUS_MODVER

extern driver_t iicbb_driver;
extern devclass_t iicbb_devclass;

#define IICBB_MODVER	1
#define IICBB_MINVER	1
#define IICBB_MAXVER	1
#define IICBB_PREFVER	IICBB_MODVER

#endif


code:
/*-
 * Copyright (c) 2010 Marcel Moolenaar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: release/9.0.0/sys/dev/io/iodev.h 207329 2010-04-28 15:38:01Z attilio $
 */

#ifndef _DEV_IODEV_H_
#define	_DEV_IODEV_H_

#define	IODEV_PIO_READ		0
#define	IODEV_PIO_WRITE		1

struct iodev_pio_req {
	u_int access;
	u_int port;
	u_int width;
	u_int val;
};

#define	IODEV_PIO	_IOWR('I', 0, struct iodev_pio_req)

#endif /* _DEV_IODEV_H_ */