Copy exact Vela configuration and run_vela function from SR app to fix compilation issues

app.py

@@ -41,22 +41,7 @@ print(f"Vela-optimized model also available: {VELA_MODEL_FILE}")
 # Force rebuild with modern design
 print(f"Repository: {MODEL_REPO}")
 
-# Create Vela config file
-config_content = """[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.05_GBs]
-core_clock=400e6
-axi0_port=Sram
-axi0_max_outstanding=32
-sram_clock_scale=1.0
-axi1_port=OffChipFlash
-Sram=3.2GB
-OnChipFlash=0.05GB
-OffChipFlash=1GB
-Cmd_Buf_Alignment=4
-Cmd_Buf_Size=65536
-"""
-
-with open(DEFAULT_CONFIG, 'w') as f:
-    f.write(config_content)
+# Vela config file is now copied from SR app
 
 def extract_summary_from_log(log_text):
     summary_keys = [
@@ -79,27 +64,24 @@ def extract_summary_from_log(log_text):
             summary.append((key, value))
     return summary
 
-def run_vela_analysis(model_path):
-    """Run Vela compiler on the model and extract performance metrics"""
+def run_vela(model_file):
     accel = "ethos-u55-128"
     optimise = "Size"
     mem_mode = "Sram_Only"
     sys_config = "Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.05_GBs"
     tmpdir = tempfile.mkdtemp()
-    
     try:
         # Use the original uploaded model filename
-        original_model_name = os.path.basename(model_path)
-        temp_model_path = os.path.join(tmpdir, original_model_name)
-        shutil.copy(model_path, temp_model_path)
-        
-        # Copy config file
+        original_model_name = os.path.basename(model_file)
+        model_path = os.path.join(tmpdir, original_model_name)
+        shutil.copy(model_file, model_path)
+
         config_path = os.path.join(tmpdir, DEFAULT_CONFIG)
         shutil.copy(DEFAULT_CONFIG, config_path)
-        
+
         output_dir = os.path.join(tmpdir, "vela_out")
         os.makedirs(output_dir, exist_ok=True)
-        
+
         cmd = [
             "vela",
             f"--accelerator-config={accel}",
@@ -107,15 +89,15 @@ def run_vela_analysis(model_path):
             f"--config={config_path}",
             f"--memory-mode={mem_mode}",
             f"--system-config={sys_config}",
-            temp_model_path,
+            model_path,
             "--verbose-cycle-estimate",
             "--verbose-performance",
             f"--output-dir={output_dir}"
         ]
-        
+
         result = subprocess.run(cmd, capture_output=True, text=True, check=True)
         vela_stdout = result.stdout
-        
+
         # Check for unsupported model patterns in logs
         unsupported_patterns = [
             "Warning: Unsupported TensorFlow Lite semantics",
@@ -123,104 +105,101 @@ def run_vela_analysis(model_path):
             "Neural network macs                                 0 MACs/batch"
         ]
         if any(pat in vela_stdout for pat in unsupported_patterns):
-            return {}, "This model has unsupported layers and needs investigation based on layers."
-        
-        # Add model filename to output
-        model_filename = os.path.basename(model_path)
+            summary_html = (
+                "<div style='background:#fff3f3;border-radius:14px;padding:24px 18px 18px 18px;"
+                "max-width:430px;min-width:320px;width:100%;margin:auto;color:#d32f2f;font-family:sans-serif;"
+                "font-size:1.1em;text-align:left;font-weight:600;'>"
+                "This model has unsupported layers and needs investigation based on layers.<br>"
+                "Please use Vela compiler on your Host Machine for further analysis."
+                "</div>"
+            )
+            # Try to provide per-layer.csv if available for download
+            per_layer_csv = None
+            for log_fname in os.listdir(output_dir):
+                if log_fname.endswith("per-layer.csv"):
+                    per_layer_csv = os.path.join("/tmp", log_fname)
+                    shutil.copy(os.path.join(output_dir, log_fname), per_layer_csv)
+                    break
+            return summary_html, None, per_layer_csv
+
+        model_filename = os.path.basename(model_file)
         if model_filename:
             vela_stdout = vela_stdout.replace(
                 "Network summary for",
                 f"Network summary for {model_filename} ("
             )
-        
-        # Extract summary metrics
+
         summary_items = extract_summary_from_log(vela_stdout)
+        # Convert summary_items to dict for easy access
         summary_dict = dict(summary_items) if summary_items else {}
-        
-        # Look for compiled model
-        compiled_model_path = None
-        per_layer_csv = None
-        
+
+        # Build 4 cards for results
+        def clean_ops(val):
+            # Remove '=' and leading/trailing spaces
+            return val.lstrip("= ").strip() if isinstance(val, str) else val
+
+        summary_html = (
+            "<div style='background:#1e1e2f;border-radius:18px;padding:18px 18px 12px 18px;"
+            "max-width:430px;min-width:320px;width:100%;margin:auto;color:#eee;font-family:sans-serif;'>"
+            "<h3 style='margin-top:0;margin-bottom:12px;font-size:1.35em;color:#00b0ff;text-align:left;'>Estimated Results on SR110</h3>"
+            "<div style='display:flex;flex-wrap:wrap;gap:10px;justify-content:center;'>"
+            # Card 1: Accelerator
+            "<div style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>"
+            "<div style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>🚀 Accelerator</div>"
+            f"<div style='margin-bottom:2px;'><span style='color:#ccc;'>Configuration:</span> <span style='color:#fff;font-weight:500'>{summary_dict.get('Accelerator configuration','-')}</span></div>"
+            f"<div><span style='color:#ccc;'>Accelerator clock:</span> <span style='color:#fff;font-weight:500'>{summary_dict.get('Accelerator clock','-')}</span></div>"
+            "</div>"
+            # Card 2: Memory Usage
+            "<div style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>"
+            "<div style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>💾 Memory Usage</div>"
+            f"<div style='margin-bottom:2px;'><span style='color:#ccc;'>Total SRAM:</span> <span style='color:#fff;font-weight:500'>{summary_dict.get('Total SRAM used','-')}</span></div>"
+            f"<div><span style='color:#ccc;'>Total On-chip Flash:</span> <span style='color:#fff;font-weight:500'>{summary_dict.get('Total On-chip Flash used','-')}</span></div>"
+            "</div>"
+            # Card 3: Operator Distribution
+            "<div style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>"
+            "<div style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>📈 Operator Distribution</div>"
+            f"<div style='margin-bottom:2px;'><span style='color:#ccc;'>CPU Operators:</span> <span style='color:#fff;font-weight:500'>{clean_ops(summary_dict.get('CPU operators','-'))}</span></div>"
+            f"<div><span style='color:#ccc;'>NPU Operators:</span> <span style='color:#fff;font-weight:500'>{clean_ops(summary_dict.get('NPU operators','-'))}</span></div>"
+            "</div>"
+            # Card 4: Performance
+            "<div style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>"
+            "<div style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>⚡ Performance</div>"
+            f"<div><span style='color:#ccc;'>Inference time:</span> <span style='color:#fff;font-weight:500'>{summary_dict.get('Inference time','-')}</span></div>"
+            "</div>"
+            "</div></div>"
+        ) if summary_items else "<div style='color:red'>Summary info not found in log.</div>"
+
         for fname in os.listdir(output_dir):
-            if fname.endswith("_vela.tflite"):
+            if fname.endswith("vela.tflite"):
                 final_path = os.path.join("/tmp", fname)
                 shutil.copy(os.path.join(output_dir, fname), final_path)
-                compiled_model_path = final_path
-            elif fname.endswith("per-layer.csv"):
-                csv_path = os.path.join("/tmp", fname)
-                shutil.copy(os.path.join(output_dir, fname), csv_path)
-                per_layer_csv = csv_path
-        
-        return summary_dict, None, compiled_model_path, per_layer_csv
-        
-    except subprocess.CalledProcessError as e:
-        return {}, f"Vela compilation failed: {e.stderr}", None, None
-    except Exception as e:
-        return {}, f"Error running Vela: {str(e)}", None, None
+                # Find per-layer.csv file for logs
+                per_layer_csv = None
+                for log_fname in os.listdir(output_dir):
+                    if log_fname.endswith("per-layer.csv"):
+                        per_layer_csv = os.path.join("/tmp", log_fname)
+                        shutil.copy(os.path.join(output_dir, log_fname), per_layer_csv)
+                        break
+                return summary_html, final_path, per_layer_csv
+
+        # If no tflite, still try to return per-layer.csv if present
+        per_layer_csv = None
+        for log_fname in os.listdir(output_dir):
+            if log_fname.endswith("per-layer.csv"):
+                per_layer_csv = os.path.join("/tmp", log_fname)
+                shutil.copy(os.path.join(output_dir, log_fname), per_layer_csv)
+                break
+        return summary_html, None, per_layer_csv
     finally:
-        shutil.rmtree(tmpdir, ignore_errors=True)
+        shutil.rmtree(tmpdir)
 
-def generate_vela_html(summary_dict, error_msg=None):
-    """Generate HTML for Vela performance results"""
-    if error_msg:
-        return f"""
-        <div style='background:#fff3f3;border-radius:14px;padding:24px 18px 18px 18px;
-        max-width:430px;min-width:320px;width:100%;margin:auto;color:#d32f2f;font-family:sans-serif;
-        font-size:1.1em;text-align:center;font-weight:600;'>
-        Vela analysis failed: {error_msg}<br>
-        Showing default values.
-        </div>
-        """
-    
-    # Helper function to clean operator values
-    def clean_ops(val):
-        return val.lstrip("= ").strip() if isinstance(val, str) else val
-    
-    # Get values from Vela analysis or use defaults
-    accel_config = summary_dict.get('Accelerator configuration', 'Ethos_U55_128')
-    accel_clock = summary_dict.get('Accelerator clock', '400 MHz')
-    sram_used = summary_dict.get('Total SRAM used', '353.50 KiB')
-    flash_used = summary_dict.get('Total On-chip Flash used', '3614.39 KiB')
-    cpu_ops = clean_ops(summary_dict.get('CPU operators', '0 (0.0%)'))
-    npu_ops = clean_ops(summary_dict.get('NPU operators', '95 (100.0%)'))
-    inference_time = summary_dict.get('Inference time', '15.14 ms')
-    
-    return f"""
-    <div style='background:#1e1e2f;border-radius:18px;padding:18px 18px 12px 18px;
-    max-width:430px;min-width:320px;width:100%;margin:auto;color:#eee;font-family:sans-serif;'>
-        <h3 style='margin-top:0;margin-bottom:12px;font-size:1.35em;color:#00b0ff;text-align:left;'>Estimated Results on SR110</h3>
-        <div style='display:flex;flex-wrap:wrap;gap:10px;justify-content:center;'>
-            <!-- Card 1: Accelerator -->
-            <div style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>
-                <div style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>🚀 Accelerator</div>
-                <div style='margin-bottom:2px;'><span style='color:#ccc;'>Configuration:</span> <span style='color:#fff;font-weight:500'>{accel_config}</span></div>
-                <div><span style='color:#ccc;'>Accelerator clock:</span> <span style='color:#fff;font-weight:500'>{accel_clock}</span></div>
-            </div>
-            <!-- Card 2: Memory Usage -->
-            <div style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>
-                <div style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>💾 Memory Usage</div>
-                <div style='margin-bottom:2px;'><span style='color:#ccc;'>Total SRAM:</span> <span style='color:#fff;font-weight:500'>{sram_used}</span></div>
-                <div><span style='color:#ccc;'>Total On-chip Flash:</span> <span style='color:#fff;font-weight:500'>{flash_used}</span></div>
-            </div>
-            <!-- Card 3: Operator Distribution -->
-            <div style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>
-                <div style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>📈 Operator Distribution</div>
-                <div style='margin-bottom:2px;'><span style='color:#ccc;'>CPU Operators:</span> <span style='color:#fff;font-weight:500'>{cpu_ops}</span></div>
-                <div><span style='color:#ccc;'>NPU Operators:</span> <span style='color:#fff;font-weight:500'>{npu_ops}</span></div>
-            </div>
-            <!-- Card 4: Performance -->
-            <div style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>
-                <div style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>⚡ Performance</div>
-                <div><span style='color:#ccc;'>Inference time:</span> <span style='color:#fff;font-weight:500'>{inference_time}</span></div>
-            </div>
-        </div>
-    </div>
-    """
 
 # Run Vela analysis on startup and cache results
 print("Running Vela analysis on MobileNetV2 model...")
-vela_results, vela_error, compiled_model, per_layer_csv = run_vela_analysis(model_path)
-vela_html = generate_vela_html(vela_results, vela_error)
+try:
+    vela_html, compiled_model, per_layer_csv = run_vela(model_path)
+except Exception as e:
+    vela_html = f"<div style='color:red'>Vela analysis failed: {str(e)}</div>"
 
 def preprocess_image(image):
     """
@@ -324,24 +303,41 @@ def load_example_image(example_path):
 def compile_uploaded_model(model_file):
     """Compile uploaded model with Vela and return results"""
     if model_file is None:
-        error_html = generate_vela_html({}, "No model file uploaded.")
+        error_html = (
+            "<div style='background:#fff3f3;border-radius:14px;padding:24px 18px 18px 18px;"
+            "max-width:430px;min-width:320px;width:100%;margin:auto;color:#d32f2f;font-family:sans-serif;"
+            "font-size:1.1em;text-align:center;font-weight:600;'>"
+            "No model file uploaded."
+            "</div>"
+        )
         return (
             error_html,
             gr.update(visible=False, value=None),
             gr.update(visible=False, value=None)
         )
     
-    # Run Vela analysis on uploaded model
-    vela_results, vela_error, compiled_model_path, per_layer_csv = run_vela_analysis(model_file)
-    
-    # Generate results HTML
-    results_html = generate_vela_html(vela_results, vela_error)
-    
-    return (
-        results_html,
-        gr.update(visible=compiled_model_path is not None, value=compiled_model_path),
-        gr.update(visible=per_layer_csv is not None, value=per_layer_csv)
-    )
+    try:
+        # Run Vela analysis on uploaded model
+        results_html, compiled_model_path, per_layer_csv = run_vela(model_file)
+        
+        return (
+            results_html,
+            gr.update(visible=compiled_model_path is not None, value=compiled_model_path),
+            gr.update(visible=per_layer_csv is not None, value=per_layer_csv)
+        )
+    except Exception as e:
+        error_html = (
+            "<div style='background:#fff3f3;border-radius:14px;padding:24px 18px 18px 18px;"
+            "max-width:430px;min-width:320px;width:100%;margin:auto;color:#d32f2f;font-family:sans-serif;"
+            "font-size:1.1em;text-align:center;font-weight:600;'>"
+            f"Vela compilation failed: {str(e)}"
+            "</div>"
+        )
+        return (
+            error_html,
+            gr.update(visible=False, value=None),
+            gr.update(visible=False, value=None)
+        )
 
 # Create Gradio interface
 with gr.Blocks(

u55_eval_with_TA_config_400_and_200_MHz.ini

@@ -0,0 +1,565 @@
+; Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved.
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the License); you may
+; not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+
+; -----------------------------------------------------------------------------
+; Vela configuration file
+
+; -----------------------------------------------------------------------------
+; System Configuration
+
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (3.2 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_3.2_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=1.0
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=12
+OffChipFlash_write_latency=12
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (1.6 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_1.6_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.5
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=15
+OffChipFlash_write_latency=15
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "2000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.8 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.8_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.25
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=18
+OffChipFlash_write_latency=18
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "1000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.4 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.4_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.125
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=24
+OffChipFlash_write_latency=24
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "500"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.2 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.2_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0625
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=36
+OffChipFlash_write_latency=36
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "250"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.1 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.1_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0312
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=60
+OffChipFlash_write_latency=60
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "125"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.05 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.05_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0156
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=108
+OffChipFlash_write_latency=108
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "62"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.025 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.025_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0078
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=204
+OffChipFlash_write_latency=204
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "31"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+
+
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (1.6 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_1.6_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=1.0
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=12
+OffChipFlash_write_latency=12
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.8 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.8_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.5
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=15
+OffChipFlash_write_latency=15
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "2000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.4 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.4_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.25
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=18
+OffChipFlash_write_latency=18
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "1000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.2 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.2_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.125
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=24
+OffChipFlash_write_latency=24
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "500"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.1 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.1_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0625
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=36
+OffChipFlash_write_latency=36
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "250"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.05 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.05_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0312
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=60
+OffChipFlash_write_latency=60
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "125"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.025 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.025_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0156
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=108
+OffChipFlash_write_latency=108
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "62"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.0125 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.0125_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0078
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=204
+OffChipFlash_write_latency=204
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "31"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+
+
+; -----------------------------------------------------------------------------
+; Memory Mode
+
+; SRAM Only: only one AXI port is used and the SRAM is used for all storage
+[Memory_Mode.Sram_Only]
+const_mem_area=Axi0
+arena_mem_area=Axi0
+cache_mem_area=Axi0
+
+; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software
+; The non-SRAM memory is assumed to be read-only
+[Memory_Mode.Shared_Sram]
+const_mem_area=Axi1
+arena_mem_area=Axi0
+cache_mem_area=Axi0
+
+; Dedicated SRAM: the SRAM (384KB) is only for use by the Ethos-U
+; The non-SRAM memory is assumed to be read-writeable
+[Memory_Mode.Dedicated_Sram]
+const_mem_area=Axi1
+arena_mem_area=Axi1
+cache_mem_area=Axi0
+arena_cache_size=393216
+
+; Dedicated SRAM 512KB: the SRAM (512KB) is only for use by the Ethos-U
+; The non-SRAM memory is assumed to be read-writeable
+[Memory_Mode.Dedicated_Sram_512KB]
+inherit=Memory_Mode.Dedicated_Sram
+arena_cache_size=524288