Datasets:
id stringlengths 7 11 | instruction stringlengths 116 4.32k | output stringlengths 599 7.64k | tb stringlengths 1.41k 14k | tb_result stringlengths 200 2.1M |
|---|---|---|---|---|
entry_5 | Please act as a professional Verilog designer. Your task is to create a Verilog module that implements a clock gating cell.
A clock gating cell is a type of digital circuit that is used to reduce power consumption in a design by gating the clock signal to a block of logic.
Your module should have the following inputs ... | <think>
1. **Requirement Analysis:**
The cell must pass `clk` to `clk_out` when `enable` is active and force `clk_out` low otherwise. Enable transitions during the clock’s high phase must not create glitches.
2. **Logical Design Decisions:**
`enable` is sampled on the falling edge of `clk` into `enable_ff`. ... | `timescale 1ns/1ps
module clock_gating_cell_tb;
reg clk;
reg enable;
wire clk_out;
integer fd;
integer errors;
integer i;
reg expected_enable;
reg next_enable;
reg finished;
clock_gating_cell dut (
.clk (clk),
.enable (enable),
.clk_out (clk_out... | 1 0 0
1 0 0
0 0 0
1 0 0
1 1 0
0 1 0
1 1 1
1 1 1
0 1 0
1 1 1
1 0 1
0 0 0
1 0 0
1 1 0
0 1 0
1 1 1
1 0 1
0 0 0
1 0 0
1 0 0
0 0 0
1 0 0
1 1 0
0 1 0
1 1 1
1 0 1
0 0 0
1 0 0
1 1 0
0 1 0
1 1 1
1 1 1
0 1 0
1 1 1
1 0 1
0 0 0
1 0 0
1 1 0
0 1 0
1 1 1
1 0 1
0 0 0
1 0 0
1 0 0
0 0 0
1 0 0
1 1 0
0 1 0
1 1 1
1 0 1
0 0 0
1 0 0
1 1 0
0 ... |
entry_6 |
You are tasked with designing a module that takes in a 4-bit binary number and outputs its decimal equivalent. The module should be named "bin2dec" and should have the following interface:
```
module bin2dec(
input [3:0] bin,
output reg [3:0] dec
);
```
The input "bin" is a 4-bit binary number and the outpu... | <think>
1. **Requirement Analysis**
- The module accepts a 4-bit input `bin`, representing values from 0 to 15.
- It produces a 4-bit output `dec` containing the same numeric value.
- The required conversion is the weighted sum:
`bin[3]*8 + bin[2]*4 + bin[1]*2 + bin[0]`.
2. **Logical Design Decisions**
... | `timescale 1ns/1ps
module bin2dec_tb;
reg [3:0] bin;
wire [3:0] dec;
integer fd;
integer i;
integer errors;
reg [3:0] expected;
bin2dec dut (
.bin(bin),
.dec(dec)
);
task check_error;
input integer case_num;
input [3:0] expected_value;
be... | 0000 0000
0001 0001
0010 0010
0011 0011
0100 0100
0101 0101
0110 0110
0111 0111
1000 1000
1001 1001
1010 1010
1011 1011
1100 1100
1101 1101
1110 1110
1111 1111
0000 0000
0001 0001
0010 0010
0011 0011
0100 0100
0101 0101
0110 0110
0111 0111
1000 1000
1001 1001
1010 1010
1011 1011
1100 1100
1101 1101
1110 1110
1111 1111
... |
entry_7 | Please act as a professional Verilog designer. Your task is to create a Verilog module that implements a comparator block.
A comparator block is a type of digital circuit that compares two input values and outputs a signal indicating whether one value is greater than, equal to, or less than the other value.
Your modu... | <think>
1. **Requirement analysis:** Compare unsigned inputs `a` and `b`, which may have independently parameterized widths. Assert exactly one output: `gt` when `a > b`, `eq` when `a == b`, or `lt` when `a < b`.
2. **Logical design decisions:** Clear all outputs at the start of the combinational process. Use mutually... | `timescale 1ns/1ps
module comparator_tb;
parameter integer WIDTH = 8;
parameter integer B_WIDTH = WIDTH;
reg [WIDTH-1:0] a;
reg [B_WIDTH-1:0] b;
wire gt;
wire eq;
wire lt;
integer fd;
integer i;
integer test_count;
integer e... | 00 00 0 1 0
00 00 0 1 0
00 00 0 1 0
00 ff 0 0 1
ff 00 1 0 0
00 ff 0 0 1
01 01 0 1 0
01 00 1 0 0
00 01 0 0 1
01 ff 0 0 1
ff 01 1 0 0
01 fe 0 0 1
02 02 0 1 0
02 00 1 0 0
00 02 0 0 1
02 ff 0 0 1
ff 02 1 0 0
02 fd 0 0 1
03 03 0 1 0
03 00 1 0 0
00 03 0 0 1
03 ff 0 0 1
ff 03 1 0 0
03 fc 0 0 1
04 04 0 1 0
04 00 1 0 0
00 04 0 ... |
entry_8 |
You are tasked with designing a Verilog module that implements a combinational logic circuit. The module should have one output, Y, and five inputs, A1, A2, B1, C1, and D1. The circuit should implement the following logic:
1. Y should be the output of a buffer gate.
2. The input to the buffer gate should be the outpu... | <think>
1. **Requirement analysis:**
The output `Y` must equal the output of a buffer. The buffer input is a four-input NAND whose inputs are `C1`, `B1`, `D1`, and `(A1 OR A2)`. Therefore:
\[
Y = \neg\left(C1 \land B1 \land D1 \land (A1 \lor A2)\right)
\]
2. **Logical design decisions:**
- Use an in... | `timescale 1ns/1ps
module combinational_logic_tb;
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
wire Y;
integer fd;
integer test_count;
integer error_count;
integer i;
combinational_logic dut (
.Y (Y),
.A1 (A1),
.A2 (A2),
.B1 (B1),
.C1 ... | 0 0 0 0 0 1
1 0 0 0 0 1
0 1 0 0 0 1
1 1 0 0 0 1
0 0 1 0 0 1
1 0 1 0 0 1
0 1 1 0 0 1
1 1 1 0 0 1
0 0 0 1 0 1
1 0 0 1 0 1
0 1 0 1 0 1
1 1 0 1 0 1
0 0 1 1 0 1
1 0 1 1 0 1
0 1 1 1 0 1
1 1 1 1 0 1
0 0 0 0 1 1
1 0 0 0 1 1
0 1 0 0 1 1
1 1 0 0 1 1
0 0 1 0 1 1
1 0 1 0 1 1
0 1 1 0 1 1
1 1 1 0 1 1
0 0 0 1 1 1
1 0 0 1 1 1
0 1 0 1 ... |
entry_10 |
You are tasked with designing a data format adapter module that takes in data from an input module and outputs it in a different format to an output module. The input and output modules use different data formats, so the adapter module must convert the data accordingly.
You are provided with a code snippet that inst... | <think>
1. **Requirement Analysis**
- The adapter must pass a `DATA_WIDTH`-bit input stream to an output stream of the same width.
- Data and packet boundary indicators (`startofpacket` and `endofpacket`) must be preserved.
- The output valid signal reflects the input valid signal.
- Backpressure from the d... | `timescale 1ns/1ps
module Computer_System_Video_In_Subsystem_avalon_st_adapter_data_format_adapter_0_tb;
parameter integer DATA_WIDTH = 24;
parameter integer EMPTY_WIDTH = 2;
reg in_clk_0_clk;
reg in_rst_0_reset;
reg [DATA_WIDTH-1:0] in_0_data;
reg ... | 3000 0 1 000000 0 0 0 | 000000 0 0 0 0 0
4000 0 0 123447 1 0 0 | 123447 1 0 0 0 0
5000 1 0 24688e 0 0 0 | 24688e 0 1 0 0 0
6000 1 0 369d35 1 0 0 | 369d35 1 1 0 0 0
7000 1 0 48d11c 0 1 0 | 48d11c 0 0 1 0 0
8000 1 0 5b05e3 1 1 0 | 5b05e3 1 0 1 0 0
9000 1 0 6d3a6a 0 1 0 | 6d3a6a 0 1 1 0 0
10000 0 0 7f6e11 1 1 0 | 7f6e11 1... |
entry_13 |
You are tasked with designing a verilog module that takes in three inputs, A, B, and C, and outputs the maximum value among them. Assume that the inputs are 8-bit unsigned integers.
Design a module named "max_finder" with the following ports:
- input [7:0] A
- input [7:0] B
- input [7:0] C
- output [7:0] max_val
Yo... | <think>
1. **Requirement Analysis**
- The module accepts three 8-bit unsigned inputs: `A`, `B`, and `C`.
- It must produce the maximum of the three on the 8-bit output `max_val`.
- The specified two-stage comparison first selects the maximum of `A` and `B`, then compares that result with `C`.
2. **Logical Des... | `timescale 1ns/1ps
module max_finder_tb;
reg [7:0] A;
reg [7:0] B;
reg [7:0] C;
wire [7:0] max_val;
integer fd;
integer errors;
integer test_count;
integer i;
max_finder dut (
.A (A),
.B (B),
.C (C),
.max_val (max_val)
);
... | 0 0 0 0
1 0 0 1
0 1 0 1
0 0 1 1
1 1 1 1
255 0 0 255
0 255 0 255
0 0 255 255
255 255 255 255
127 128 1 128
128 127 1 128
1 128 127 128
85 170 51 170
170 85 204 204
204 170 85 204
16 32 48 48
48 32 16 48
32 48 16 48
128 128 127 128
128 127 128 128
127 128 128 128
18 52 86 86
86 52 18 86
52 86 18 86
254 253 252 254
252 25... |
entry_15 |
You are tasked with designing a module in Verilog that implements a 4-to-1 multiplexer with an additional control input. The module should have six input ports and one output port, as well as a control input that selects which of the four data inputs is routed to the output. The control input should be a single bit, w... | <think>
1. **Requirement analysis:**
The module has four 8-bit data inputs (`A`–`D`), a 1-bit control input (`ctrl`), and an 8-bit output (`out`). For the defined control values, `ctrl = 0` routes `A` to `out`, while `ctrl = 1` routes `D` to `out`. Although named a 4-to-1 multiplexer, the single-bit control cannot... | `timescale 1ns/1ps
module mux4_ctrl_tb;
reg [7:0] A;
reg [7:0] B;
reg [7:0] C;
reg [7:0] D;
reg ctrl;
wire [7:0] out;
integer fd;
integer error_count;
integer test_count;
integer i;
time start_time;
mux4_ctrl dut (
.A (A),
.B (B),
... | 00000000 00010001 00100010 00110011 0 00000000
01000100 01010101 01100110 01110111 1 01110111
10101010 10111011 11001100 11011101 x zzzzzzzz
00010010 00110100 01010110 01111000 z zzzzzzzz
00000000 00010001 00100010 00110011 0 00000000
00000001 00010010 00100011 00110100 1 00110100
00000010 00010011 00100100 00110101 0 ... |
entry_16 |
You are tasked with designing a module called `minimac2_sync` that synchronizes signals between two clock domains: `sys_clk` and `phy_clk`. The module has the following inputs and outputs:
- `sys_clk`: the clock signal for the system domain
- `phy_rx_clk`: the clock signal for the PHY (physical layer) receive domain... | <think>
1. **Requirement Analysis**
- Synchronize `sys_rx_ready[1:0]` from `sys_clk` to `phy_rx_clk`.
- Synchronize `phy_rx_done[1:0]` and receive counts from `phy_rx_clk` to `sys_clk`.
- Synchronize `sys_tx_start` and transmit count from `sys_clk` to `phy_tx_clk`.
- Synchronize `phy_tx_done` from `phy_tx_c... | `timescale 1ns/1ps
module minimac2_psync_tb;
reg sys_clk;
reg phy_rx_clk;
reg phy_tx_clk;
reg [1:0] sys_rx_ready;
wire [1:0] sys_rx_done;
wire [10:0] sys_rx_count_0;
wire [10:0] sys_rx_count_1;
reg sys_tx_start;
wire sys_tx_done;
reg ... | 1 0 0 00 0 01 00000000011 00000000111 00000001011 0 01 00000000011 00000000111 0 00 0 00000001011 <%b> <%b> <%b>
1 0 1 01 0 00 00000010100 00000100100 00000110110 0 00 00000010100 00000100100 0 01 0 00000110110 <%b> <%b> <%b>
1 1 1 10 0 11 00000100101 00001000001 00001100001 0 11 00000100101 00001000001 0 10 0 00001100... |
entry_17 |
You have been tasked with designing a verilog module that implements a 4-bit adder-subtractor circuit with a control input `mode`. The circuit should have two 4-bit inputs `A` and `B`, and a 1-bit input `mode`. When `mode` is 0, the circuit should add `A` and `B`, and when `mode` is 1, the circuit should subtract `B`... | <think>
1. **Requirement Analysis:**
The module accepts two 4-bit operands, `A` and `B`, plus a control signal `mode`. It produces a 4-bit `result`: addition when `mode` is `0`, and subtraction (`A - B`) when `mode` is `1`.
2. **Logical Design Decisions:**
Use a conditional selection based on `mode`. The exp... | `timescale 1ns/1ps
module adder_subtractor_tb;
reg [3:0] A;
reg [3:0] B;
reg mode;
wire [3:0] result;
integer fd;
integer errors;
integer test_count;
integer i;
integer j;
integer k;
adder_subtractor dut (
.A (A),
.B (B),
.mode ... | 0000 0000 0 0000
0000 0001 0 0001
0000 0010 0 0010
0000 0011 0 0011
0000 0100 0 0100
0000 0101 0 0101
0000 0110 0 0110
0000 0111 0 0111
0000 1000 0 1000
0000 1001 0 1001
0000 1010 0 1010
0000 1011 0 1011
0000 1100 0 1100
0000 1101 0 1101
0000 1110 0 1110
0000 1111 0 1111
0001 0000 0 0001
0001 0001 0 0010
0001 0010 0 00... |
entry_18 | As a professional Verilog designer, create a pipelined module that implements a 4-bit barrel shifter with a shift left, shift right, and rotate right operation. The module should have four inputs (data, shift_left, shift_right, and rotate_right) and one output (shifted_data). When shift_left is high, the output should ... | <think>
1. **Requirement Analysis**
- Accept a 4-bit `data` value and three operation controls.
- Perform a one-bit shift or rotation:
- `shift_left`: shift toward the MSB, insert `0` at bit 0.
- `shift_right`: shift toward the LSB, insert `0` at bit 3.
- `rotate_right`: move bit 0 into bit 3 while... | `timescale 1ns/1ps
module barrel_shifter_4bit_tb;
reg clk;
reg [3:0] data;
reg shift_left;
reg shift_right;
reg rotate_right;
wire [3:0] shifted_data;
integer fd;
integer data_index;
integer control_index;
integer test_count;
integer error_coun... | 1 0000 0 0 0 0000 0000
1 0000 0 0 1 0000 0000
1 0000 0 1 0 0000 0000
1 0000 0 1 1 0000 0000
1 0000 1 0 0 0000 0000
1 0000 1 0 1 0000 0000
1 0000 1 1 0 0000 0000
1 0000 1 1 1 0000 0000
1 0001 0 0 0 0001 0001
1 0001 0 0 1 1000 1000
1 0001 0 1 0 0000 0000
1 0001 0 1 1 0000 0000
1 0001 1 0 0 0010 0010
1 0001 1 0 1 0010 001... |
entry_20 | Create a 4-digit BCD counter module with enable signals for each of the upper three digits. The counter should be implemented using a combination of D flip-flops and a combinational circuit. The output should be in binary format, with q[3:0] representing the ones digit, q[7:4] representing the tens digit, and so on. | <think>
The implementation is correct. A skilled implementation approach would be:
1. **Requirement Analysis**
- Implement a synchronous 4-digit BCD counter.
- `q[3:0]`, `q[7:4]`, `q[11:8]`, and `q[15:12]` represent the ones, tens, hundreds, and thousands BCD digits.
- The ones digit advances every clock.
... | `timescale 1ns/1ps
module bcd_counter_tb;
reg clk;
reg reset;
wire [3:1] ena;
wire [15:0] q;
integer fd;
integer error_count;
integer test_count;
reg finished;
reg [15:0] expected_q;
top_module dut (
.clk (clk),
.reset (reset),
.... | 1 1 000 0000
1 1 000 0000
1 0 000 0001
1 0 000 0002
1 0 000 0003
1 0 000 0004
1 0 000 0005
1 0 000 0006
1 0 000 0007
1 0 000 0008
1 0 001 0009
1 0 000 0010
1 0 000 0011
1 0 000 0012
1 0 000 0013
1 0 000 0014
1 0 000 0015
1 0 000 0016
1 0 000 0017
1 0 000 0018
1 0 001 0019
1 0 000 0020
1 0 000 0021
1 0 000 0022
1 0 000 ... |
entry_21 | Create a module that combines the functionality of the 2:1 multiplexer module and the 4-bit shift register module. The module should have 4 inputs labeled A, B, SEL, and DATA, and 2 outputs labeled Y and Q. The module should behave like a 2:1 multiplexer when SEL is 0, outputting A or B based on the SEL input. When SEL... | <think>
1. **Requirement analysis**
- `Y` is a combinational 2:1 multiplexer output: it selects `A` when `SEL=0` and `B` when `SEL=1`.
- `Q` is a 4-bit register.
- When `RESET` is asserted, `Q` must clear asynchronously.
- On a rising `CLK` edge, when `SEL=1`:
- `LOAD=1` loads `DATA` into `Q`.
- O... | `timescale 1ns/1ps
module combined_mux_shift_register_tb;
reg A;
reg B;
reg SEL;
reg [3:0] DATA;
reg CLK;
reg RESET;
reg LOAD;
reg ENABLE;
wire Y;
wire [3:0] Q;
integer fd;
integer errors;
integer vector_coun... | 0 1 0 0 0 1 0 0 0 0
0 0 0 5 1 0 0 0 0 0
1 0 0 8 1 0 0 0 1 0
0 1 0 b 1 0 0 0 0 0
1 1 0 e 1 0 0 0 1 0
0 0 1 1 1 0 0 0 0 0
1 0 1 4 1 0 0 0 0 0
0 1 1 7 1 0 0 0 1 0
1 1 1 a 1 0 0 0 1 0
0 0 0 d 1 0 1 0 0 0
1 0 0 0 1 0 1 0 1 0
0 1 0 3 1 0 1 0 0 0
1 1 0 6 1 0 1 0 1 0
0 0 1 9 1 0 1 0 0 9
1 0 1 c 1 0 1 0 0 c
0 1 1 f 1 0 1 0 1 f
... |
entry_24 |
You are tasked with designing a simple RAM module in Verilog. The RAM should have a read and write port, with the read and write operations being synchronous to a clock signal. The RAM should have a data width of 8 bits and an address width of 4 bits. The RAM should be initialized to all zeros.
The Verilog module s... | <think>
1. **Requirement analysis:**
The module implements 16 memory locations (`2^4`) with 8-bit data. Writes occur on the rising edge when `wen` is asserted. Reads are synchronous: `rdata` updates on the rising edge using `raddr`. Memory and `rdata` are initialized to zero.
2. **Logical design decisions:**
... | `timescale 1ns/1ps
module ram_rw_tb;
reg clk;
reg [3:0] waddr;
reg [7:0] wdata;
reg wen;
reg [3:0] raddr;
wire [7:0] rdata;
reg [7:0] model_mem [0:15];
integer fd;
integer i;
integer errors;
integer test_count;
integer done;
reg [7:0] expected_dat... | 1 00 00 0 00 00
1 00 00 0 01 00
1 00 00 0 02 00
1 00 00 0 03 00
1 00 00 0 04 00
1 00 00 0 05 00
1 00 00 0 06 00
1 00 00 0 07 00
1 00 00 0 08 00
1 00 00 0 09 00
1 00 00 0 0a 00
1 00 00 0 0b 00
1 00 00 0 0c 00
1 00 00 0 0d 00
1 00 00 0 0e 00
1 00 00 0 0f 00
1 00 03 1 00 03
1 01 14 1 01 14
1 02 25 1 02 25
1 03 36 1 03 36
... |
entry_28 |
You are tasked with designing a verilog module for a 4-input multiplexer. The module should have four input ports, one output port, and an additional select input port to choose which input to output. The select input should be a 2-bit input, with the following encoding:
- 00: output A
- 01: output B
- 10: output C
-... | <think>
1. **Requirement analysis**
The module implements a combinational 4:1 multiplexer:
- `sel = 2'b00` → `Y = A`
- `sel = 2'b01` → `Y = B`
- `sel = 2'b10` → `Y = C`
- `sel = 2'b11` → `Y = D`
The implementation uses only the permitted standard-cell types. The included behavioral cell definitions... | `timescale 1ns/1ps
module sky130_fd_sc_hdll__buf_tb;
reg A;
reg B;
reg C;
reg D;
reg [1:0] sel;
wire Y;
integer fd;
integer errors;
integer test_count;
integer rep;
integer a_i;
integer b_i;
integer c_i;
integer d_i;
integer sel... | 0 0 0 0 0 0 0
0 0 0 0 0 1 0
0 0 0 0 1 0 0
0 0 0 0 1 1 0
0 0 0 1 0 0 0
0 0 0 1 0 1 0
0 0 0 1 1 0 0
0 0 0 1 1 1 1
0 0 1 0 0 0 0
0 0 1 0 0 1 0
0 0 1 0 1 0 1
0 0 1 0 1 1 0
0 0 1 1 0 0 0
0 0 1 1 0 1 0
0 0 1 1 1 0 1
0 0 1 1 1 1 1
0 1 0 0 0 0 0
0 1 0 0 0 1 1
0 1 0 0 1 0 0
0 1 0 0 1 1 0
0 1 0 1 0 0 0
0 1 0 1 0 1 1
0 1 0 1 1 0 ... |
End of preview. Expand in Data Studio
VeriReason Luna Medium 16K
16,075 verified VeriReason-format examples generated from all 26,532 RTL-Coder source rows.
This is a local augmentation using openai/gpt-5.6-luna with reasoning_effort=medium;
it is a separate release from the original VeriReason datasets.
| Split | Examples |
|---|---|
| train | 12,859 |
| validation | 1,608 |
| test | 1,608 |
Use
from datasets import load_dataset
dataset = load_dataset("DanielJeongsooLee/VeriReason-Luna-Medium-16K")
Each row has the original compatible fields: id, instruction, output, tb, tb_result.
output contains a nonempty <think>...</think> explanation and <answer>...</answer> RTL.
tb is the Verilog testbench, and tb_result is its saved simulation output.
JSONL files preserve the corrected local release byte for byte.
Testbench suffix correction (2026-10-01)
This revision removes invalid text after the final endmodule in 770 testbenches
(train 613, validation 88, test 69). The preliminary scan counted 769; a stricter
directive check identified one additional malformed backtick-prefixed suffix.
Valid trailing Verilog directives, comments and
module labels are retained. All 16,075 row IDs, split memberships, row order,
instructions, RTL/reasoning outputs and saved tb_result values are unchanged.
Every changed RTL/TB pair was recompiled and simulated twice, with nonempty,
deterministic results identical to its saved tb_result (at least 100 vectors).
The remaining examples retain their prior strict validation; the full release
was rescanned for invalid tails and split overlap.
The corrected reference dataset
Jongbin-kr/VeriReason-reasoning-reproduced-1513_luna-medium
at revision 238253c738520eb1a0196c618f49e923f458b66d has train 1,513 and validation 189;
All 1,702 reference problems retain their original splits, instructions, RTL/reasoning
and saved results. All five fields match exactly for 1,701 rows. In entry_8440,
this release retains the valid trailing `default_nettype wire directive that
the reference trimmed; executable testbench code through endmodule is identical.
That reference has no test split. None of its problems appears in this release's test.
repair_manifest.json records per-row before/after TB hashes and verification counts.
Original artifacts and the previous Hub revision remain available for provenance.
Generation and validation
The pinned VeriReason generator checks RTL syntax, generates an explanation and may revise RTL,
then generates a testbench conditioned on RTL. Empty explanations are retried at most twice,
and empty or negative final explanations are excluded before testbench generation.
The generation gate requires at least 100 test vectors. Strict validation recompiles RTL/TB,
runs the simulator twice, and checks nonempty, deterministic output against saved tb_result.
API failures and source provenance were audited before merging the surviving examples.
No Qwen filtration or difficulty labels were applied. The final explanation audit has zero
empty/missing <think> sections and zero negative markers.
The saved explanation is a separate model response, not the model's internal reasoning tokens.
Split policy and limits
The existing deterministic split uses seed 42 and groups whitespace-normalized instructions. Earlier train/validation membership is retained; test is taken from fresh train prompt groups and excludes the prior medium train/validation cohort. IDs and normalized instructions do not overlap between splits. Semantic near-duplicates and overlap with external training or evaluation corpora have not been audited. Testbenches are generated from RTL, so passing these checks does not establish independent correctness against the natural-language specification.
Provenance and attribution
- Input: RTL-Coder, commit
b2847073be62d5f1d6d9b17bb247f0cfeb1ce642,dataset/Resyn27k.json. - Generator: VeriReason, commit
d215b7fe1b3db6dd4ca725f7d9399c49414c7531. - Local pipeline: veriReason-dataset,
commit
7a4554ba795be1295885df7460e90e7fa73e6733. - Release date: 2026-10-01. Generation job: 264647; split packaging job: 264648.
provenance.json contains source hashes, generation settings and split checks.
SHA256SUMS covers the public release files. The complete source cohort produced 16,075 survivors
(60.59%); 4,758 saved examples were quarantined and 5,699 source rows produced no saved example.
License information
No new license is assigned by this release. The pinned upstream source checkouts do not include a standalone license file. Rights and applicable terms for upstream material remain with the original projects; see the source repositories linked above.
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