u55_eval_with_TA_config_400_and_200_MHz.ini

; Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
; Licensed under the Apache License, Version 2.0 (the License); you may
; not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.

; -----------------------------------------------------------------------------
; Vela configuration file

; -----------------------------------------------------------------------------
; System Configuration


;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (3.2 GB/s)
[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_3.2_GBs]
core_clock=400e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=1.0
OffChipFlash_burst_length=128
OffChipFlash_read_latency=12
OffChipFlash_write_latency=12

;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")


;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (1.6 GB/s)
[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_1.6_GBs]
core_clock=400e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.5
OffChipFlash_burst_length=128
OffChipFlash_read_latency=15
OffChipFlash_write_latency=15

;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "2000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.8 GB/s)
[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.8_GBs]
core_clock=400e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.25
OffChipFlash_burst_length=128
OffChipFlash_read_latency=18
OffChipFlash_write_latency=18

;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "1000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.4 GB/s)
[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.4_GBs]
core_clock=400e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.125
OffChipFlash_burst_length=128
OffChipFlash_read_latency=24
OffChipFlash_write_latency=24

;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "500"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.2 GB/s)
[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.2_GBs]
core_clock=400e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.0625
OffChipFlash_burst_length=128
OffChipFlash_read_latency=36
OffChipFlash_write_latency=36
;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "250"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.1 GB/s)
[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.1_GBs]
core_clock=400e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.0312
OffChipFlash_burst_length=128
OffChipFlash_read_latency=60
OffChipFlash_write_latency=60
;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "125"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.05 GB/s)
[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.05_GBs]
core_clock=400e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.0156
OffChipFlash_burst_length=128
OffChipFlash_read_latency=108
OffChipFlash_write_latency=108
;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "62"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.025 GB/s)
[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.025_GBs]
core_clock=400e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.0078
OffChipFlash_burst_length=128
OffChipFlash_read_latency=204
OffChipFlash_write_latency=204

;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "31"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")




;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (1.6 GB/s)
[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_1.6_GBs]
core_clock=200e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=1.0
OffChipFlash_burst_length=128
OffChipFlash_read_latency=12
OffChipFlash_write_latency=12

;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")


;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.8 GB/s)
[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.8_GBs]
core_clock=200e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.5
OffChipFlash_burst_length=128
OffChipFlash_read_latency=15
OffChipFlash_write_latency=15

;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "2000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.4 GB/s)
[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.4_GBs]
core_clock=200e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.25
OffChipFlash_burst_length=128
OffChipFlash_read_latency=18
OffChipFlash_write_latency=18

;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "1000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.2 GB/s)
[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.2_GBs]
core_clock=200e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.125
OffChipFlash_burst_length=128
OffChipFlash_read_latency=24
OffChipFlash_write_latency=24

;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "500"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.1 GB/s)
[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.1_GBs]
core_clock=200e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.0625
OffChipFlash_burst_length=128
OffChipFlash_read_latency=36
OffChipFlash_write_latency=36
;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "250"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.05 GB/s)
[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.05_GBs]
core_clock=200e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.0312
OffChipFlash_burst_length=128
OffChipFlash_read_latency=60
OffChipFlash_write_latency=60
;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "125"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.025 GB/s)
[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.025_GBs]
core_clock=200e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.0156
OffChipFlash_burst_length=128
OffChipFlash_read_latency=108
OffChipFlash_write_latency=108
;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "62"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.0125 GB/s)
[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.0125_GBs]
core_clock=200e6
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
Sram_burst_length=32
Sram_read_latency=8
Sram_write_latency=8
OffChipFlash_clock_scale=0.0078
OffChipFlash_burst_length=128
OffChipFlash_read_latency=204
OffChipFlash_write_latency=204

;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")

;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
;set(TA1_RLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
;set(TA1_WLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
;set(TA1_BWCAP       "31"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")



; -----------------------------------------------------------------------------
; Memory Mode

; SRAM Only: only one AXI port is used and the SRAM is used for all storage
[Memory_Mode.Sram_Only]
const_mem_area=Axi0
arena_mem_area=Axi0
cache_mem_area=Axi0

; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software
; The non-SRAM memory is assumed to be read-only
[Memory_Mode.Shared_Sram]
const_mem_area=Axi1
arena_mem_area=Axi0
cache_mem_area=Axi0

; Dedicated SRAM: the SRAM (384KB) is only for use by the Ethos-U
; The non-SRAM memory is assumed to be read-writeable
[Memory_Mode.Dedicated_Sram]
const_mem_area=Axi1
arena_mem_area=Axi1
cache_mem_area=Axi0
arena_cache_size=393216

; Dedicated SRAM 512KB: the SRAM (512KB) is only for use by the Ethos-U
; The non-SRAM memory is assumed to be read-writeable
[Memory_Mode.Dedicated_Sram_512KB]
inherit=Memory_Mode.Dedicated_Sram
arena_cache_size=524288